Bring Raspberry Pi 4 (RPi4) support

Signed-off-by: Lukas Graber <lukas.graber@hensoldt-cyber.de>

configs/seL4Config.cmake

@@ -166,6 +166,7 @@ foreach(
     KernelArmCortexA35
     KernelArmCortexA53
     KernelArmCortexA57
+    KernelArmCortexA72
     KernelArm1136JF_S
     KernelArchArmV6
     KernelArchArmV7a
@@ -202,6 +203,7 @@ config_set(KernelArmCortexA15 ARM_CORTEX_A15 "${KernelArmCortexA15}")
 config_set(KernelArmCortexA35 ARM_CORTEX_A35 "${KernelArmCortexA35}")
 config_set(KernelArmCortexA53 ARM_CORTEX_A53 "${KernelArmCortexA53}")
 config_set(KernelArmCortexA57 ARM_CORTEX_A57 "${KernelArmCortexA57}")
+config_set(KernelArmCortexA72 ARM_CORTEX_A72 "${KernelArmCortexA72}")
 config_set(KernelArm1136JF_S ARM1136JF_S "${KernelArm1136JF_S}")
 config_set(KernelArchArmV6 ARCH_ARM_V6 "${KernelArchArmV6}")
 config_set(KernelArchArmV7a ARCH_ARM_V7A "${KernelArchArmV7a}")
@@ -236,6 +238,8 @@ elseif(KernelArmCortexA53)
     set(KernelArmCPU "cortex-a53" CACHE INTERNAL "")
 elseif(KernelArmCortexA57)
     set(KernelArmCPU "cortex-a57" CACHE INTERNAL "")
+elseif(KernelArmCortexA72)
+    set(KernelArmCPU "cortex-a72" CACHE INTERNAL "")
 elseif(KernelArm1136JF_S)
     set(KernelArmCPU "arm1136jf-s" CACHE INTERNAL "")
 endif()

libsel4/sel4_plat_include/bcm2711/sel4/plat/api/constants.h

@@ -0,0 +1,27 @@
+/*
+ * Copyright 2020, Data61, CSIRO (ABN 41 687 119 230)
+ * Copyright (C) 2021, Hensoldt Cyber GmbH
+ *
+ * SPDX-License-Identifier: BSD-2-Clause
+ */
+#pragma once
+
+#ifdef HAVE_AUTOCONF
+#include <autoconf.h>
+#endif
+
+/* Cortex A72 manual, section 10.3 */
+#define seL4_NumHWBreakpoints (10)
+#define seL4_NumExclusiveBreakpoints (6)
+#define seL4_NumExclusiveWatchpoints (4)
+#ifdef CONFIG_HARDWARE_DEBUG_API
+#define seL4_FirstWatchpoint (6)
+#define seL4_NumDualFunctionMonitors (0)
+#endif
+
+#if CONFIG_WORD_SIZE == 32
+/* First address in the virtual address space that is not accessible to user level */
+#define seL4_UserTop 0xe0000000
+#else
+/* otherwise this is defined at the arch level */
+#endif

src/arch/arm/config.cmake

@@ -23,6 +23,11 @@ elseif(KernelArmCortexA53)
 elseif(KernelArmCortexA57)
     set(KernelArmPASizeBits44 ON)
     math(EXPR KernelPaddrUserTop "(1 << 44) - 1")
+elseif(KernelArmCortexA72)
+    # For Cortex-A72 in AArch64 state, the physical address range is 44 bits
+    # (https://developer.arm.com/documentation/100095/0001/memory-management-unit/about-the-mmu)
+    set(KernelArmPASizeBits44 ON)
+    math(EXPR KernelPaddrUserTop "(1 << 44) - 1")
 endif()
 config_set(KernelArmPASizeBits40 ARM_PA_SIZE_BITS_40 "${KernelArmPASizeBits40}")
 config_set(KernelArmPASizeBits44 ARM_PA_SIZE_BITS_44 "${KernelArmPASizeBits44}")
@@ -83,7 +88,8 @@ config_option(
     KernelArmHypervisorSupport ARM_HYPERVISOR_SUPPORT
     "Build as Hypervisor. Utilise ARM virtualisation extensions to build the kernel as a hypervisor"
     DEFAULT ${default_hyp_support}
-    DEPENDS "KernelArmCortexA15 OR KernelArmCortexA35 OR KernelArmCortexA57 OR KernelArmCortexA53"
+    DEPENDS
+        "KernelArmCortexA15 OR KernelArmCortexA35 OR KernelArmCortexA57 OR KernelArmCortexA53 OR KernelArmCortexA72"
 )
 
 config_option(
@@ -188,7 +194,11 @@ if(
     OR KernelArmCortexA35
     OR KernelArmCortexA53
     OR KernelArmCortexA57
+    OR KernelArmCortexA72
 )
+    # According to https://developer.arm.com/documentation/100095/0001/functional-description/about-the-cortex-a72-processor-functions/components-of-the-processor
+    # the L1 instruction on the Cortex-A72 cache has a 64-byte cache line.
+    # Thus, 6 bits are needed.
     config_set(KernelArmCacheLineSizeBits L1_CACHE_LINE_SIZE_BITS "6")
 elseif(KernelArmCortexA9 OR KernelArm1136JF_S)
     config_set(KernelArmCacheLineSizeBits L1_CACHE_LINE_SIZE_BITS "5")

src/plat/bcm2711/config.cmake

@@ -0,0 +1,51 @@
+#
+# Copyright 2020, Data61, CSIRO (ABN 41 687 119 230)
+# Copyright (C) 2021, Hensoldt Cyber GmbH
+#
+# SPDX-License-Identifier: GPL-2.0-only
+#
+
+cmake_minimum_required(VERSION 3.7.2)
+
+declare_platform(bcm2711 KernelPlatformRpi4 PLAT_BCM2711 KernelArchARM)
+
+if(KernelPlatformRpi4)
+    if("${KernelSel4Arch}" STREQUAL aarch32)
+        declare_seL4_arch(aarch32)
+    elseif("${KernelSel4Arch}" STREQUAL aarch64)
+        declare_seL4_arch(aarch64)
+    else()
+        # set aarch64 as default for RPi4
+        fallback_declare_seL4_arch_default(aarch64)
+    endif()
+    set(KernelArmCortexA72 ON)
+    set(KernelArchArmV8a ON)
+    config_set(KernelARMPlatform ARM_PLAT rpi4)
+    set(KernelArmMachFeatureModifiers "+crc" CACHE INTERNAL "")
+    list(APPEND KernelDTSList "tools/dts/rpi4.dts")
+    list(APPEND KernelDTSList "src/plat/bcm2711/overlay-rpi4.dts")
+
+    # - The clock frequency is 54 MHz as can be seen in bcm2711.dtsi in the
+    # Linux Kernel under clk_osc, thus TIMER_FREQUENCY = 54000000.
+    # - The GIC-400 offers 216 SPI IRQs (MAX_IRQ = 216) as can be seen in the
+    # BCM2711 TRM under chapter 6.3. The GIC-400 implements the GICv2
+    # architecture.
+    # https://www.raspberrypi.org/forums/viewtopic.php?t=244479&start=25#p1499052
+    # - CLK_MAGIC and CLK_SHIFT can be calculated with:
+    #       tools/reciprocal.py --divisor 54000000
+    declare_default_headers(
+        TIMER_FREQUENCY 54000000llu
+        MAX_IRQ 216
+        NUM_PPI 32
+        TIMER drivers/timer/arm_generic.h
+        INTERRUPT_CONTROLLER arch/machine/gic_v2.h
+        KERNEL_WCET 10u
+        CLK_MAGIC 5337599559llu
+        CLK_SHIFT 58u
+    )
+endif()
+
+add_sources(
+    DEP "KernelPlatformRpi4"
+    CFILES src/arch/arm/machine/gic_v2.c src/arch/arm/machine/l2c_nop.c
+)

src/plat/bcm2711/overlay-rpi4.dts

@@ -0,0 +1,24 @@
+/*
+ * Copyright 2020, Data61, CSIRO (ABN 41 687 119 230)
+ * Copyright (C) 2021, Hensoldt Cyber GmbH
+ *
+ * SPDX-License-Identifier: GPL-2.0-only
+ */
+
+/ {
+	chosen {
+		seL4,elfloader-devices =
+		    "serial1";
+
+		seL4,kernel-devices =
+		    "serial1",
+		    &{/soc/interrupt-controller@40041000},
+		    &{/soc/local_intc@40000000},
+		    &{/timer};
+	};
+
+	memory@0 {
+		/* This is configurable in the Pi's config.txt, but we use 128MiB of RAM by default. */
+		reg = <0x00 0x00000000 0x08000000>;
+	};
+};

tools/dts/update-dts.sh

@@ -63,6 +63,7 @@ xilinx/zynqmp-zcu102-rev1.0=zynqmp
 freescale/fsl-imx8mq-evk=imx8mq-evk
 freescale/fsl-imx8mm-evk=imx8mm-evk
 rockchip/rk3399-rockpro64=rockpro64
+broadcom/bcm2711-rpi-4-b=rpi4
 "
 
 extract_dts() {