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Author SHA1 Message Date
Simon Shields
b5c56244f1 Create device untypeds at boot for all arches 
Currently on x86 device untypeds are generated by passing the entire
address space minus any parts that are reserved by the kernel or that
are "real" memory (e.g. kernel image, physical RAM).

On ARM and RISC-V, device untypeds were generated at compile-time from
a device tree. This patch moves ARM and RISC-V to use the same approach
as x86, and moves the code from x86 into a common location that's
shared between the three architectures.

Co-Authored-By: Anna Lyons <anna@gh.st>
 2019-11-12 16:20:07 +11:00
Simon Shields
28c1ff4b4b kernel: set maximum user paddr in build system 
expose the maximum physical address that can be given to userspace
for use in hardware_gen.py
 2019-11-12 16:20:07 +11:00
Simon Shields
75ee55a8fd hardware: expose rpi3 intc region to userspace 
the intc region contains a timer that userspace uses on the MCS kernel.
 2019-11-12 16:18:33 +11:00
Simon Shields
cc655275f4 spike: remove unneeded empty seL4,kernel-devices 
hardware_gen assumes this prop is empty if it isn't specified.
 2019-11-12 16:18:33 +11:00
Simon Shields
294b592bb1 trivial: hardware.yml: clean up indentation 2019-11-12 16:18:33 +11:00
Simon Shields
82084ad92b hardware_schema: simplify and clarify schema 
The two interrupt-related 'macros' are rather confusingly different.
Explain them, rename them and simplify interrupt specification while
we're at it.
 2019-11-12 16:18:33 +11:00
Simon Shields
cdb6a093d4 hardware: remove executeNever 
this is now implicitly true. MMIO regions should always be executeNever.
 2019-11-12 16:18:33 +11:00
Simon Shields
7a26d271c3 hardware: change region logic in hardware yaml 
- we're going to switch to mapping the whole address space, excluding
parts used by the kernel, to userspace. We trust the root server anyway,
so giving it extra (possibly invalid) MMIO space just simplifies stuff
on the kernel end.
- drop the hacky true/false/null 'user' flag in favour of a saner
true/false one.
- remove support for 'default' regions. By default we will pass unused
regions through to userspace.
 2019-11-12 16:18:33 +11:00
Simon Shields
75f2c54b42 tools: rewrite hardware_gen.py 
This is almost a complete rewrite from the old hardware_gen.py.

It separates the 'parse DT' stage from the 'generate output'
devices more strictly, and is hopefully easier to understand and
easier to extend.

We also no longer generate the 'devices' list (in YAML)
or the dev_p_regs array (in C), as the kernel will implicitly
expose all non-RAM untypeds as devices.
 2019-11-12 16:18:33 +11:00
Siwei Zhuang
6e3606d056 RISCV: Add support for Ariane SoC 
Support Ariane SoC platform running on Genesys 2 FPGA board.
 2019-11-05 12:15:31 +11:00
Jimmy Brush
e460b934b1 trivial: fix typos in manual 2019-10-30 00:43:57 -04:00
Corey Lewis
7889580a7d mcs: Refactor reply_push 
This removes an unnecessary if and asssert, and simplifies the proofs.
 2019-10-25 15:41:14 +11:00
Oliver Scott
b5a39a92a9 trivial: update licence 2019-10-25 14:18:20 +11:00
Oliver Scott
9abe8a4f0b add support for rockpro64 
Kernel support for 64 bit rockpro board.
Dts was taken from the linux kernel.
 2019-10-25 14:18:20 +11:00
Axel Heider
5c700c15a2 output: use CR LF as line break and not LF CR 2019-10-25 02:18:02 +02:00
G. Branden Robinson
5e7f50e835 config.cmake: fix typo 
Discovered at IEEE SecDev 2019 when someone asked about binary
verification and optimisation levels.
 2019-10-24 14:23:17 +11:00
Kent McLeod
a5148a1957 exynos: Move mct MCS functions to specific header 
On exynos5 platforms the Arm Generic timer is available and is used for
MCS, but the mct.h is still used as the mct device needs to be
configured to implement the Arm Generic timer. mct.h is a common header
for register definitions while exynos4412-mct.h is used for implementing
timer functions on the exynos4 where the mct doesn't support being the
Arm generic timer.

Also remove misplaced initGenericTimer() declaration.
 2019-10-23 16:30:17 +11:00
Oliver Scott
cd956d5769 bbone-MCS: add mcs 
Add MCS functionality to bboneblack platform.
 2019-10-22 16:31:58 +11:00
Oliver Scott
8fd26bd759 bbone-MCS: kernel switch to dmtimer4 
The kernel was originally using dmtimer0
which had a fixed clock speed not fast enough
for mcs.
 2019-10-22 16:31:58 +11:00
Sylvain Gauthier
4efbd4365e Updated CHANGES file 
Updated CHANGES file to add virt support.
 2019-10-14 15:46:08 +11:00
Sylvain Gauthier
5ffb2a1bc1 Added the new virt platform 
`virt` is a QEMU virtual platform that support 3 ARM CPUs.
 2019-10-14 15:46:08 +11:00
Oliver Scott
7dc6b23ef9 exynos4: MCS timer 
Add required functionality for MCS.
 2019-10-11 11:16:47 +11:00
Yanyan Shen
1cb5887abe trivial: Update CHANGES 2019-10-10 17:26:17 +11:00
Yanyan Shen
834dda6756 trivial: Remove unused code 2019-10-10 17:22:06 +11:00
Yanyan Shen
2719999046 trivial: Fix style 2019-10-10 17:22:06 +11:00
Yanyan Shen
17b6f2a265 trivial: Replace asm with fence_rw_rw() 2019-10-10 17:22:06 +11:00
Yanyan Shen
db3c4ff44f riscv: Guard SMP inlines with the macro 
Guard the added SMP inline functions with the ENABLE_SMP_SUPPORT.
 2019-10-10 17:22:06 +11:00
Yanyan Shen
0a6df5fc87 riscv: Remove IPI functions when SMP is off 
Remove ipi_get_irq() and ipi_clear_irq() when SMP is not enabled.
 2019-10-10 17:22:06 +11:00
Yanyan Shen
e7957006e5 trivial: Correct year 2019-10-10 17:22:06 +11:00
Yanyan Shen
fbc70aa02f riscv: Use inline functions to replace inline asm 
Use inline functions to replace inline assembly.
 2019-10-10 17:22:06 +11:00
Yanyan Shen
b32c0b8dcb riscv: Add fence_r_rw() and fence_w_r() 
Add more memory fences.
 2019-10-10 17:22:06 +11:00
Yanyan Shen
860ab65d01 trivial: Fix compile error when debug is off 2019-10-10 17:22:06 +11:00
Yanyan Shen
a45f389704 trivial: Fix style 2019-10-10 17:22:06 +11:00
Yanyan Shen
582e6e2646 riscv: SMP option 
Allow to enable the SMP option for RISCV.
 2019-10-10 17:22:06 +11:00
Yanyan Shen
a269298c71 riscv: Flush pipeline and instruction cache 
Flush the instruction cache and pipeline when handling
a reschedule IPI.
 2019-10-10 17:22:06 +11:00
Yanyan Shen
4741fb6492 riscv: SMPify booting code 
Add SMP support for booting code.
 2019-10-10 17:22:06 +11:00
Yanyan Shen
fb7dee9a2b riscv: Add Arch_migrateTCB function for SMP 
Add an empty function to pass compilation at the moment.
 2019-10-10 17:22:06 +11:00
Yanyan Shen
fa696b8585 riscv: Get the lock first when handling interrupts 
Get the lock when handling interrupts.
 2019-10-10 17:22:06 +11:00
Yanyan Shen
79e0613c76 riscv: Add IPI support and SMPify IRQ-related code 
Add IPI support and SMPify IRQ-related code.
 2019-10-10 17:22:06 +11:00
Yanyan Shen
b848e58d5a riscv: Add IPI calls and handlers 
Add IPI call functions and handler functions.
 2019-10-10 17:22:06 +11:00
Yanyan Shen
c83a771000 riscv: Print SIP for spurious interrupts 
Add a bit more information for spurious interrupts.
 2019-10-10 17:22:06 +11:00
Yanyan Shen
633412dbf1 riscv: Generalise/SMPify PLIC code 
Add SMP support for PLIC code.
 2019-10-10 17:22:06 +11:00
Yanyan Shen
d1a0de41ff riscv: Split IRQ init to platform and local 
Split IRQ init code to platform-code and per-hart code.
 2019-10-10 17:22:06 +11:00
Yanyan Shen
e1c529caa5 riscv: Add SMP code for ifence/sfence/hwASIDFlush 
If SMP is enabled, sfence/ifence/hwASIDFlush also IPI other
cores.
 2019-10-10 17:22:06 +11:00
Yanyan Shen
07a5a3f5d9 riscv: Add memory fences and local ifence/sfence 
Add memory fences.
Add local ifence and sfence which work on the calling
core only.
 2019-10-10 17:22:06 +11:00
Yanyan Shen
8f7b168a53 riscv: Add SMP data 
Add data for converting logical core ID to hart ID and vice verse.
 2019-10-10 17:22:06 +11:00
Yanyan Shen
5a0d349845 riscv: Include header for SMP macros 
Include header or SMP macros.
 2019-10-10 17:22:06 +11:00
Yanyan Shen
99e9092b23 riscv: Set up the idle threads' per-core stacks 
Use per-core stacks for idle thread stacks.
 2019-10-10 17:22:06 +11:00
Yanyan Shen
1c53fea9d3 riscv: Add L1 cache line size and memory barrier 
Add the L1 cache line size based on HiFive Unleashed.
 2019-10-10 17:22:06 +11:00
Yanyan Shen
934080b7f5 riscv: Add IPI types and arch_pause() function 
Add reschedule and call IPI types.
Add arch_pause() function.
 2019-10-10 17:22:06 +11:00