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exynos: Move mct MCS functions to specific header

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On exynos5 platforms the Arm Generic timer is available and is used for
MCS, but the mct.h is still used as the mct device needs to be
configured to implement the Arm Generic timer. mct.h is a common header
for register definitions while exynos4412-mct.h is used for implementing
timer functions on the exynos4 where the mct doesn't support being the
Arm generic timer.

Also remove misplaced initGenericTimer() declaration.
This commit is contained in:
Kent McLeod
2019-10-23 14:22:46 +11:00
committed by Kent Mcleod
parent cd956d5769
commit a5148a1957
2 changed files with 41 additions and 41 deletions
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41
include/drivers/timer/exynos4412-mct.h
View File

@@ -20,4 +20,45 @@ static inline void resetTimer(void)
mct_reset();
}
#ifdef CONFIG_KERNEL_MCS
/** DONT_TRANSLATE **/
static inline ticks_t getCurrentTime(void)
{
uint32_t hi, hi2, lo;
hi2 = mct->global.cnth;
do {
hi = hi2;
lo = mct->global.cntl;
hi2 = mct->global.cnth;
} while (hi != hi2);
return ((((uint64_t) hi) << 32llu) | (uint64_t) lo);
}
/** DONT_TRANSLATE **/
static inline void setDeadline(ticks_t deadline)
{
/*
* After writing a value to a comp register a bit in the wstat
* register is asserted. A write of 1 clears this bit.
*/
mct->global.comp0h = (uint32_t)(deadline >> 32u);
while (!(mct->global.wstat & GWSTAT_COMP0H));
mct->global.wstat |= GWSTAT_COMP0H;
mct->global.comp0l = (uint32_t) deadline;
while (!(mct->global.wstat & GWSTAT_COMP0L));
mct->global.wstat |= GWSTAT_COMP0L;
}
static inline void ackDeadlineIRQ(void)
{
/* ack everything */
mct_reset();
}
#endif
#endif /* !__DRIVER_TIMER_MCT_EXYNOS4412_H */

41
include/drivers/timer/mct.h
View File

@@ -129,46 +129,5 @@ static inline void mct_clear_write_status(void)
mct->global.cnt_wstat = mct->global.cnt_wstat;
}
#ifdef CONFIG_KERNEL_MCS
/** DONT_TRANSLATE **/
static inline ticks_t getCurrentTime(void)
{
uint32_t hi, hi2, lo;
hi2 = mct->global.cnth;
do {
hi = hi2;
lo = mct->global.cntl;
hi2 = mct->global.cnth;
} while (hi != hi2);
return ((((uint64_t) hi) << 32llu) | (uint64_t) lo);
}
/** DONT_TRANSLATE **/
static inline void setDeadline(ticks_t deadline)
{
/*
* After writing a value to a comp register a bit in the wstat
* register is asserted. A write of 1 clears this bit.
*/
mct->global.comp0h = (uint32_t)(deadline >> 32u);
while (!(mct->global.wstat & GWSTAT_COMP0H));
mct->global.wstat |= GWSTAT_COMP0H;
mct->global.comp0l = (uint32_t) deadline;
while (!(mct->global.wstat & GWSTAT_COMP0L));
mct->global.wstat |= GWSTAT_COMP0L;
}
static inline void ackDeadlineIRQ(void)
{
/* ack everything */
mct_reset();
}
BOOT_CODE void initGenericTimer(void);
#endif
#endif /* __DRIVERS_TIMER_MCT_H */