forked from Imagelibrary/seL4
a5148a1957
On exynos5 platforms the Arm Generic timer is available and is used for MCS, but the mct.h is still used as the mct device needs to be configured to implement the Arm Generic timer. mct.h is a common header for register definitions while exynos4412-mct.h is used for implementing timer functions on the exynos4 where the mct doesn't support being the Arm generic timer. Also remove misplaced initGenericTimer() declaration.
65 lines
1.5 KiB
C
65 lines
1.5 KiB
C
/*
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* Copyright 2017, Data61
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* Commonwealth Scientific and Industrial Research Organisation (CSIRO)
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* ABN 41 687 119 230.
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*
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* This software may be distributed and modified according to the terms of
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* the GNU General Public License version 2. Note that NO WARRANTY is provided.
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* See "LICENSE_GPLv2.txt" for details.
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*
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* @TAG(DATA61_GPL)
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*/
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#ifndef __DRIVER_TIMER_MCT_EXYNOS4412_H
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#define __DRIVER_TIMER_MCT_EXYNOS4412_H
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#include <drivers/timer/mct.h>
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static inline void resetTimer(void)
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{
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mct_reset();
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}
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#ifdef CONFIG_KERNEL_MCS
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/** DONT_TRANSLATE **/
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static inline ticks_t getCurrentTime(void)
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{
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uint32_t hi, hi2, lo;
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hi2 = mct->global.cnth;
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do {
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hi = hi2;
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lo = mct->global.cntl;
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hi2 = mct->global.cnth;
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} while (hi != hi2);
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return ((((uint64_t) hi) << 32llu) | (uint64_t) lo);
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}
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/** DONT_TRANSLATE **/
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static inline void setDeadline(ticks_t deadline)
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{
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/*
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* After writing a value to a comp register a bit in the wstat
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* register is asserted. A write of 1 clears this bit.
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*/
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mct->global.comp0h = (uint32_t)(deadline >> 32u);
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while (!(mct->global.wstat & GWSTAT_COMP0H));
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mct->global.wstat |= GWSTAT_COMP0H;
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mct->global.comp0l = (uint32_t) deadline;
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while (!(mct->global.wstat & GWSTAT_COMP0L));
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mct->global.wstat |= GWSTAT_COMP0L;
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}
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static inline void ackDeadlineIRQ(void)
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{
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/* ack everything */
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mct_reset();
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}
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#endif
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#endif /* !__DRIVER_TIMER_MCT_EXYNOS4412_H */
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