Upgrade to 4.9.4

* libfs/src/dosfs/msdos_create.c: Fix the date/time call order to
        'msdos_date_unix2dos'.

VERSION

@@ -4,4 +4,4 @@
 #  $Id$
 #
 
-RTEMS Version 4.9.1
+RTEMS Version 4.9.4

aclocal/version.m4

@@ -1,4 +1,4 @@
 AC_DEFUN([RTEMS_VERSIONING],
-m4_define([_RTEMS_VERSION],[4.9.1]))
+m4_define([_RTEMS_VERSION],[4.9.4]))
 
 m4_define([RTEMS_API],[4.9])

c/src/ChangeLog

@@ -1,3 +1,14 @@
+2009-03-12	Daniel Hellstrom <daniel@gaisler.com>
+
+	PR 1392/bsps
+	* libchip/i2c/spi-memdrv.c: SPI Memory driver. Fix but where writes
+	over multiple pages results in extra data being written.
+
+2009-01-21	Sebastian Huber <sebastian.huber@embedded-brains.de>
+
+	* libchip/i2c/spi-sd-card.c: Fixed RTEMS_BLKDEV_CAPABILITIES ioctl
+	which caused invalid multiple block writes.
+
 2008-11-13	Sebastian Huber <sebastian.huber@embedded-brains.de>
 
 	* libchip/serial/ns16550.c: Transmit the character in the polled write

c/src/aclocal/version.m4

@@ -1,4 +1,4 @@
 AC_DEFUN([RTEMS_VERSIONING],
-m4_define([_RTEMS_VERSION],[4.9.1]))
+m4_define([_RTEMS_VERSION],[4.9.4]))
 
 m4_define([RTEMS_API],[4.9])

c/src/lib/libbsp/arm/ChangeLog

@@ -1,3 +1,12 @@
+2009-03-12	Joel Sherrill <joel.sherrill@OARcorp.com>
+
+	PR 1385/cpukit
+	* shared/irq/irq_asm.S: When the type rtems_boolean was switched to the
+	C99 bool, the size changed from 4 bytes to 1 byte. The interrupt
+	dispatching code accesses two boolean variables for scheduling
+	purposes and the assembly implementations of this code did not get
+	updated.
+
 2008-08-18	Ralf Corsépius <ralf.corsepius@rtems.org>
 
 	* shared/irq/irq_init.c: Add missing prototypes.

c/src/lib/libbsp/arm/csb336/ChangeLog

@@ -1,3 +1,8 @@
+2009-01-06	Joel Sherrill <joel.sherrill@OARcorp.com>
+
+	PR 1350/bsps
+	* network/lan91c11x.c: Do not write 65th element into 64 element array.
+
 2008-12-08	Ralf Corsépius <ralf.corsepius@rtems.org>
 
 	* bsp_specs: Backport from CVS-HEAD.

c/src/lib/libbsp/arm/csb336/network/lan91c11x.c

@@ -224,9 +224,6 @@ void lan91c11x_write_phy_reg(int reg, uint16_t phydata)
         mask >>= 1;
     }
 
-    /* Final clock bit */
-    bits[clk_idx++] = 0;
-    
     /* Turn off all MII Interface bits */
     lan91c11x_write_reg(LAN91C11X_MGMT, 
                         lan91c11x_read_reg(LAN91C11X_MGMT) & 0xfff0);

c/src/lib/libbsp/arm/gba/ChangeLog

@@ -1,3 +1,12 @@
+2009-03-12	Joel Sherrill <joel.sherrill@OARcorp.com>
+
+	PR 1385/cpukit
+	* irq/irq_asm.S: When the type rtems_boolean was switched to the C99
+	bool, the size changed from 4 bytes to 1 byte. The interrupt
+	dispatching code accesses two boolean variables for scheduling
+	purposes and the assembly implementations of this code did not get
+	updated.
+
 2008-12-08	Ralf Corsépius <ralf.corsepius@rtems.org>
 
 	* bsp_specs: Backport from CVS-HEAD.

c/src/lib/libbsp/arm/gba/console/defaultfont.h

@@ -0,0 +1,601 @@
+/**
+ *  @file defaultfont.c
+ *
+ *  This file contains default font definitions.
+ */
+/*
+ *  RTEMS GBA BSP
+ *
+ *  Copyright (c) 2004  Markku Puro <markku.puro@kopteri.net>
+ *
+ *  The license and distribution terms for this file may be
+ *  found in found in the file LICENSE in this distribution or at
+ *  http://www.rtems.com/license/LICENSE.
+ *
+ *  $Id$
+ */
+
+/** Font array dot value   */
+#define  X  255
+/** Generate font row data */
+#define GEN_FONT_DATA(a,b,c,d)  ( ((d)<<24) | ((c)<<16) | ((b)<<8) | ((a)<<0) )
+/** array for 3x5 font, font screen size is 4x6 */
+static const unsigned long	font3x5[256][6] =
+	{	{		/* ' ' - ascii:0x20 font:0x00   */
+		GEN_FONT_DATA(  0,0,0,0  ),
+		GEN_FONT_DATA(  0,0,0,0  ),
+		GEN_FONT_DATA(  0,0,0,0  ),
+		GEN_FONT_DATA(  0,0,0,0  ),
+		GEN_FONT_DATA(  0,0,0,0  )
+		},{		/* '!' - ascii:0x21 font:0x01   */
+		GEN_FONT_DATA(  0,0,X,0  ),
+		GEN_FONT_DATA(  0,0,X,0  ),
+		GEN_FONT_DATA(  0,0,X,0  ),
+		GEN_FONT_DATA(  0,0,0,0  ),
+		GEN_FONT_DATA(  0,0,X,0  )
+		},{		/* '"' - ascii:0x22 font:0x02   */
+		GEN_FONT_DATA(  0,X,0,X  ),
+		GEN_FONT_DATA(  0,X,0,X  ),
+		GEN_FONT_DATA(  0,0,0,0  ),
+		GEN_FONT_DATA(  0,0,0,0  ),
+		GEN_FONT_DATA(  0,0,0,0  )
+		},{		/* '#' - ascii:0x23 font:0x03   */
+		GEN_FONT_DATA(  0,X,0,X  ),
+		GEN_FONT_DATA(  0,X,X,X  ),
+		GEN_FONT_DATA(  0,X,0,X  ),
+		GEN_FONT_DATA(  0,X,X,X  ),
+		GEN_FONT_DATA(  0,X,0,X  )
+		},{		/* '$' - ascii:0x24 font:0x04    */
+		GEN_FONT_DATA(  0,0,X,X  ),
+		GEN_FONT_DATA(  0,X,X,0  ),
+		GEN_FONT_DATA(  0,0,X,X  ),
+		GEN_FONT_DATA(  0,X,X,0  ),
+		GEN_FONT_DATA(  0,0,X,0  )
+		},{		/* '%' - ascii:0x25 font:0x05   */
+		GEN_FONT_DATA(  0,0,0,X  ),
+		GEN_FONT_DATA(  0,X,0,X  ),
+		GEN_FONT_DATA(  0,0,X,0  ),
+		GEN_FONT_DATA(  0,X,0,X  ),
+		GEN_FONT_DATA(  0,X,0,0  )
+		},{		/* '&' - ascii:0x26 font:0x06   */
+		GEN_FONT_DATA(  0,0,X,X  ),
+		GEN_FONT_DATA(  0,X,0,0  ),
+		GEN_FONT_DATA(  0,0,X,0  ),
+		GEN_FONT_DATA(  0,X,0,X  ),
+		GEN_FONT_DATA(  0,0,X,0  )
+		},{		/* ''' - ascii:0x27 font:0x07   */
+		GEN_FONT_DATA(  0,0,X,0  ),
+		GEN_FONT_DATA(  0,0,X,0  ),
+		GEN_FONT_DATA(  0,0,0,0  ),
+		GEN_FONT_DATA(  0,0,0,0  ),
+		GEN_FONT_DATA(  0,0,0,0  )
+		},{		/* '(' - ascii:0x28 font:0x08   */
+		GEN_FONT_DATA(  0,0,0,X  ),
+		GEN_FONT_DATA(  0,0,X,0  ),
+		GEN_FONT_DATA(  0,0,X,0  ),
+		GEN_FONT_DATA(  0,0,X,0  ),
+		GEN_FONT_DATA(  0,0,0,X  )
+		},{		/* ')' - ascii:0x29 font:0x09   */
+		GEN_FONT_DATA(  0,X,0,0  ),
+		GEN_FONT_DATA(  0,0,X,0  ),
+		GEN_FONT_DATA(  0,0,X,0  ),
+		GEN_FONT_DATA(  0,0,X,0  ),
+		GEN_FONT_DATA(  0,X,0,0  )
+		},{		/* '*' - ascii:0x2A font:0x0A   */
+		GEN_FONT_DATA(  0,0,0,0  ),
+		GEN_FONT_DATA(  0,X,0,X  ),
+		GEN_FONT_DATA(  0,0,X,0  ),
+		GEN_FONT_DATA(  0,X,0,X  ),
+		GEN_FONT_DATA(  0,0,0,0  )
+		},{		/* '+' - ascii:0x2B font:0x0B   */
+		GEN_FONT_DATA(  0,0,0,0  ),
+		GEN_FONT_DATA(  0,0,X,0  ),
+		GEN_FONT_DATA(  0,X,X,X  ),
+		GEN_FONT_DATA(  0,0,X,0  ),
+		GEN_FONT_DATA(  0,0,0,0  )
+		},{		/* '´' - ascii:0x2C font:0x0C   */
+		GEN_FONT_DATA(  0,0,0,X  ),
+		GEN_FONT_DATA(  0,0,X,0  ),
+		GEN_FONT_DATA(  0,0,0,0  ),
+		GEN_FONT_DATA(  0,0,0,0  ),
+		GEN_FONT_DATA(  0,0,0,0  )
+		},{		/* '-' - ascii:0x2D font:0x0D   */
+		GEN_FONT_DATA(  0,0,0,0  ),
+		GEN_FONT_DATA(  0,0,0,0  ),
+		GEN_FONT_DATA(  0,X,X,X  ),
+		GEN_FONT_DATA(  0,0,0,0  ),
+		GEN_FONT_DATA(  0,0,0,0  )
+		},{		/* '.' - ascii:0x2E font:0x0E   */
+		GEN_FONT_DATA(  0,0,0,0  ),
+		GEN_FONT_DATA(  0,0,0,0  ),
+		GEN_FONT_DATA(  0,0,0,0  ),
+		GEN_FONT_DATA(  0,0,0,0  ),
+		GEN_FONT_DATA(  0,0,X,0  ),
+		},{		/* '/' - ascii:0x2F font:0x0F   */
+		GEN_FONT_DATA(  0,0,0,0  ),
+		GEN_FONT_DATA(  0,0,0,X  ),
+		GEN_FONT_DATA(  0,0,X,0  ),
+		GEN_FONT_DATA(  0,X,0,0  ),
+		GEN_FONT_DATA(  X,0,0,0  )
+		},{		/* '0' - ascii:0x30 font:0x10   */
+		GEN_FONT_DATA(  0,X,X,X  ),
+		GEN_FONT_DATA(  0,X,0,X  ),
+		GEN_FONT_DATA(  0,X,0,X  ),
+		GEN_FONT_DATA(  0,X,0,X  ),
+		GEN_FONT_DATA(  0,X,X,X  )
+		},{		/* '1' - ascii:0x31 font:0x11   */
+		GEN_FONT_DATA(  0,0,X,0  ),
+		GEN_FONT_DATA(  0,X,X,0  ),
+		GEN_FONT_DATA(  0,0,X,0  ),
+		GEN_FONT_DATA(  0,0,X,0  ),
+		GEN_FONT_DATA(  0,X,X,X  )
+		},{		/* '2' - ascii:0x32 font:0x12   */
+		GEN_FONT_DATA(  0,X,X,X  ),
+		GEN_FONT_DATA(  0,0,0,X  ),
+		GEN_FONT_DATA(  0,X,X,X  ),
+		GEN_FONT_DATA(  0,X,0,0  ),
+		GEN_FONT_DATA(  0,X,X,X  )
+		},{		/* '3' - ascii:0x33 font:0x13   */
+		GEN_FONT_DATA(  0,X,X,X  ),
+		GEN_FONT_DATA(  0,0,0,X  ),
+		GEN_FONT_DATA(  0,0,X,X  ),
+		GEN_FONT_DATA(  0,0,0,X  ),
+		GEN_FONT_DATA(  0,X,X,X  )
+		},{		/* '4' - ascii:0x34 font:0x14   */
+		GEN_FONT_DATA(  0,X,0,X  ),
+		GEN_FONT_DATA(  0,X,0,X  ),
+		GEN_FONT_DATA(  0,X,X,X  ),
+		GEN_FONT_DATA(  0,0,0,X  ),
+		GEN_FONT_DATA(  0,0,0,X  )
+		},{		/* '5' - ascii:0x35 font:0x15   */
+		GEN_FONT_DATA(  0,X,X,X  ),
+		GEN_FONT_DATA(  0,X,0,0  ),
+		GEN_FONT_DATA(  0,X,X,X  ),
+		GEN_FONT_DATA(  0,0,0,X  ),
+		GEN_FONT_DATA(  0,X,X,X  )
+		},{		/* '6' - ascii:0x36 font:0x16   */
+		GEN_FONT_DATA(  0,X,X,X  ),
+		GEN_FONT_DATA(  0,X,0,0  ),
+		GEN_FONT_DATA(  0,X,X,X  ),
+		GEN_FONT_DATA(  0,X,0,X  ),
+		GEN_FONT_DATA(  0,X,X,X  )
+		},{		/* '7' - ascii:0x37 font:0x17   */
+		GEN_FONT_DATA(  0,X,X,X  ),
+		GEN_FONT_DATA(  0,0,0,X  ),
+		GEN_FONT_DATA(  0,0,X,X  ),
+		GEN_FONT_DATA(  0,0,X,0  ),
+		GEN_FONT_DATA(  0,0,X,0  )
+		},{		/* '8' - ascii:0x38 font:0x18   */
+		GEN_FONT_DATA(  0,X,X,X  ),
+		GEN_FONT_DATA(  0,X,0,X  ),
+		GEN_FONT_DATA(  0,X,X,X  ),
+		GEN_FONT_DATA(  0,X,0,X  ),
+		GEN_FONT_DATA(  0,X,X,X  )
+		},{		/* '9' - ascii:0x39 font:0x19   */
+		GEN_FONT_DATA(  0,X,X,X  ),
+		GEN_FONT_DATA(  0,X,0,X  ),
+		GEN_FONT_DATA(  0,X,X,X  ),
+		GEN_FONT_DATA(  0,0,0,X  ),
+		GEN_FONT_DATA(  0,X,X,X  )
+		},{		/* ':' - ascii:0x3A font:0x1A   */
+		GEN_FONT_DATA(  0,0,0,0  ),
+		GEN_FONT_DATA(  0,0,X,0  ),
+		GEN_FONT_DATA(  0,0,0,0  ),
+		GEN_FONT_DATA(  0,0,X,0  ),
+		GEN_FONT_DATA(  0,0,0,0  ),
+		},{		/* ';' - ascii:0x3B font:0x1B   */
+		GEN_FONT_DATA(  0,0,0,0  ),
+		GEN_FONT_DATA(  0,0,X,0  ),
+		GEN_FONT_DATA(  0,0,0,0  ),
+		GEN_FONT_DATA(  0,0,X,0  ),
+		GEN_FONT_DATA(  0,X,0,0  ),
+		},{		/* '<' - ascii:0x3C font:0x1C   */
+		GEN_FONT_DATA(  0,0,0,X  ),
+		GEN_FONT_DATA(  0,0,X,0  ),
+		GEN_FONT_DATA(  0,X,0,0  ),
+		GEN_FONT_DATA(  0,0,X,0  ),
+		GEN_FONT_DATA(  0,0,0,X  )
+		},{		/* '=' - ascii:0x3D font:0x1D   */
+		GEN_FONT_DATA(  0,0,0,0  ),
+		GEN_FONT_DATA(  0,X,X,X  ),
+		GEN_FONT_DATA(  0,0,0,0  ),
+		GEN_FONT_DATA(  0,X,X,X  ),
+		GEN_FONT_DATA(  0,0,0,0  )
+		},{		/* '>' - ascii:0x3E font:0x1E   */
+		GEN_FONT_DATA(  0,X,0,0  ),
+		GEN_FONT_DATA(  0,0,X,0  ),
+		GEN_FONT_DATA(  0,0,0,X  ),
+		GEN_FONT_DATA(  0,0,X,0  ),
+		GEN_FONT_DATA(  0,X,0,0  )
+		},{		/* '?' - ascii:0x3F font:0x1F   */
+		GEN_FONT_DATA(  0,X,X,X  ),
+		GEN_FONT_DATA(  0,0,0,X  ),
+		GEN_FONT_DATA(  0,0,X,X  ),
+		GEN_FONT_DATA(  0,0,0,0  ),
+		GEN_FONT_DATA(  0,0,X,0  )
+		},{		/* '@' - ascii:0x40 font:0x20   */
+		GEN_FONT_DATA(  0,0,X,X  ),
+		GEN_FONT_DATA(  0,X,0,X  ),
+		GEN_FONT_DATA(  0,X,0,X  ),
+		GEN_FONT_DATA(  0,X,0,0  ),
+		GEN_FONT_DATA(  0,0,X,X  )
+		},{		/* 'A' - ascii:0x41 font:0x21   */
+		GEN_FONT_DATA(  0,0,X,0  ),
+		GEN_FONT_DATA(  0,X,0,X  ),
+		GEN_FONT_DATA(  0,X,X,X  ),
+		GEN_FONT_DATA(  0,X,0,X  ),
+		GEN_FONT_DATA(  0,X,0,X  )
+		},{		/* 'B' - ascii:0x42 font:0x22   */
+		GEN_FONT_DATA(  0,X,X,0  ),
+		GEN_FONT_DATA(  0,X,0,X  ),
+		GEN_FONT_DATA(  0,X,X,0  ),
+		GEN_FONT_DATA(  0,X,0,X  ),
+		GEN_FONT_DATA(  0,X,X,0  )
+		},{		/* 'C' - ascii:0x43 font:0x23   */
+		GEN_FONT_DATA(  0,0,X,X  ),
+		GEN_FONT_DATA(  0,X,0,0  ),
+		GEN_FONT_DATA(  0,X,0,0  ),
+		GEN_FONT_DATA(  0,X,0,0  ),
+		GEN_FONT_DATA(  0,0,X,X  )
+		},{		/* 'D' - ascii:0x44 font:0x24   */
+		GEN_FONT_DATA(  0,X,X,0  ),
+		GEN_FONT_DATA(  0,X,0,X  ),
+		GEN_FONT_DATA(  0,X,0,X  ),
+		GEN_FONT_DATA(  0,X,0,X  ),
+		GEN_FONT_DATA(  0,X,X,0  ),
+		},{		/* 'E' - ascii:0x45 font:0x25   */
+		GEN_FONT_DATA(  0,X,X,X  ),
+		GEN_FONT_DATA(  0,X,0,0  ),
+		GEN_FONT_DATA(  0,X,X,X  ),
+		GEN_FONT_DATA(  0,X,0,0  ),
+		GEN_FONT_DATA(  0,X,X,X  )
+		},{		/* 'F' - ascii:0x46 font:0x26   */
+		GEN_FONT_DATA(  0,X,X,X  ),
+		GEN_FONT_DATA(  0,X,0,0  ),
+		GEN_FONT_DATA(  0,X,X,0  ),
+		GEN_FONT_DATA(  0,X,0,0  ),
+		GEN_FONT_DATA(  0,X,0,0  ),
+		},{		/* 'G' - ascii:0x47 font:0x27   */
+		GEN_FONT_DATA(  0,0,X,X  ),
+		GEN_FONT_DATA(  0,X,0,0  ),
+		GEN_FONT_DATA(  0,X,0,X  ),
+		GEN_FONT_DATA(  0,X,0,X  ),
+		GEN_FONT_DATA(  0,0,X,X  )
+		},{		/* 'H' - ascii:0x48 font:0x28   */
+		GEN_FONT_DATA(  0,X,0,X  ),
+		GEN_FONT_DATA(  0,X,0,X  ),
+		GEN_FONT_DATA(  0,X,X,X  ),
+		GEN_FONT_DATA(  0,X,0,X  ),
+		GEN_FONT_DATA(  0,X,0,X  )
+		},{		/* 'I' - ascii:0x49 font:0x29   */
+		GEN_FONT_DATA(  0,0,X,0  ),
+		GEN_FONT_DATA(  0,0,X,0  ),
+		GEN_FONT_DATA(  0,0,X,0  ),
+		GEN_FONT_DATA(  0,0,X,0  ),
+		GEN_FONT_DATA(  0,0,X,0  )
+		},{		/* 'J' - ascii:0x4A font:0x2A   */
+		GEN_FONT_DATA(  0,0,0,X  ),
+		GEN_FONT_DATA(  0,0,0,X  ),
+		GEN_FONT_DATA(  0,0,0,X  ),
+		GEN_FONT_DATA(  0,X,0,X  ),
+		GEN_FONT_DATA(  0,0,X,0  )
+		},{		/* 'K' - ascii:0x4B font:0x2B   */
+		GEN_FONT_DATA(  0,X,0,X  ),
+		GEN_FONT_DATA(  0,X,X,0  ),
+		GEN_FONT_DATA(  0,X,0,0  ),
+		GEN_FONT_DATA(  0,X,X,0  ),
+		GEN_FONT_DATA(  0,X,0,X  )
+		},{		/* 'L' - ascii:0x4C font:0x2C   */
+		GEN_FONT_DATA(  0,X,0,0  ),
+		GEN_FONT_DATA(  0,X,0,0  ),
+		GEN_FONT_DATA(  0,X,0,0  ),
+		GEN_FONT_DATA(  0,X,0,0  ),
+		GEN_FONT_DATA(  0,X,X,X  )
+		},{		/* 'M' - ascii:0x4D font:0x2D   */
+		GEN_FONT_DATA(  0,X,0,X  ),
+		GEN_FONT_DATA(  0,X,X,X  ),
+		GEN_FONT_DATA(  0,X,0,X  ),
+		GEN_FONT_DATA(  0,X,0,X  ),
+		GEN_FONT_DATA(  0,X,0,X  )
+		},{		/* 'N' - ascii:0x4E font:0x2E   */
+		GEN_FONT_DATA(  0,X,0,X  ),
+		GEN_FONT_DATA(  0,X,X,X  ),
+		GEN_FONT_DATA(  0,X,X,X  ),
+		GEN_FONT_DATA(  0,X,0,X  ),
+		GEN_FONT_DATA(  0,X,0,X  )
+		},{		/* 'O' - ascii:0x4F font:0x2F   */
+		GEN_FONT_DATA(  0,0,X,0  ),
+		GEN_FONT_DATA(  0,X,0,X  ),
+		GEN_FONT_DATA(  0,X,0,X  ),
+		GEN_FONT_DATA(  0,X,0,X  ),
+		GEN_FONT_DATA(  0,0,X,0  )
+		},{		/* 'P' - ascii:0x50 font:0x30   */
+		GEN_FONT_DATA(  0,X,X,0  ),
+		GEN_FONT_DATA(  0,X,0,X  ),
+		GEN_FONT_DATA(  0,X,X,0  ),
+		GEN_FONT_DATA(  0,X,0,0  ),
+		GEN_FONT_DATA(  0,X,0,0  ),
+		},{		/* 'Q' - ascii:0x51 font:0x31   */
+		GEN_FONT_DATA(  0,0,X,0  ),
+		GEN_FONT_DATA(  0,X,0,X  ),
+		GEN_FONT_DATA(  0,X,0,X  ),
+		GEN_FONT_DATA(  0,X,0,X  ),
+		GEN_FONT_DATA(  0,0,X,X  )
+		},{		/* 'R' - ascii:0x52 font:0x33   */
+		GEN_FONT_DATA(  0,X,X,0  ),
+		GEN_FONT_DATA(  0,X,0,X  ),
+		GEN_FONT_DATA(  0,X,X,0  ),
+		GEN_FONT_DATA(  0,X,0,X  ),
+		GEN_FONT_DATA(  0,X,0,X  )
+		},{		/* 'S' - ascii:0x53 font:0x33   */
+		GEN_FONT_DATA(  0,0,X,X  ),
+		GEN_FONT_DATA(  0,X,0,0  ),
+		GEN_FONT_DATA(  0,0,X,0  ),
+		GEN_FONT_DATA(  0,0,0,X  ),
+		GEN_FONT_DATA(  0,X,X,0  )
+		},{		/* 'T' - ascii:0x54 font:0x34   */
+		GEN_FONT_DATA(  0,X,X,X  ),
+		GEN_FONT_DATA(  0,0,X,0  ),
+		GEN_FONT_DATA(  0,0,X,0  ),
+		GEN_FONT_DATA(  0,0,X,0  ),
+		GEN_FONT_DATA(  0,0,X,0  ),
+		},{		/* 'U' - ascii:0x55 font:0x35   */
+		GEN_FONT_DATA(  0,X,0,X  ),
+		GEN_FONT_DATA(  0,X,0,X  ),
+		GEN_FONT_DATA(  0,X,0,X  ),
+		GEN_FONT_DATA(  0,X,0,X  ),
+		GEN_FONT_DATA(  0,X,X,X  )
+		},{		/* 'V' - ascii:0x56 font:0x36   */
+		GEN_FONT_DATA(  0,X,0,X  ),
+		GEN_FONT_DATA(  0,X,0,X  ),
+		GEN_FONT_DATA(  0,X,0,X  ),
+		GEN_FONT_DATA(  0,X,0,X  ),
+		GEN_FONT_DATA(  0,0,X,0  ),
+		},{		/* 'W' - ascii:0x57 font:0x37   */
+		GEN_FONT_DATA(  0,X,0,X  ),
+		GEN_FONT_DATA(  0,X,0,X  ),
+		GEN_FONT_DATA(  0,X,0,X  ),
+		GEN_FONT_DATA(  0,X,X,X  ),
+		GEN_FONT_DATA(  0,X,0,X  ),
+		},{		/* 'X' - ascii:0x58 font:0x38   */
+		GEN_FONT_DATA(  0,X,0,X  ),
+		GEN_FONT_DATA(  0,X,0,X  ),
+		GEN_FONT_DATA(  0,0,X,0  ),
+		GEN_FONT_DATA(  0,X,0,X  ),
+		GEN_FONT_DATA(  0,X,0,X  )
+		},{		/* 'Y' - ascii:0x59 font:0x39   */
+		GEN_FONT_DATA(  0,X,0,X  ),
+		GEN_FONT_DATA(  0,X,0,X  ),
+		GEN_FONT_DATA(  0,0,X,0  ),
+		GEN_FONT_DATA(  0,0,X,0  ),
+		GEN_FONT_DATA(  0,0,X,0  ),
+		},{		/* 'Z' - ascii:0x5A font:0x3A   */
+		GEN_FONT_DATA(  0,X,X,X  ),
+		GEN_FONT_DATA(  0,0,0,X  ),
+		GEN_FONT_DATA(  0,0,X,0  ),
+		GEN_FONT_DATA(  0,X,0,0  ),
+		GEN_FONT_DATA(  0,X,X,X  )
+		},{		/* '[' - ascii:0x5B font:0x3B   */
+		GEN_FONT_DATA(  0,X,X,X  ),
+		GEN_FONT_DATA(  0,X,0,0  ),
+		GEN_FONT_DATA(  0,X,0,0  ),
+		GEN_FONT_DATA(  0,X,0,0  ),
+		GEN_FONT_DATA(  0,X,X,X  )
+		},{		/* '\' - ascii:0x5C font:0x3C   */
+		GEN_FONT_DATA(  X,0,0,0  ),
+		GEN_FONT_DATA(  0,X,0,0  ),
+		GEN_FONT_DATA(  0,0,X,0  ),
+		GEN_FONT_DATA(  0,0,0,X  ),
+		GEN_FONT_DATA(  0,0,0,0  )
+		},{		/* ']' - ascii:0x5D font:0x3D   */
+		GEN_FONT_DATA(  0,X,X,X  ),
+		GEN_FONT_DATA(  0,0,0,X  ),
+		GEN_FONT_DATA(  0,0,0,X  ),
+		GEN_FONT_DATA(  0,0,0,X  ),
+		GEN_FONT_DATA(  0,X,X,X  )
+		},{		/* '^' - ascii:0x5E font:0x3E   */
+		GEN_FONT_DATA(  0,0,X,0  ),
+		GEN_FONT_DATA(  0,X,0,X  ),
+		GEN_FONT_DATA(  0,0,0,0  ),
+		GEN_FONT_DATA(  0,0,0,0  ),
+		GEN_FONT_DATA(  0,0,0,0  )
+		},{		/* '_' - ascii:0x5F font:0x3F   */
+		GEN_FONT_DATA(  0,0,0,0  ),
+		GEN_FONT_DATA(  0,0,0,0  ),
+		GEN_FONT_DATA(  0,0,0,0  ),
+		GEN_FONT_DATA(  0,0,0,0  ),
+		GEN_FONT_DATA(  0,X,X,X  )
+		},{		/* '´' - ascii:0x60 font:0x30   */
+		GEN_FONT_DATA(  0,0,X,0  ),
+		GEN_FONT_DATA(  0,0,0,X  ),
+		GEN_FONT_DATA(  0,0,0,0  ),
+		GEN_FONT_DATA(  0,0,0,0  ),
+		GEN_FONT_DATA(  0,0,0,0  )
+		},{		/* 'a' - ascii:0x31 font:0x31   */
+		GEN_FONT_DATA(  0,0,0,0  ),
+		GEN_FONT_DATA(  0,X,X,0  ),
+		GEN_FONT_DATA(  0,0,X,X  ),
+		GEN_FONT_DATA(  0,X,0,X  ),
+		GEN_FONT_DATA(  0,X,X,X  )
+		},{		/* 'b' - ascii:0x62 font:0x32   */
+		GEN_FONT_DATA(  0,X,0,0  ),
+		GEN_FONT_DATA(  0,X,0,0  ),
+		GEN_FONT_DATA(  0,X,X,0  ),
+		GEN_FONT_DATA(  0,X,0,X  ),
+		GEN_FONT_DATA(  0,X,X,0  )
+		},{		/* 'c' - ascii:0x63 font:0x33   */
+		GEN_FONT_DATA(  0,0,0,0  ),
+		GEN_FONT_DATA(  0,0,X,X  ),
+		GEN_FONT_DATA(  0,X,0,0  ),
+		GEN_FONT_DATA(  0,X,0,0  ),
+		GEN_FONT_DATA(  0,0,X,X  )
+		},{		/* 'd' - ascii:0x64 font:0x34   */
+		GEN_FONT_DATA(  0,0,0,X  ),
+		GEN_FONT_DATA(  0,0,0,X  ),
+		GEN_FONT_DATA(  0,0,X,X  ),
+		GEN_FONT_DATA(  0,X,0,X  ),
+		GEN_FONT_DATA(  0,0,X,X  ),
+		},{		/* 'e' - ascii:0x65 font:0x35   */
+		GEN_FONT_DATA(  0,0,0,0  ),
+		GEN_FONT_DATA(  0,0,X,0  ),
+		GEN_FONT_DATA(  0,X,0,X  ),
+		GEN_FONT_DATA(  0,X,X,0  ),
+		GEN_FONT_DATA(  0,0,X,X  )
+		},{		/* 'f' - ascii:0x66 font:0x36   */
+		GEN_FONT_DATA(  0,0,0,0  ),
+		GEN_FONT_DATA(  0,0,X,X  ),
+		GEN_FONT_DATA(  0,X,0,0  ),
+		GEN_FONT_DATA(  0,X,X,X  ),
+		GEN_FONT_DATA(  0,X,0,0  ),
+		},{		/* 'g' - ascii:0x67 font:0x37   */
+		GEN_FONT_DATA(  0,0,0,0  ),
+		GEN_FONT_DATA(  0,0,X,0  ),
+		GEN_FONT_DATA(  0,X,0,X  ),
+		GEN_FONT_DATA(  0,0,X,X  ),
+		GEN_FONT_DATA(  0,X,X,0  )
+		},{		/* 'h' - ascii:0x68 font:0x38   */
+		GEN_FONT_DATA(  0,X,0,0  ),
+		GEN_FONT_DATA(  0,X,0,0  ),
+		GEN_FONT_DATA(  0,X,X,X  ),
+		GEN_FONT_DATA(  0,X,0,X  ),
+		GEN_FONT_DATA(  0,X,0,X  )
+		},{		/* 'i' - ascii:0x69 font:0x39   */
+		GEN_FONT_DATA(  0,0,X,0  ),
+		GEN_FONT_DATA(  0,0,0,0  ),
+		GEN_FONT_DATA(  0,0,X,0  ),
+		GEN_FONT_DATA(  0,0,X,0  ),
+		GEN_FONT_DATA(  0,0,X,0  )
+		},{		/* 'j' - ascii:0x6A font:0x3A   */
+		GEN_FONT_DATA(  0,0,0,X  ),
+		GEN_FONT_DATA(  0,0,0,0  ),
+		GEN_FONT_DATA(  0,0,0,X  ),
+		GEN_FONT_DATA(  0,X,0,X  ),
+		GEN_FONT_DATA(  0,0,X,0  )
+		},{		/* 'k' - ascii:0x6B font:0x3B   */
+		GEN_FONT_DATA(  0,X,0,0  ),
+		GEN_FONT_DATA(  0,X,0,0  ),
+		GEN_FONT_DATA(  0,X,0,X  ),
+		GEN_FONT_DATA(  0,X,X,0  ),
+		GEN_FONT_DATA(  0,X,0,X  )
+		},{		/* 'l' - ascii:0x6C font:0x3C   */
+		GEN_FONT_DATA(  0,X,X,0  ),
+		GEN_FONT_DATA(  0,0,X,0  ),
+		GEN_FONT_DATA(  0,0,X,0  ),
+		GEN_FONT_DATA(  0,0,X,0  ),
+		GEN_FONT_DATA(  0,X,X,X  )
+		},{		/* 'm' - ascii:0x6D font:0x3D   */
+		GEN_FONT_DATA(  0,0,0,0  ),
+		GEN_FONT_DATA(  0,X,0,X  ),
+		GEN_FONT_DATA(  0,X,X,X  ),
+		GEN_FONT_DATA(  0,X,0,X  ),
+		GEN_FONT_DATA(  0,X,0,X  )
+		},{		/* 'n' - ascii:0x6E font:0x3E   */
+		GEN_FONT_DATA(  0,0,0,0  ),
+		GEN_FONT_DATA(  0,X,X,0  ),
+		GEN_FONT_DATA(  0,X,0,X  ),
+		GEN_FONT_DATA(  0,X,0,X  ),
+		GEN_FONT_DATA(  0,X,0,X  )
+		},{		/* 'o' - ascii:0x6F font:0x6F   */
+		GEN_FONT_DATA(  0,0,0,0  ),
+		GEN_FONT_DATA(  0,0,X,0  ),
+		GEN_FONT_DATA(  0,X,0,X  ),
+		GEN_FONT_DATA(  0,X,0,X  ),
+		GEN_FONT_DATA(  0,0,X,0  )
+		},{		/* 'p' - ascii:0x70 font:0x40   */
+		GEN_FONT_DATA(  0,0,0,0  ),
+		GEN_FONT_DATA(  0,X,X,0  ),
+		GEN_FONT_DATA(  0,X,0,X  ),
+		GEN_FONT_DATA(  0,X,X,0  ),
+		GEN_FONT_DATA(  0,X,0,0  ),
+		},{		/* 'q' - ascii:0x71 font:0x41   */
+		GEN_FONT_DATA(  0,0,0,0  ),
+		GEN_FONT_DATA(  0,0,X,X  ),
+		GEN_FONT_DATA(  0,X,0,X  ),
+		GEN_FONT_DATA(  0,0,X,X  ),
+		GEN_FONT_DATA(  0,0,0,X  )
+		},{		/* 'r' - ascii:0x72 font:0x43   */
+		GEN_FONT_DATA(  0,0,0,0  ),
+		GEN_FONT_DATA(  0,X,0,X  ),
+		GEN_FONT_DATA(  0,X,X,0  ),
+		GEN_FONT_DATA(  0,X,0,0  ),
+		GEN_FONT_DATA(  0,X,0,0  )
+		},{		/* 's' - ascii:0x73 font:0x43   */
+		GEN_FONT_DATA(  0,0,0,0  ),
+		GEN_FONT_DATA(  0,0,X,X  ),
+		GEN_FONT_DATA(  0,X,X,0  ),
+		GEN_FONT_DATA(  0,0,X,X  ),
+		GEN_FONT_DATA(  0,X,X,0  )
+		},{		/* 't' - ascii:0x74 font:0x44   */
+		GEN_FONT_DATA(  0,0,0,0  ),
+		GEN_FONT_DATA(  0,0,X,0  ),
+		GEN_FONT_DATA(  0,X,X,X  ),
+		GEN_FONT_DATA(  0,0,X,0  ),
+		GEN_FONT_DATA(  0,0,X,X  ),
+		},{		/* 'u' - ascii:0x75 font:0x45   */
+		GEN_FONT_DATA(  0,0,0,0  ),
+		GEN_FONT_DATA(  0,X,0,X  ),
+		GEN_FONT_DATA(  0,X,0,X  ),
+		GEN_FONT_DATA(  0,X,0,X  ),
+		GEN_FONT_DATA(  0,0,X,X  )
+		},{		/* 'v' - ascii:0x76 font:0x46   */
+		GEN_FONT_DATA(  0,0,0,0  ),
+		GEN_FONT_DATA(  0,X,0,X  ),
+		GEN_FONT_DATA(  0,X,0,X  ),
+		GEN_FONT_DATA(  0,X,0,X  ),
+		GEN_FONT_DATA(  0,0,X,0  ),
+		},{		/* 'w' - ascii:0x77 font:0x47   */
+		GEN_FONT_DATA(  0,0,0,0  ),
+		GEN_FONT_DATA(  0,X,0,X  ),
+		GEN_FONT_DATA(  0,X,0,X  ),
+		GEN_FONT_DATA(  0,X,X,X  ),
+		GEN_FONT_DATA(  0,X,0,X  ),
+		},{		/* 'x' - ascii:0x78 font:0x48   */
+		GEN_FONT_DATA(  0,0,0,0  ),
+		GEN_FONT_DATA(  0,X,0,X  ),
+		GEN_FONT_DATA(  0,0,X,0  ),
+		GEN_FONT_DATA(  0,0,X,0  ),
+		GEN_FONT_DATA(  0,X,0,X  )
+		},{		/* 'y' - ascii:0x79 font:0x49   */
+		GEN_FONT_DATA(  0,0,0,0  ),
+		GEN_FONT_DATA(  0,X,0,X  ),
+		GEN_FONT_DATA(  0,0,X,0  ),
+		GEN_FONT_DATA(  0,0,X,0  ),
+		GEN_FONT_DATA(  0,X,0,0  ),
+		},{		/* 'z' - ascii:0x7A font:0x4A   */
+		GEN_FONT_DATA(  0,0,0,0  ),
+		GEN_FONT_DATA(  0,X,X,X  ),
+		GEN_FONT_DATA(  0,0,0,X  ),
+		GEN_FONT_DATA(  0,0,X,0  ),
+		GEN_FONT_DATA(  0,X,X,X  )
+		},{		/* '{' - ascii:0x7B font:0x4B   */
+		GEN_FONT_DATA(  0,0,X,X  ),
+		GEN_FONT_DATA(  0,0,X,0  ),
+		GEN_FONT_DATA(  0,X,0,0  ),
+		GEN_FONT_DATA(  0,0,X,0  ),
+		GEN_FONT_DATA(  0,0,X,X  )
+		},{		/* '\' - ascii:0x7C font:0x4C   */
+		GEN_FONT_DATA(  0,0,0,0  ),
+		GEN_FONT_DATA(  0,X,0,0  ),
+		GEN_FONT_DATA(  0,0,X,0  ),
+		GEN_FONT_DATA(  0,0,0,X  ),
+		GEN_FONT_DATA(  0,0,0,0  )
+		},{		/* '}' - ascii:0x7D font:0x4D   */
+		GEN_FONT_DATA(  0,X,X,0  ),
+		GEN_FONT_DATA(  0,0,X,0  ),
+		GEN_FONT_DATA(  0,0,0,X  ),
+		GEN_FONT_DATA(  0,0,X,0  ),
+		GEN_FONT_DATA(  0,X,X,0  )
+		},{		/* '~' - ascii:0x7E font:0x4E   */
+		GEN_FONT_DATA(  0,0,0,0  ),
+		GEN_FONT_DATA(  0,X,0,0  ),
+		GEN_FONT_DATA(  0,X,X,X  ),
+		GEN_FONT_DATA(  0,0,0,X  ),
+		GEN_FONT_DATA(  0,0,0,0  )
+		},{		/* DEL - ascii:0x7F font:0x4F   */
+		GEN_FONT_DATA(  X,X,X,X  ),
+		GEN_FONT_DATA(  X,X,X,X  ),
+		GEN_FONT_DATA(  X,X,X,X  ),
+		GEN_FONT_DATA(  X,X,X,X  ),
+		GEN_FONT_DATA(  X,X,X,X  )
+		}
+	};

c/src/lib/libbsp/arm/gba/irq/irq_asm.S

@@ -83,13 +83,13 @@ PUBLIC_ARM_FUNCTION(_ISR_Handler)
 
 /* If a task switch is necessary, call scheduler */
         ldr     r0, =_Context_Switch_necessary
-        ldr     r1, [r0]
+        ldrb    r1, [r0]
         cmp     r1, #0
 
         /* since bframe is going to clear _ISR_Signals_to_thread_executing, */
         /*    we need to load it here */
         ldr     r0, =_ISR_Signals_to_thread_executing
-        ldr     r1, [r0]
+        ldrb    r1, [r0]
         bne     bframe
 
 /* If a signals to be sent (_ISR_Signals_to_thread_executing != 0),        */
@@ -99,7 +99,7 @@ PUBLIC_ARM_FUNCTION(_ISR_Handler)
 
 /* _ISR_Signals_to_thread_executing = FALSE */
         mov     r1, #0
-        str     r1, [r0]
+        strb    r1, [r0]
 
 bframe:
 /* Now we need to set up the return from this ISR to be _ISR_Dispatch */

c/src/lib/libbsp/arm/rtl22xx/ChangeLog

@@ -1,3 +1,8 @@
+2009-03-02	Ray Xu <rayx.cn@gmail.com>
+
+	PR 1380/bsps
+	* include/bsp.h: Switch to English comments.
+
 2008-12-08	Ralf Corsépius <ralf.corsepius@rtems.org>
 
 	* bsp_specs: Backport from CVS-HEAD.

c/src/lib/libbsp/arm/rtl22xx/include/bsp.h

@@ -30,12 +30,15 @@ extern "C" {
 /* cclk=cco/(2*P) */
 /* cco = cclk*2*P 	*/
 
-#define	LPC22xx_Fcclk	CONFIG_ARM_CLK  /* system clk frequecy,<=60Mhz, defined in system configuration */
+/* system clk frequecy,<=60Mhz, defined in system configuration */
+#define	LPC22xx_Fcclk	CONFIG_ARM_CLK
 
 /* Fcco 156M~320Mhz*/
-#define	LPC22xx_Fcclk	CONFIG_ARM_CLK  /* system clk frequecy,<=60Mhz, defined in system configuration */
+/* system clk frequecy,<=60Mhz, defined in system configuration */
+#define	LPC22xx_Fcclk	CONFIG_ARM_CLK
 #define LPC22xx_Fcco	LPC22xx_Fcclk * 4
-#define LPC22xx_Fpclk	(LPC22xx_Fcclk /4) *1  /*VPB clk frequency,1,1/2,1/4 times of Fcclk */
+/*VPB clk frequency,1,1/2,1/4 times of Fcclk */
+#define LPC22xx_Fpclk	(LPC22xx_Fcclk /4) *1
 
 
 
@@ -76,14 +79,15 @@ extern "C" {
 /**
 * help file 
 */
-/* ϵͳ<EFBFBD><EFBFBD><EFBFBD><EFBFBD>, Fosc<EFBFBD><EFBFBD>Fcclk<EFBFBD><EFBFBD>Fcco<EFBFBD><EFBFBD>Fpclk<EFBFBD><EFBFBD><EFBFBD>붨<EFBFBD><EFBFBD>*/
-#define Fosc            11059200                    //<2F><><EFBFBD><EFBFBD>Ƶ<EFBFBD><C6B5>,10MHz~25MHz<48><7A>Ӧ<EFBFBD><D3A6><EFBFBD><EFBFBD>ʵ<EFBFBD><CAB5>һ<EFBFBD><D2BB>
-#define Fcclk           (Fosc << 2)                  //ϵͳƵ<EFBFBD>ʣ<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ΪFosc<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>(1~32)<29><><EFBFBD><EFBFBD><=60MHZ
-#define Fcco            (Fcclk <<2)                 //CCOƵ<4F>ʣ<EFBFBD><CAA3><EFBFBD><EFBFBD><EFBFBD>ΪFcclk<6C><6B>2<EFBFBD><32>4<EFBFBD><34>8<EFBFBD><38>16<31><36><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ΧΪ156MHz~320MHz
-#define Fpclk           (Fcclk >>2) * 1             //VPBʱ<42><CAB1>Ƶ<EFBFBD>ʣ<EFBFBD>ֻ<EFBFBD><D6BB>Ϊ(Fcclk / 4)<29><>1 ~ 4<><34>
-#define M                Fcclk / Fosc;
-#define P_min         Fcco_MIN / (2*Fcclk) + 1;
-#define P_max        Fcco_MAX / (2*Fcclk);
+/* System configure, Fosc Fcclk Fcco Fpclk must be defined*/
+#define Fosc    11059200          // osc freq,10MHz~25MHz,
+                                  //    change to real one if needed
+#define Fcclk   (Fosc << 2)       //system freq 2^n time of  Fosc(1~32) <=60MHZ
+#define Fcco    (Fcclk <<2)       //CCO freq 2,4,8,16 time of Fcclk 156MHz~320MHz
+#define Fpclk   (Fcclk >>2) * 1   //VPB freq only(Fcclk / 4) 1~4
+#define M       Fcclk / Fosc
+#define P_min   Fcco_MIN / (2*Fcclk) + 1;
+#define P_max   Fcco_MAX / (2*Fcclk);
 
 
 
@@ -106,20 +110,20 @@ extern "C" {
 #define SPI_CS_PIN_FUNC   PINSEL0_bit.SPI_CS_PIN
 
 // Flash definition
-//#define FLASH_SIZE              (0x200000-FLASH_BOOT)   // Total area of Flash region in words 8 bit
-#define FLASH_SIZE              (0x80000-FLASH_BOOT)   // Total area of Flash region in words 8 bit
-//#define FLASH_SIZE              (0x80000-FLASH_BOOT)      // Total area of Flash region in words 8 bit
-#define FLASH_BEGIN             0x80000000
-#define FLASH_BASE              (FLASH_BEGIN+FLASH_BOOT)   //First 0x8000 bytes reserved for boot loader etc.
+//#define FLASH_SIZE      (0x200000-FLASH_BOOT)   // Total area of Flash region in words 8 bit
+#define FLASH_SIZE        (0x80000-FLASH_BOOT)   // Total area of Flash region in words 8 bit
+//#define FLASH_SIZE      (0x80000-FLASH_BOOT)      // Total area of Flash region in words 8 bit
+#define FLASH_BEGIN       0x80000000
+#define FLASH_BASE        (FLASH_BEGIN+FLASH_BOOT)   //First 0x8000 bytes reserved for boot loader etc.
 
 // SRAM definition
-#define SRAM_SIZE               0x100000                  // Total area of Flash region in words 8 bit
-#define SRAM_BASE               0x81000000                //First 0x8000 bytes reserved for boot loader etc.
+#define SRAM_SIZE         0x100000                  // Total area of Flash region in words 8 bit
+#define SRAM_BASE         0x81000000                //First 0x8000 bytes reserved for boot loader etc.
 
 // CS8900A definition
-#define CS8900A_BASE            0x82000000                //
+#define CS8900A_BASE      0x82000000
 // RTL8019AS definition
-#define RTL8019AS_BASE            0x82000000                //
+#define RTL8019AS_BASE    0x82000000
 
 struct rtems_bsdnet_ifconfig;
 int cs8900_driver_attach (struct rtems_bsdnet_ifconfig *config,

c/src/lib/libbsp/arm/shared/irq/irq_asm.S

@@ -79,13 +79,13 @@ _ISR_Handler:
 
 /* If a task switch is necessary, call scheduler */
         ldr     r0, =_Context_Switch_necessary
-        ldr     r1, [r0]
+        ldrb    r1, [r0]
         cmp     r1, #0
 
         /* since bframe is going to clear _ISR_Signals_to_thread_executing, */
         /*    we need to load it here */
         ldr     r0, =_ISR_Signals_to_thread_executing
-        ldr     r1, [r0]
+        ldrb    r1, [r0]
         bne     bframe
 
 /* If a signals to be sent (_ISR_Signals_to_thread_executing != 0),        */
@@ -95,7 +95,7 @@ _ISR_Handler:
 
 /* _ISR_Signals_to_thread_executing = FALSE */
         mov     r1, #0
-        str     r1, [r0]
+        strb    r1, [r0]
 
 bframe:
 

c/src/lib/libbsp/arm/smdk2410/include/.cvsignore

@@ -0,0 +1,4 @@
+stamp-h
+stamp-h.in
+bspopts.h
+bspopts.h.in

c/src/lib/libbsp/bare/preinstall.am

@@ -0,0 +1,45 @@
+## Automatically generated by ampolish3 - Do not edit
+
+if AMPOLISH3
+$(srcdir)/preinstall.am: Makefile.am
+	$(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am
+endif
+
+PREINSTALL_DIRS =
+DISTCLEANFILES += $(PREINSTALL_DIRS)
+
+all-am: $(PREINSTALL_FILES)
+
+PREINSTALL_FILES =
+CLEANFILES = $(PREINSTALL_FILES)
+
+$(PROJECT_LIB)/$(dirstamp):
+	@$(MKDIR_P) $(PROJECT_LIB)
+	@: > $(PROJECT_LIB)/$(dirstamp)
+PREINSTALL_DIRS += $(PROJECT_LIB)/$(dirstamp)
+
+$(PROJECT_INCLUDE)/$(dirstamp):
+	@$(MKDIR_P) $(PROJECT_INCLUDE)
+	@: > $(PROJECT_INCLUDE)/$(dirstamp)
+PREINSTALL_DIRS += $(PROJECT_INCLUDE)/$(dirstamp)
+
+$(PROJECT_LIB)/bsp_specs: bsp_specs $(PROJECT_LIB)/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_LIB)/bsp_specs
+PREINSTALL_FILES += $(PROJECT_LIB)/bsp_specs
+
+$(PROJECT_INCLUDE)/bsp.h: include/bsp.h $(PROJECT_INCLUDE)/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp.h
+
+$(PROJECT_INCLUDE)/tm27.h: include/tm27.h $(PROJECT_INCLUDE)/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/tm27.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/tm27.h
+
+$(PROJECT_INCLUDE)/bspopts.h: include/bspopts.h $(PROJECT_INCLUDE)/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bspopts.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bspopts.h
+
+$(PROJECT_INCLUDE)/coverhd.h: ../shared/include/coverhd.h $(PROJECT_INCLUDE)/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/coverhd.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/coverhd.h
+

c/src/lib/libbsp/i386/ChangeLog

@@ -1,3 +1,17 @@
+2009-05-18	Joel Sherrill <joel.sherrill@OARcorp.com>
+
+	* shared/irq/irq.c, shared/irq/irq.h, shared/irq/irq_asm.S: Add shared
+	interrupt support to i386.
+
+2009-03-12	Joel Sherrill <joel.sherrill@OARcorp.com>
+
+	PR 1385/cpukit
+	* shared/irq/irq_asm.S: When the type rtems_boolean was switched to the
+	C99 bool, the size changed from 4 bytes to 1 byte. The interrupt
+	dispatching code accesses two boolean variables for scheduling
+	purposes and the assembly implementations of this code did not get
+	updated.
+
 2008-09-07	Ralf Corsépius <ralf.corsepius@rtems.org>
 
 	* shared/comm/i386-stub.c: Include stdbool.h.

c/src/lib/libbsp/i386/pc386/ChangeLog

@@ -1,3 +1,16 @@
+2010-03-10	Gedare Bloom <gedare@gwu.edu>
+
+	PR 1495/bsp
+	* clock/ckinit.c: Calling rtems_clock_get_uptime() in a tight loop
+	sometimes showed time moving backwards.
+
+2009-09-15	Till Straumann <strauman@slac.stanford.edu>
+
+	PR 1344/bsps:
+	* clock/ckinit.c: Fix more bugs (applied PR1344/attachment 702):
+	TSC handler was used when 8254 was requested and vice versa.
+	Also, nanosecond handler was never installed to RTEMS clock.
+
 2008-12-08	Ralf Corsépius <ralf.corsepius@rtems.org>
 
 	* bsp_specs: Backport from CVS-HEAD.

c/src/lib/libbsp/i386/pc386/clock/ckinit.c

@@ -47,6 +47,11 @@ uint64_t pc586_tsc_at_tick;
 /* this driver may need to count ISRs per tick */
 #define CLOCK_DRIVER_ISRS_PER_TICK pc386_isrs_per_tick
 
+/* if so, the driver may use the count in Clock_driver_support_at_tick */
+#ifdef CLOCK_DRIVER_ISRS_PER_TICK
+extern volatile uint32_t Clock_driver_isrs;
+#endif
+
 #define READ_8254( _lsb, _msb )                               \
   do { outport_byte(TIMER_MODE, TIMER_SEL0|TIMER_LATCH);      \
      inport_byte(TIMER_CNTR0, _lsb);                          \
@@ -66,7 +71,18 @@ uint32_t (*Clock_driver_nanoseconds_since_last_tick)(void) = NULL;
  */
 void Clock_driver_support_at_tick_tsc(void)
 {
+#ifdef CLOCK_DRIVER_ISRS_PER_TICK
+  /*
+   *  The driver is multiple ISRs per clock tick.
+  */
+  if (!Clock_driver_isrs)
+    pc586_tsc_at_tick = rdtsc();
+#else
+  /*
+   *  The driver is one ISR per clock tick.
+   */
   pc586_tsc_at_tick = rdtsc();
+#endif
 }
 
 void Clock_driver_support_at_tick_empty(void)
@@ -285,19 +301,27 @@ void Clock_driver_support_initialize_hardware(void)
     /* printk( "Use 8254\n" ); */
     Clock_driver_support_at_tick = Clock_driver_support_at_tick_empty;
     Clock_driver_nanoseconds_since_last_tick = 
-      bsp_clock_nanoseconds_since_last_tick_tsc;
-
+      bsp_clock_nanoseconds_since_last_tick_i8254;
   } else {
     /* printk( "Use TSC\n" ); */
     Clock_driver_support_at_tick = Clock_driver_support_at_tick_tsc;
     Clock_driver_nanoseconds_since_last_tick = 
-      bsp_clock_nanoseconds_since_last_tick_i8254;
+      bsp_clock_nanoseconds_since_last_tick_tsc;
   }
 
+  /* Shell installs nanosecond handler before calling
+   * Clock_driver_support_initialize_hardware() :-(
+   * so we do it again now that we're ready.
+   */
+  rtems_clock_set_nanoseconds_extension(
+    Clock_driver_nanoseconds_since_last_tick
+  );
+
   if (!BSP_install_rtems_irq_handler (&clockIrqData)) {
     printk("Unable to initialize system clock\n");
     rtems_fatal_error_occurred(1);
   }
+
 }
 
 #define Clock_driver_support_shutdown_hardware() \

c/src/lib/libbsp/i386/shared/irq/irq.c

@@ -2,7 +2,7 @@
  *
  *  This file contains the implementation of the function described in irq.h
  *
- *  CopyRight (C) 1998 valette@crf.canon.fr
+ *  Copyright (C) 1998 valette@crf.canon.fr
  *
  *  The license and distribution terms for this file may be
  *  found in found in the file LICENSE in this distribution or at
@@ -195,7 +195,63 @@ static int isValidInterrupt(int irq)
 }
 
 /*
- * ------------------------ RTEMS Single Irq Handler Mngt Routines ----------------
+ * ------------------- RTEMS Shared Irq Handler Mngt Routines ------------
+ */
+int BSP_install_rtems_shared_irq_handler  (const rtems_irq_connect_data* irq)
+{
+  rtems_interrupt_level   level;
+  rtems_irq_connect_data* vchain;
+
+  if (!isValidInterrupt(irq->name)) {
+    printk("Invalid interrupt vector %d\n",irq->name);
+    return 0;
+  }
+
+  rtems_interrupt_disable(level);
+
+  if ( (int)rtems_hdl_tbl[irq->name].next_handler  == -1 ) {
+    rtems_interrupt_enable(level);
+    printk(
+      "IRQ vector %d already connected to an unshared handler\n",
+      irq->name
+    );
+    return 0;
+  }
+
+   vchain = (rtems_irq_connect_data*)malloc(sizeof(rtems_irq_connect_data));
+
+  /* save off topmost handler */
+  vchain[0]= rtems_hdl_tbl[irq->name];
+
+  /*
+   * store the data provided by user
+   */
+  rtems_hdl_tbl[irq->name] = *irq;
+
+  /* link chain to new topmost handler */
+  rtems_hdl_tbl[irq->name].next_handler = (void *)vchain;
+
+  /*
+   * enable_irq_at_pic is supposed to ignore
+   * requests to disable interrupts outside
+   * of the range handled by the PIC
+   */
+  BSP_irq_enable_at_i8259s (irq->name);
+
+  /*
+   * Enable interrupt on device
+   */
+  if (irq->on)
+    irq->on(irq);
+
+  rtems_interrupt_enable(level);
+
+  return 1;
+}
+
+
+/*
+ * --------------- RTEMS Single Irq Handler Mngt Routines ---------------
  */
 
 int BSP_install_rtems_irq_handler  (const rtems_irq_connect_data* irq)
@@ -222,6 +278,8 @@ int BSP_install_rtems_irq_handler  (const rtems_irq_connect_data* irq)
      * store the data provided by user
      */
     rtems_hdl_tbl[irq->name] = *irq;
+    rtems_hdl_tbl[irq->name].next_handler = (void *)-1;
+
     /*
      * Enable interrupt at PIC level
      */
@@ -229,7 +287,7 @@ int BSP_install_rtems_irq_handler  (const rtems_irq_connect_data* irq)
     /*
      * Enable interrupt on device
      */
-	if (irq->on)
+    if (irq->on)
     	irq->on(irq);
 
     rtems_interrupt_enable(level);
@@ -252,43 +310,86 @@ int BSP_get_current_rtems_irq_handler	(rtems_irq_connect_data* irq)
 
 int BSP_remove_rtems_irq_handler  (const rtems_irq_connect_data* irq)
 {
-    rtems_interrupt_level       level;
+  rtems_interrupt_level       level;
+  rtems_irq_connect_data *pchain= NULL, *vchain = NULL;
 
-    if (!isValidInterrupt(irq->name)) {
+  if (!isValidInterrupt(irq->name)) {
+    return 0;
+  }
+
+  /*
+   * Check if default handler is actually connected. If not issue an error.
+   * You must first get the current handler via i386_get_current_idt_entry
+   * and then disconnect it using i386_delete_idt_entry.
+   * RATIONALE : to always have the same transition by forcing the user
+   * to get the previous handler before accepting to disconnect.
+   */
+  rtems_interrupt_disable(level);
+  if (rtems_hdl_tbl[irq->name].hdl != irq->hdl) {
+    rtems_interrupt_enable(level);
+    return 0;
+  }
+
+  if ( (int)rtems_hdl_tbl[irq->name].next_handler != -1 ) {
+    int found = 0;
+
+    for( (pchain= NULL, vchain = &rtems_hdl_tbl[irq->name]);
+         (vchain->hdl != default_rtems_entry.hdl);
+         (pchain= vchain,
+          vchain = (rtems_irq_connect_data*)vchain->next_handler) ) {
+      if ( vchain->hdl == irq->hdl ) {
+        found =  -1;
+        break;
+      }
+    }
+
+    if ( !found ) {
+      rtems_interrupt_enable(level);
       return 0;
     }
-    /*
-     * Check if default handler is actually connected. If not issue an error.
-     * You must first get the current handler via i386_get_current_idt_entry
-     * and then disconnect it using i386_delete_idt_entry.
-     * RATIONALE : to always have the same transition by forcing the user
-     * to get the previous handler before accepting to disconnect.
-     */
-    rtems_interrupt_disable(level);
+  } else {
     if (rtems_hdl_tbl[irq->name].hdl != irq->hdl) {
       rtems_interrupt_enable(level);
       return 0;
     }
+  }
 
-    /*
-     * disable interrupt at PIC level
-     */
-    BSP_irq_disable_at_i8259s (irq->name);
+  /*
+   * disable interrupt at PIC level
+   */
+  BSP_irq_disable_at_i8259s (irq->name);
 
-    /*
-     * Disable interrupt on device
-     */
-	if (irq->off)
-    	irq->off(irq);
+  /*
+   * Disable interrupt on device
+   */
+  if (irq->off)
+    irq->off(irq);
 
-    /*
-     * restore the default irq value
-     */
-    rtems_hdl_tbl[irq->name] = default_rtems_entry;
+  /*
+   * restore the default irq value
+   */
+  if( !vchain ) {
+     /* single handler vector... */
+     rtems_hdl_tbl[irq->name] = default_rtems_entry;
+  } else {
+    if ( pchain ) {
+       /* non-first handler being removed */
+       pchain->next_handler = vchain->next_handler;
+    } else {
+       /* first handler isn't malloc'ed, so just overwrite it.  Since
+        * the contents of vchain are being struct copied, vchain itself
+        * goes away
+        */
+       vchain = vchain->next_handler;
+       rtems_hdl_tbl[irq->name]= *vchain;
+    }
+    free(vchain);
+  }
 
-    rtems_interrupt_enable(level);
 
-    return 1;
+  rtems_interrupt_enable(level);
+
+  return 1;
 }
 
 /*
@@ -298,6 +399,7 @@ int BSP_remove_rtems_irq_handler  (const rtems_irq_connect_data* irq)
 int BSP_rtems_irq_mngt_set(rtems_irq_global_settings* config)
 {
     int                    i;
+    rtems_irq_connect_data*       vchain;
     rtems_interrupt_level  level;
 
     /*
@@ -314,17 +416,16 @@ int BSP_rtems_irq_mngt_set(rtems_irq_global_settings* config)
     compute_i8259_masks_from_prio ();
 
     for (i=0; i < internal_config->irqNb; i++) {
-      if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) {
+      BSP_irq_disable_at_i8259s (i);
+      for( vchain = &rtems_hdl_tbl[i];
+           ((int)vchain != -1 && vchain->hdl != default_rtems_entry.hdl); 
+           vchain = (rtems_irq_connect_data*)vchain->next_handler ) {
 	BSP_irq_enable_at_i8259s (i);
-	if (rtems_hdl_tbl[i].on)
-		rtems_hdl_tbl[i].on(&rtems_hdl_tbl[i]);
-      }
-      else {
-	if (rtems_hdl_tbl[i].off)
-		rtems_hdl_tbl[i].off(&rtems_hdl_tbl[i]);
-	BSP_irq_disable_at_i8259s (i);
+        if (vchain->on)
+          vchain->on(vchain);
       }
     }
+
     /*
      * must enable slave pic anyway
      */
@@ -363,3 +464,23 @@ void processIrq(unsigned index)
   rtems_hdl_tbl[index].hdl(rtems_hdl_tbl[index].handle);
 }
 
+static inline void
+bsp_irq_dispatch_list(
+  rtems_irq_connect_data *tbl,
+  unsigned                irq,
+  rtems_irq_hdl                sentinel
+)
+{
+  rtems_irq_connect_data* vchain;
+  for( vchain = &tbl[irq];
+       ((int)vchain != -1 && vchain->hdl != sentinel);
+       vchain = (rtems_irq_connect_data*)vchain->next_handler ) {
+          vchain->hdl(vchain->handle);
+  }
+}
+
+
+void C_dispatch_isr(int irq)
+{
+  bsp_irq_dispatch_list(rtems_hdl_tbl, irq, default_rtems_entry.hdl);
+}

c/src/lib/libbsp/i386/shared/irq/irq.h

@@ -31,6 +31,7 @@ extern "C" {
 
 #include <bsp/irq_asm.h>
 #include <rtems.h>
+#define BSP_SHARED_HANDLER_SUPPORT      1
 #include <rtems/irq.h>
 
 /*-------------------------------------------------------------------------+
@@ -46,7 +47,7 @@ extern "C" {
      * Interrupt offset in comparison to BSP_ASM_IRQ_VECTOR_BASE
      * NB : 1) Interrupt vector number in IDT = offset + BSP_ASM_IRQ_VECTOR_BASE
      * 	    2) The same name should be defined on all architecture
-     *	       so that handler connexion can be unchanged.
+     *	       so that handler connection can be unchanged.
      */
 #define BSP_PERIODIC_TIMER      0
 #define BSP_KEYBOARD          	1

c/src/lib/libbsp/i386/shared/irq/irq_asm.S

@@ -107,11 +107,7 @@ nested:
 	 */
 
         pushl     ecx                       /* push vector number */
-        lea       (ecx,ecx,2), eax
-        mov       SYM (rtems_hdl_tbl), edx
-        shl       $0x3,eax
-        pushl     0x8(edx,eax,1)            /* push hdl argument */
-        call      *0x4(edx,eax,1)           /* call hdl */
+	call	  C_dispatch_isr
         addl      $4, esp
 
 	/*
@@ -143,17 +139,17 @@ nested:
                                             /* Is dispatch disabled */
         jne       .exit                     /* Yes, then exit */
 
-        cmpl      $0, SYM (_Context_Switch_necessary)
+        cmpb      $0, SYM (_Context_Switch_necessary)
                                             /* Is task switch necessary? */
         jne	  .schedule		    /* Yes, then call the scheduler */
 
-        cmpl      $0, SYM (_ISR_Signals_to_thread_executing)
+        cmpb      $0, SYM (_ISR_Signals_to_thread_executing)
                                             /* signals sent to Run_thread */
                                             /*   while in interrupt handler? */
         je        .exit                     /* No, exit */
 
 .bframe:
-        movl      $0, SYM (_ISR_Signals_to_thread_executing)
+        movb      $0, SYM (_ISR_Signals_to_thread_executing)
 	/*
 	 * This code is the less critical path. In order to have a single
 	 * Thread Context, we take the same frame than the one pushed on

c/src/lib/libbsp/m68k/av5282/ChangeLog

@@ -1,3 +1,13 @@
+2009-01-21	Frank Ueberschar <frank.ueberschar@dsa-volgmann.de>
+
+	PR 1354/bsps
+	* network/network.c: In some cases it can occur that an empty mbuf is
+	put on the descriptor chain. (We found it especially then when
+	transmitting fragmented IP Packets.) Since the actual buffer
+	descriptor pointer will be incremented after every inserted mbuf
+	(txBd = sc->txBdBase + sc->txBdHead;) even if m->m_len of the current
+	mbuf was zero. This leads to the bug.
+
 2008-12-08	Ralf Corsépius <ralf.corsepius@rtems.org>
 
 	* bsp_specs: Backport from CVS-HEAD.

c/src/lib/libbsp/m68k/av5282/network/network.c

@@ -548,10 +548,10 @@ fec_sendpacket(struct ifnet *ifp, struct mbuf *m)
 		* The IP fragmentation routine in ip_output
 		* can produce fragments with zero length.
 		*/
-		txBd = sc->txBdBase + sc->txBdHead;
 		if (m->m_len){
 			char *p = mtod(m, char *);
 			int offset = (int) p & 0x3;
+			txBd = sc->txBdBase + sc->txBdHead;
 			if (offset == 0) {
 				txBd->buffer = p;
 				txBd->length = m->m_len;

c/src/lib/libbsp/m68k/gen68340/ChangeLog

@@ -1,3 +1,8 @@
+2009-02-27	Joel Sherrill <joel.sherrill@OARcorp.com>
+
+	* Makefile.am: Remove unnecessary copy of cpu_asm.S
+	* console/Modif_cpu_asm.S: Removed.
+
 2008-12-08	Ralf Corsépius <ralf.corsepius@rtems.org>
 
 	* bsp_specs: Backport from CVS-HEAD.

c/src/lib/libbsp/m68k/gen68340/Makefile.am

@@ -37,8 +37,8 @@ startup_SOURCES = startup/bspclean.c ../../shared/bsplibc.c \
     ../../shared/sbrk.c ../../m68k/shared/setvec.c \
     startup/dumpanic.c ../../shared/gnatinstallhandler.c
 clock_SOURCES = clock/ckinit.c
-console_SOURCES = console/Modif_cpu_asm.S console/console.c \
-    console/m340uart.c ../../shared/dummy_printk_support.c
+console_SOURCES = console/console.c console/m340uart.c \
+    ../../shared/dummy_printk_support.c
 timer_SOURCES = timer/timer.c
 
 noinst_LIBRARIES = libbsp.a

c/src/lib/libbsp/m68k/gen68340/console/Modif_cpu_asm.S

@@ -1,178 +0,0 @@
-/*  cpu_asm.s
- *
- *  This file contains all assembly code for the MC68020 implementation
- *  of RTEMS.
- *
- *  ATTENTION: Modified for benchmarks
- *
- *  COPYRIGHT (c) 1989-1999.
- *  On-Line Applications Research Corporation (OAR).
- *
- *  The license and distribution terms for this file may be
- *  found in the file LICENSE in this distribution or at
- *  http://www.rtems.com/license/LICENSE.
- *
- *  $Id$
- */
-
-#include <rtems/asm.h>
-
-        .text
-
-/*PAGE
- *  void _Debug_ISR_Handler_Console()
- *
- *  This routine provides the RTEMS interrupt management.
- *
- *  NOTE:
- *    Upon entry, the master stack will contain an interrupt stack frame
- *    back to the interrupted thread and the interrupt stack will contain
- *    a throwaway interrupt stack frame.  If dispatching is enabled, this
- *    is the outer most interrupt, and (a context switch is necessary or
- *    the current thread has signals), then set up the master stack to
- *    transfer control to the interrupt dispatcher.
- *  NOTE:
- *    USED TO MESURE THE TIME SPENT IN THE INTERRUPT SUBROUTINE
- *    CS5 - CS8 are linked to an oscilloscope so that you can mesure
- *    RTEMS overhead (BTW it's very short :) )
- */
-
-/*
- *  With this approach, lower priority interrupts may
- *  execute twice if a higher priority interrupt is
- *  acknowledged before _Thread_Dispatch_disable is
- *  increamented and the higher priority interrupt
- *  preforms a context switch after executing. The lower
- *  priority intterrupt will execute (1) at the end of the
- *  higher priority interrupt in the new context if
- *  permitted by the new interrupt level mask, and (2) when
- *  the original context regains the cpu.
- */
-
-#if ( M68K_HAS_VBR == 1)
-.set SR_OFFSET,    0                     | Status register offset
-.set PC_OFFSET,    2                     | Program Counter offset
-.set FVO_OFFSET,   6                     | Format/vector offset
-#else
-.set SR_OFFSET,    2                     | Status register offset
-.set PC_OFFSET,    4                     | Program Counter offset
-.set FVO_OFFSET,   0                     | Format/vector offset placed in the stack
-#endif /* M68K_HAS_VBR */
-
-.set SAVED,        16                    | space for saved registers
-
-        .align  4
-        .global SYM (_Debug_ISR_Handler_Console)
-
-SYM (_Debug_ISR_Handler_Console):
-
-					 |
-	tst.w	0x14000000		 | ALLUME CS5
-					 |
-
-        addql   #1,SYM (_Thread_Dispatch_disable_level) | disable multitasking
-        moveml  d0-d1/a0-a1,a7@-         | save d0-d1,a0-a1
-        movew   a7@(SAVED+FVO_OFFSET),d0 | d0 = F/VO
-        andl    #0x0fff,d0               | d0 = vector offset in vbr
-
-#if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == 1 )
-	movew	sr,d1			| Save status register
-	oriw	#0x700,sr		| Disable interrupts
-	tstl	SYM (_ISR_Nest_level)	| Interrupting an interrupt handler?
-	bne	1f			| Yes, just skip over stack switch code
-	movel	SYM(_CPU_Interrupt_stack_high),a0	| End of interrupt stack
-	movel	a7,a0@-			| Save task stack pointer
-	movel	a0,a7			| Switch to interrupt stack
-1:
-	addql   #1,SYM(_ISR_Nest_level)	| one nest level deeper
-	movew	d1,sr			| Restore status register
-#else
-	addql   #1,SYM (_ISR_Nest_level) | one nest level deeper
-#endif /* CPU_HAS_SOFTWARE_INTERRUPT_STACK == 1 */
-
-#if ( M68K_HAS_PREINDEXING == 1 )
-        movel   @( SYM (_ISR_Vector_table),d0:w:1),a0| fetch the ISR
-#else
-        movel   # SYM (_ISR_Vector_table),a0   | a0 = base of RTEMS table
-        addal   d0,a0                    | a0 = address of vector
-        movel   (a0),a0                  | a0 = address of user routine
-#endif
-
-        lsrl    #2,d0                    | d0 = vector number
-        movel   d0,a7@-                  | push vector number
-
-					 |
-	tst.w	0x18000000		 | ALLUME CS6
-					 |
-
-        jbsr    a0@                      | invoke the user ISR
-
-					 |
-	tst.w	0x18000000		 | ALLUME CS6
-					 |
-
-        addql   #4,a7                    | remove vector number
-
-#if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == 1 )
-	movew	sr,d0			| Save status register
-	oriw	#0x700,sr		| Disable interrupts
-	subql	#1,SYM(_ISR_Nest_level)	| Reduce interrupt-nesting count
-	bne	1f			| Skip if return to interrupt
-	movel	(a7),a7			| Restore task stack pointer
-1:
-	movew	d0,sr			| Restore status register
-#else
-	subql   #1,SYM (_ISR_Nest_level) | one less nest level
-#endif /* CPU_HAS_SOFTWARE_INTERRUPT_STACK == 1 */
-
-        subql   #1,SYM (_Thread_Dispatch_disable_level)
-                                         | unnest multitasking
-        bne     Debug_exit                     | If dispatch disabled, Debug_exit
-
-#if ( M68K_HAS_SEPARATE_STACKS == 1 )
-        movew   #0xf000,d0               | isolate format nibble
-        andw    a7@(SAVED+FVO_OFFSET),d0 | get F/VO
-        cmpiw   #0x1000,d0               | is it a throwaway isf?
-        bne     Debug_exit                     | NOT outer level, so branch
-#endif
-
-        tstl    SYM (_Context_Switch_necessary)
-                                         | Is thread switch necessary?
-        bne     bframe                   | Yes, invoke dispatcher
-
-        tstl    SYM (_ISR_Signals_to_thread_executing)
-                                         | signals sent to Run_thread
-                                         |   while in interrupt handler?
-        beq     Debug_exit               | No, then Debug_exit
-
-bframe: clrl    SYM (_ISR_Signals_to_thread_executing)
-                                         | If sent, will be processed
-#if ( M68K_HAS_SEPARATE_STACKS == 1 )
-        movec   msp,a0                   | a0 = master stack pointer
-        movew   #0,a0@-                  | push format word
-        movel   # SYM (_ISR_Dispatch),a0@- | push return addr
-        | filter out the trace bit to stop single step debugging breaking
-        movew   a0@(6+SR_OFFSET),d0
-        andw    #0x7FFF,d0
-        movew   d0,a0@-                  | push thread sr
-        movec   a0,msp                   | set master stack pointer
-#else
-
-        | filter out the trace bit to stop single step debugging breaking
-        movew   a7@(16+SR_OFFSET),d0
-        andw    #0x7FFF,d0
-        movew   d0,sr
-        jsr SYM (_Thread_Dispatch)
-#endif
-
-Debug_exit:   moveml  a7@+,d0-d1/a0-a1         | restore d0-d1,a0-a1
-#if ( M68K_HAS_VBR == 0 )
-        addql   #2,a7                    | pop format/id
-#endif /* M68K_HAS_VBR */
-
-					 |
-	tst.w	0x1C000000		 | ALLUME CS7
-					 |
-
-        rte                              | return to thread
-                                         |   OR _Isr_dispatch

c/src/lib/libbsp/m68k/genmcf548x/include/.cvsignore

@@ -0,0 +1,4 @@
+stamp-h
+stamp-h.in
+bspopts.h
+bspopts.h.in

c/src/lib/libbsp/m68k/mcf52235/include/.cvsignore

@@ -0,0 +1,4 @@
+stamp-h
+stamp-h.in
+bspopts.h
+bspopts.h.in

c/src/lib/libbsp/m68k/mcf5329/include/.cvsignore

@@ -0,0 +1,4 @@
+stamp-h
+stamp-h.in
+bspopts.h
+bspopts.h.in

c/src/lib/libbsp/m68k/mvme167/ChangeLog

@@ -1,3 +1,14 @@
+2009-02-17	Till Straumann <strauman@slac.stanford.edu>
+
+	PR 1371/bsps
+	* network/network.c: mvme167 network driver buggy.
+
+2009-02-17	Till Straumann <strauman@slac.stanford.edu>
+
+	PR 1370/bsps
+	* console/console.c: mvme167 console driver BSP_output_char fails to
+	convert \n -> \n\r
+
 2008-12-08	Ralf Corsépius <ralf.corsepius@rtems.org>
 
 	* bsp_specs: Backport from CVS-HEAD.

c/src/lib/libbsp/m68k/mvme167/console/console.c

@@ -161,6 +161,15 @@ int _167Bug_pollWrite( int minor, const char *buf, int len );
 static void _BSP_output_char( char c );
 BSP_output_char_function_type BSP_output_char = _BSP_output_char;
 
+/* '\r' character in memory. This used to live on
+ * the stack but storing the '\r' character is
+ * optimized away by gcc-4.3.2 (since it seems to
+ * be unused [only referenced from inline assembly
+ * code in _167Bug_pollWrite()]).
+ * Hence we make it a global constant.
+ */
+static const char cr_char = '\r';
+
 /* Channel info */
 /* static */ volatile struct {
   void *tty;                    /* Really a struct rtems_termios_tty * */
@@ -1366,12 +1375,11 @@ rtems_status_code do_poll_write(
 {
   rtems_libio_rw_args_t *rw_args = arg;
   uint32_t   i;
-  char cr ='\r';
 
   for( i = 0; i < rw_args->count; i++ ) {
     _167Bug_pollWrite(minor, &(rw_args->buffer[i]), 1);
     if ( rw_args->buffer[i] == '\n' )
-      _167Bug_pollWrite(minor, &cr, 1);
+      _167Bug_pollWrite(minor, &cr_char, 1);
   }
   rw_args->bytes_moved = i;
   return RTEMS_SUCCESSFUL;
@@ -1385,7 +1393,6 @@ rtems_status_code do_poll_write(
 void _BSP_output_char(char c)
 {
   rtems_device_minor_number printk_minor;
-  char cr ='\r';
 
   /*
    *  Can't rely on console_initialize having been called before this function
@@ -1399,7 +1406,7 @@ void _BSP_output_char(char c)
 
   _167Bug_pollWrite(printk_minor, &c, 1);
   if ( c == '\n' )
-      _167Bug_pollWrite(printk_minor, &cr, 1);
+      _167Bug_pollWrite(printk_minor, &cr_char, 1);
 }
 
 /*

c/src/lib/libbsp/m68k/mvme167/network/network.c

@@ -29,6 +29,10 @@
 #define DBG_PACKETS
 */
 
+#define IGNORE_SPURIOUS_IRQ
+#define IGNORE_NO_RFA
+#define IGNORE_MULTIPLE_RF
+
 /*
  * Default number of buffer descriptors and buffer sizes.
  */
@@ -69,8 +73,8 @@
 #include "uti596.h"
 
 /* If we are running interrupt driven I/O no debug output is printed */
-#if CD2401_POLLED_IO == 1
-   #define printk(arglist) printk arglist;
+#if CD2401_IO_MODE == 0
+   #define printk(arglist) do { printk arglist; printk("\r"); } while (0);
 #else
    #define printk(arglist)
 #endif
@@ -906,7 +910,7 @@ static int uti596_initRFA( int num )
   } /* end for */
 
   uti596_softc.pEndRFA->next = I596_NULL;
-  UTI_596_ASSERT(uti596_softc.countRFD == RX_BUF_COUNT,"INIT:WRONG RFD COUNT\n" )
+  UTI_596_ASSERT(uti596_softc.countRFD == num,"INIT:WRONG RFD COUNT\n" )
 
   #ifdef DBG_INIT
   printk (("uti596_initRFA: Head of RFA is buffer %p \n\
@@ -1029,7 +1033,7 @@ void uti596_initialize(
   /* write the SYSBUS: interrupt pin active high, LOCK disabled,
    * internal triggering, linear mode
    */
-  sc->pScp->sysbus = 0x54;
+  sc->pScp->sysbus = 0x44;
 
   /* provide the iscp to the scp, keep a pointer for our use */
   sc->pScp->iscp_pointer = word_swap((unsigned long)&sc->iscp);
@@ -1219,7 +1223,7 @@ void uti596_reset( void )
     sc-> pLastUnkRFD = I596_NULL;
   }
 
-  sc->pEndRFA->next = sc->pSavedRfdQueue;
+  sc->pEndRFA->next = (i596_rfd*)word_swap((uint32_t)sc->pSavedRfdQueue);
   if ( sc->pSavedRfdQueue != I596_NULL ) {
     sc->pEndRFA = sc->pEndSavedQueue;
     sc->pSavedRfdQueue = sc->pEndSavedQueue = I596_NULL;
@@ -1846,6 +1850,12 @@ void uti596_init(
     printk(("uti596_init: After attach, status of board = 0x%x\n", sc->scb.status ))
     #endif
   }
+ 
+  /*
+   * In case the ISR discovers there are no resources it reclaims
+   * them and restarts
+   */
+  sc->started = 1;
 
   /*
    * Enable receiver
@@ -2132,13 +2142,15 @@ void uti596_resetDaemon(
   rtems_vector_number irq
 )
 {
+int fullStatus;
+
 	#ifdef DBG_ISR
   printk(("uti596_DynamicInterruptHandler: begins"))
 	#endif
 
  uti596_wait (&uti596_softc, UTI596_WAIT_FOR_CU_ACCEPT);
 
- scbStatus = uti596_softc.scb.status & 0xf000;
+ scbStatus = (fullStatus = uti596_softc.scb.status) & 0xf000;
 
  if ( scbStatus ) {
    /* acknowledge interrupts */
@@ -2166,8 +2178,10 @@ void uti596_resetDaemon(
     }
   }
   else {
-    printk(("\n***ERROR: Spurious interrupt. Resetting...\n"))
+#ifndef IGNORE_SPURIOUS_IRQ
+    printk(("\n***ERROR: Spurious interrupt (full status 0x%x). Resetting...\n", fullStatus))
     uti596_softc.nic_reset = 1;
+#endif
   }
 
   if ( (scbStatus & SCB_STAT_CX) && !(scbStatus & SCB_STAT_CNA) ) {
@@ -2217,8 +2231,10 @@ void uti596_resetDaemon(
 		#endif
     if ( uti596_softc.pBeginRFA == I596_NULL ||
        !( uti596_softc.pBeginRFA -> stat & STAT_C)) {
+#ifndef IGNORE_NO_RFA
       uti596_dump_scb();
       uti596_softc.nic_reset = 1;
+#endif
     }
     else {
       while ( uti596_softc.pBeginRFA != I596_NULL &&
@@ -2228,9 +2244,11 @@ void uti596_resetDaemon(
         printk(("uti596_DynamicInterruptHandler: pBeginRFA != NULL\n"))
 				#endif
         count_rx ++;
+#ifndef IGNORE_MULTIPLE_RF
         if ( count_rx > 1) {
-          printk(("****WARNING: Received 2 frames on 1 interrupt \n"))
-                                }
+          printk(("****WARNING: Received %i frames on 1 interrupt \n", count_rx))
+		}
+#endif
        /* Give Received Frame to the ULCS */
         uti596_softc.countRFD--;
 
@@ -2711,7 +2729,7 @@ static void dumpQ( void )
 
   for( pRfd = uti596_softc.pSavedRfdQueue;
        pRfd != I596_NULL;
-       pRfd = pRfd -> next) {
+       pRfd = (i596_rfd*)word_swap((uint32_t)pRfd -> next)) {
       printk(("pRfd: %p, stat: 0x%x cmd: 0x%x\n",pRfd,pRfd -> stat,pRfd -> cmd))
   }
 
@@ -2719,7 +2737,7 @@ static void dumpQ( void )
 
   for( pRfd = uti596_softc.pInboundFrameQueue;
        pRfd != I596_NULL;
-       pRfd = pRfd -> next) {
+       pRfd = (i596_rfd*)word_swap((uint32_t)pRfd -> next)) {
     printk(("pRfd: %p, stat: 0x%x cmd: 0x%x\n",pRfd,pRfd -> stat,pRfd -> cmd))
   }
 
@@ -2728,7 +2746,7 @@ static void dumpQ( void )
 
   for( pRfd = uti596_softc.pBeginRFA;
        pRfd != I596_NULL;
-       pRfd = pRfd -> next) {
+       pRfd = (i596_rfd*)word_swap((uint32_t)pRfd -> next)) {
     printk(("pRfd: %p, stat: 0x%x cmd: 0x%x\n",pRfd,pRfd -> stat,pRfd -> cmd))
   }
 }
@@ -2751,7 +2769,7 @@ static void show_buffers (void)
 
   for ( pRfd = uti596_softc.pBeginRFA;
         pRfd != I596_NULL;
-        pRfd = pRfd->next) {
+        pRfd = (i596_rfd *)word_swap((uint32_t)pRfd->next) ) {
     printk(("Frame @ %p, status: %2.2x, cmd: %2.2x\n",
             pRfd, pRfd->stat, pRfd->cmd))
         }
@@ -2759,7 +2777,7 @@ static void show_buffers (void)
 
   for ( pRfd = uti596_softc.pInboundFrameQueue;
         pRfd != I596_NULL;
-        pRfd = pRfd->next) {
+        pRfd = (i596_rfd *)word_swap((uint32_t)pRfd->next) ) {
     printk(("Frame @ %p, status: %2.2x, cmd: %2.2x\n",
             pRfd, pRfd->stat, pRfd->cmd))
         }
@@ -2768,7 +2786,7 @@ static void show_buffers (void)
 
   for ( pRfd = uti596_softc.pSavedRfdQueue;
         pRfd != I596_NULL;
-        pRfd = pRfd->next) {
+        pRfd = (i596_rfd *)word_swap((uint32_t)pRfd->next) ) {
     printk(("Frame @ %p, status: %2.2x, cmd: %2.2x\n",
              pRfd, pRfd->stat, pRfd->cmd))
   }
@@ -2793,7 +2811,7 @@ static void show_queues(void)
   for ( pRfd = uti596_softc.pSavedRfdQueue;
         pRfd != I596_NULL &&
         pRfd != NULL;
-        pRfd = pRfd->next) {
+        pRfd = (i596_rfd *)word_swap((uint32_t)pRfd->next) ) {
     printk(("0x%p\n", pRfd))
   }
 
@@ -2804,7 +2822,7 @@ static void show_queues(void)
   for ( pRfd = uti596_softc.pBeginRFA;
         pRfd != I596_NULL &&
         pRfd != NULL;
-        pRfd = pRfd->next) {
+        pRfd = (i596_rfd *)word_swap((uint32_t)pRfd->next) ) {
     printk(("0x%p\n", pRfd))
   }
 

c/src/lib/libbsp/m68k/uC5282/ChangeLog

@@ -1,3 +1,38 @@
+2009-09-09	Till Straumann <strauman@slac.stanford.edu>
+
+	* startup/bspstart.c: Added dummy implementation of firmware
+	syscalls for use with QEMU. Dummy handler is installed if no
+	pre-existing firmware handler is found.
+
+2009-07-30  Eric Norum <norume@aps.anl.gov>
+
+	* include/bsp.h, network/network.c, startup/bspstart.c:  Try enabling
+    the data cache.
+
+2009-07-28  Eric Norum <norume@aps.anl.gov>
+
+   PR 1420/bsps
+   * startup/bspstart.c: Turn on buffered writes to DRAM. As Device Errata
+      SECF124 notes this may cause double writes, but that's not really a big
+      problem and benchmarking tests have shown that buffered writes do gain
+      some performance.
+
+2009-06-02	Eric Norum <norume@aps.anl.gov>
+
+	PR 1420/bsps
+	* startup/bspstart.c: Turn off buffered writes.
+
+2009-03-02	Till Straumann <strauman@slac.stanford.edu>
+
+	PR 1375/bsps
+	* clock/clock.c: Correct implementation of nanoseconds since last tick
+	handler.
+
+2009-01-21	Eric Norum <norume@aps.anl.gov>
+
+	PR 1358/bsps
+	* clock/clock.c: Fix time-access bug in uc5282 BSP.
+
 2008-12-08	Ralf Corsépius <ralf.corsepius@rtems.org>
 
 	* bsp_specs: Backport from CVS-HEAD.

c/src/lib/libbsp/m68k/uC5282/clock/clock.c

@@ -30,15 +30,15 @@ extern int __SRAMBASE[];
 #define IDLE_COUNTER      __SRAMBASE[0]
 #define FILTERED_IDLE     __SRAMBASE[1]
 #define MAX_IDLE_COUNT    __SRAMBASE[2]
-#define PCNTR_AT_TICK     (*(uint16 *)&__SRAMBASE[3])
+#define USEC_PER_TICK     __SRAMBASE[3]
 #define FILTER_SHIFT    6
 
 uint32_t bsp_clock_nanoseconds_since_last_tick(void)
 {
     int i = MCF5282_PIT3_PCNTR;
     if (MCF5282_PIT3_PCSR & MCF5282_PIT_PCSR_PIF)
-        i = MCF5282_PIT3_PCNTR + MCF5282_PIT3_PMR;
-    return (i - PCNTR_AT_TICK) * 1000;
+        i = MCF5282_PIT3_PCNTR - USEC_PER_TICK;
+    return (USEC_PER_TICK - i) * 1000;
 }
 
 #define Clock_driver_nanoseconds_since_last_tick bsp_clock_nanoseconds_since_last_tick
@@ -53,7 +53,6 @@ uint32_t bsp_clock_nanoseconds_since_last_tick(void)
         if (idle > MAX_IDLE_COUNT)                                           \
             MAX_IDLE_COUNT = idle;                                           \
         FILTERED_IDLE = idle + FILTERED_IDLE - (FILTERED_IDLE>>FILTER_SHIFT);\
-        PCNTR_AT_TICK = MCF5282_PIT3_PCNTR;                                  \
         MCF5282_PIT3_PCSR |= MCF5282_PIT_PCSR_PIF;                           \
     } while (0)
 
@@ -102,12 +101,12 @@ uint32_t bsp_clock_nanoseconds_since_last_tick(void)
                             MCF5282_PIT_PCSR_OVW |                       \
                             MCF5282_PIT_PCSR_PIE |                       \
                             MCF5282_PIT_PCSR_RLD;                        \
-        MCF5282_PIT3_PMR = rtems_configuration_get_microseconds_per_tick() - 1;  \
+        USEC_PER_TICK = rtems_configuration_get_microseconds_per_tick(); \
+        MCF5282_PIT3_PMR = USEC_PER_TICK - 1;                            \
         MCF5282_PIT3_PCSR = MCF5282_PIT_PCSR_PRE(preScaleCode) |         \
                             MCF5282_PIT_PCSR_PIE |                       \
                             MCF5282_PIT_PCSR_RLD |                       \
                             MCF5282_PIT_PCSR_EN;                         \
-        PCNTR_AT_TICK = MCF5282_PIT3_PCNTR;                              \
     } while (0)
 
 /*

c/src/lib/libbsp/m68k/uC5282/include/bsp.h

@@ -31,7 +31,7 @@ extern "C" {
  * Uncomment to use instruction/data cache
  * Leave commented to use instruction-only cache
  */
-/* #define RTEMS_MCF5282_BSP_ENABLE_DATA_CACHE */
+#define RTEMS_MCF5282_BSP_ENABLE_DATA_CACHE
 
 /***************************************************************************/
 /**  Hardware data structure headers                                      **/

c/src/lib/libbsp/m68k/uC5282/network/network.c

@@ -492,13 +492,9 @@ fec_rxDaemon (void *arg)
 #ifdef RTEMS_MCF5282_BSP_ENABLE_DATA_CACHE
             /*
              * Invalidate the cache.  The cache is so small that it's
-             * more efficient to just invalidate the whole thing unless
-             * the packet is very small.
+             * reasonable to simply invalidate the whole thing.
              */
-            if (len < 128)
-                rtems_cache_invalidate_multiple_data_lines(m->m_data, len);
-            else
-                rtems_cache_invalidate_entire_data();
+            rtems_cache_invalidate_entire_data();
 #endif
             m->m_len = m->m_pkthdr.len = len - sizeof(struct ether_header);
             eh = mtod(m, struct ether_header *);

c/src/lib/libbsp/m68k/uC5282/startup/bspstart.c

@@ -57,6 +57,20 @@
  * should be followed immediately by a NOP instruction.  This avoids the cache
  * corruption problem.
  * DATECODES AFFECTED: All
+ *
+ *
+ * Buffered writes must be disabled as described in "MCF5282 Chip Errata",
+ * MCF5282DE, Rev. 6, 5/2009:
+ *   SECF124: Buffered Write May Be Executed Twice 
+ *   Errata type: Silicon 
+ *   Affected component: Cache 
+ *   Description: If buffered writes are enabled using the CACR or ACR
+ *                registers, the imprecise write transaction generated
+ *                by a buffered write may be executed twice. 
+ *   Workaround: Do not enable buffered writes in the CACR or ACR registers: 
+ *               CACR[8] = DBWE (default buffered write enable) must be 0 
+ *               ACRn[5] = BUFW (buffered write enable) must be 0 
+ *   Fix plan: Currently, there are no plans to fix this. 
  */
 #define m68k_set_cacr_nop(_cacr) asm volatile ("movec %0,%%cacr\n\tnop" : : "d" (_cacr))
 #define m68k_set_cacr(_cacr) asm volatile ("movec %0,%%cacr" : : "d" (_cacr))
@@ -67,7 +81,7 @@
  * Read/write copy of cache registers
  *   Split instruction/data or instruction-only
  *   Allow CPUSHL to invalidate a cache line
- *   Enable buffered writes
+ *   Disable buffered writes
  *   No burst transfers on non-cacheable accesses
  *   Default cache mode is *disabled* (cache only ACRx areas)
  */
@@ -75,7 +89,6 @@ uint32_t mcf5282_cacr_mode = MCF5XXX_CACR_CENB |
 #ifndef RTEMS_MCF5282_BSP_ENABLE_DATA_CACHE
                              MCF5XXX_CACR_DISD |
 #endif
-                             MCF5XXX_CACR_DBWE |
                              MCF5XXX_CACR_DCM;
 uint32_t mcf5282_acr0_mode = 0;
 uint32_t mcf5282_acr1_mode = 0;
@@ -99,7 +112,7 @@ void _CPU_cache_enable_instruction(void)
 
     rtems_interrupt_disable(level);
     mcf5282_cacr_mode &= ~MCF5XXX_CACR_DIDI;
-    m68k_set_cacr(mcf5282_cacr_mode);
+    m68k_set_cacr_nop(mcf5282_cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVI);
     rtems_interrupt_enable(level);
 }
 
@@ -133,8 +146,8 @@ void _CPU_cache_enable_data(void)
     rtems_interrupt_level level;
 
     rtems_interrupt_disable(level);
-    mcf5282_cacr_mode &= ~MCF5XXX_CACR_CENB;
-    m68k_set_cacr(mcf5282_cacr_mode);
+    mcf5282_cacr_mode &= ~MCF5XXX_CACR_DISD;
+    m68k_set_cacr_nop(mcf5282_cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVD);
     rtems_interrupt_enable(level);
 #endif
 }
@@ -145,8 +158,7 @@ void _CPU_cache_disable_data(void)
     rtems_interrupt_level level;
 
     rtems_interrupt_disable(level);
-    rtems_interrupt_disable(level);
-    mcf5282_cacr_mode |= MCF5XXX_CACR_CENB;
+    mcf5282_cacr_mode |= MCF5XXX_CACR_DISD;
     m68k_set_cacr(mcf5282_cacr_mode);
     rtems_interrupt_enable(level);
 #endif
@@ -176,6 +188,8 @@ void _CPU_cache_invalidate_1_data_line(const void *addr)
 void bsp_libc_init( void *, uint32_t, int );
 void bsp_pretasking_hook(void);         /* m68k version */
 
+extern void bsp_fake_syscall();
+
 /*
  * The Arcturus boot ROM prints exception information improperly
  * so use this default exception handler instead.  This one also
@@ -248,6 +262,13 @@ void bsp_start( void )
         if (i != (32+2)) /* Catch all but bootrom system calls */
             *((void (**)(int))(i * 4)) = handler;
 
+	/*
+	 * Qemu has no trap handler; install our fake syscall
+	 * implementation if there is no existing handler.
+	 */
+	if ( 0 == *((void (**)(int))((32+2) * 4)) )
+		*((void (**)(int))((32+2) * 4)) = bsp_fake_syscall;
+
   /*
    *  Need to "allocate" the memory for the RTEMS Workspace and
    *  tell the RTEMS configuration where it is.  This memory is
@@ -265,12 +286,16 @@ void bsp_start( void )
 
   /*
    * Cache SDRAM
+   * Enable buffered writes
+   * As Device Errata SECF124 notes this may cause double writes,
+   * but that's not really a big problem and benchmarking tests have
+   * shown that buffered writes do gain some performance.
    */
   mcf5282_acr0_mode = MCF5XXX_ACR_AB((uint32_t)_RamBase)     |
                       MCF5XXX_ACR_AM((uint32_t)_RamSize-1)   |
                       MCF5XXX_ACR_EN                         |
-                      MCF5XXX_ACR_BWE                        |
-                      MCF5XXX_ACR_SM_IGNORE;
+                      MCF5XXX_ACR_SM_IGNORE                  |
+                      MCF5XXX_ACR_BWE;
   m68k_set_acr0(mcf5282_acr0_mode);
 
   /*
@@ -403,6 +428,37 @@ syscall_2(int, program, bsp_mnode_t *, chain, int, flags)
 syscall_3(int, flash_erase_range, volatile unsigned short *, flashptr, int, start, int, end);
 syscall_3(int, flash_write_range, volatile unsigned short *, flashptr, bsp_mnode_t *, chain, int, offset);
 
+/* Provide a dummy-implementation of these syscalls
+ * for qemu (which lacks the firmware).
+ */
+
+#define __STR(x)    #x
+#define __STRSTR(x) __STR(x)
+#define ERRVAL      __STRSTR(EACCES)
+
+/* reset-control register */
+#define RCR "__IPSBAR + 0x110000"
+
+asm(
+    "bsp_fake_syscall:         \n"
+    "   cmpl  #0,  %d0         \n" /* sysreset    */
+    "   bne   1f               \n"
+    "   moveb #0x80, %d0       \n"
+    "   moveb %d0, "RCR"       \n" /* reset-controller */
+        /* should never get here - but we'd return -EACCESS if we do */
+    "1:                        \n"
+    "   cmpl  #12, %d0         \n" /* gethwaddr   */
+    "   beq   2f               \n"
+    "   cmpl  #14, %d0         \n" /* getbenv     */
+    "   beq   2f               \n"
+    "   movel #-"ERRVAL", %d0  \n" /* return -EACCESS */
+    "   rte                    \n"
+    "2:                        \n"
+    "   movel #0,  %d0         \n" /* return NULL */
+    "   rte                    \n"
+);
+
+
 /*
  * 'Extended BSP' routines
  * Should move to cpukit/score/cpu/m68k/cpu.c someday.

c/src/lib/libbsp/mips/csb350/start/regs.h

@@ -0,0 +1,138 @@
+/*
+ * regs.S -- standard MIPS register names from
+ * newlib-1.8.2/libgloss/mips and adapted.
+ *
+ * Copyright (c) 1995 Cygnus Support
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/* Standard MIPS register names: */
+#define zero	$0
+#define z0	$0
+#define v0	$2
+#define v1	$3
+#define a0	$4
+#define a1	$5
+#define a2	$6
+#define a3	$7
+#define t0	$8
+#define t1	$9
+#define t2	$10
+#define t3	$11
+#define t4	$12
+#define t5	$13
+#define t6	$14
+#define t7	$15
+#define s0	$16
+#define s1	$17
+#define s2	$18
+#define s3	$19
+#define s4	$20
+#define s5	$21
+#define s6	$22
+#define s7	$23
+#define t8	$24
+#define t9	$25
+#define k0	$26	/* kernel private register 0 */
+#define k1	$27	/* kernel private register 1 */
+#define gp	$28	/* global data pointer */
+#define sp 	$29	/* stack-pointer */
+#define fp	$30	/* frame-pointer */
+#define ra	$31	/* return address */
+#define pc	$pc	/* pc, used on mips16 */
+
+#define fp0	$f0
+#define fp1	$f1
+
+/* Useful memory constants: */
+#define K0BASE		0x80000000
+#ifndef __mips64
+#define K1BASE		0xA0000000
+#else
+#define K1BASE		0xFFFFFFFFA0000000LL
+#endif
+
+#define PHYS_TO_K1(a)   ((unsigned)(a) | K1BASE)
+
+/* Standard Co-Processor 0 register numbers: */
+#define C0_COUNT	$9		/* Count Register */
+#define C0_SR		$12		/* Status Register */
+#define C0_CAUSE	$13		/* last exception description */
+#define C0_EPC		$14		/* Exception error address */
+#define C0_CONFIG	$16		/* CPU configuration */
+
+/* Standard Status Register bitmasks: */
+#define SR_CU1		0x20000000	/* Mark CP1 as usable */
+#define SR_FR		0x04000000	/* Enable MIPS III FP registers */
+#define SR_BEV		0x00400000	/* Controls location of exception vectors */
+#define SR_PE		0x00100000	/* Mark soft reset (clear parity error) */
+
+#define SR_KX		0x00000080	/* Kernel extended addressing enabled */
+#define SR_SX		0x00000040	/* Supervisor extended addressing enabled */
+#define SR_UX		0x00000020	/* User extended addressing enabled */
+
+/* Standard (R4000) cache operations. Taken from "MIPS R4000
+   Microprocessor User's Manual" 2nd edition: */
+
+#define CACHE_I		(0)	/* primary instruction */
+#define CACHE_D		(1)	/* primary data */
+#define CACHE_SI	(2)	/* secondary instruction */
+#define CACHE_SD	(3)	/* secondary data (or combined instruction/data) */
+
+#define INDEX_INVALIDATE		(0)	/* also encodes WRITEBACK if CACHE_D or CACHE_SD */
+#define INDEX_LOAD_TAG			(1)
+#define INDEX_STORE_TAG			(2)
+#define CREATE_DIRTY_EXCLUSIVE		(3)	/* CACHE_D and CACHE_SD only */
+#define HIT_INVALIDATE			(4)
+#define CACHE_FILL			(5)	/* CACHE_I only */
+#define HIT_WRITEBACK_INVALIDATE	(5)	/* CACHE_D and CACHE_SD only */
+#define HIT_WRITEBACK			(6)	/* CACHE_I, CACHE_D and CACHE_SD only */
+#define HIT_SET_VIRTUAL			(7)	/* CACHE_SI and CACHE_SD only */
+
+#define BUILD_CACHE_OP(o,c)		(((o) << 2) | (c))
+
+/* Individual cache operations: */
+#define INDEX_INVALIDATE_I		BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_I)
+#define INDEX_WRITEBACK_INVALIDATE_D	BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_D)
+#define INDEX_INVALIDATE_SI             BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_SI)
+#define INDEX_WRITEBACK_INVALIDATE_SD	BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_SD)
+
+#define INDEX_LOAD_TAG_I		BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_I)
+#define INDEX_LOAD_TAG_D                BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_D)
+#define INDEX_LOAD_TAG_SI               BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_SI)
+#define INDEX_LOAD_TAG_SD               BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_SD)
+
+#define INDEX_STORE_TAG_I              	BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_I)
+#define INDEX_STORE_TAG_D               BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_D)
+#define INDEX_STORE_TAG_SI              BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_SI)
+#define INDEX_STORE_TAG_SD              BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_SD)
+
+#define CREATE_DIRTY_EXCLUSIVE_D        BUILD_CACHE_OP(CREATE_DIRTY_EXCLUSIVE,CACHE_D)
+#define CREATE_DIRTY_EXCLUSIVE_SD       BUILD_CACHE_OP(CREATE_DIRTY_EXCLUSIVE,CACHE_SD)
+
+#define HIT_INVALIDATE_I                BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_I)
+#define HIT_INVALIDATE_D                BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_D)
+#define HIT_INVALIDATE_SI               BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_SI)
+#define HIT_INVALIDATE_SD               BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_SD)
+
+#define CACHE_FILL_I                    BUILD_CACHE_OP(CACHE_FILL,CACHE_I)
+#define HIT_WRITEBACK_INVALIDATE_D      BUILD_CACHE_OP(HIT_WRITEBACK_INVALIDATE,CACHE_D)
+#define HIT_WRITEBACK_INVALIDATE_SD     BUILD_CACHE_OP(HIT_WRITEBACK_INVALIDATE,CACHE_SD)
+
+#define HIT_WRITEBACK_I                 BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_I)
+#define HIT_WRITEBACK_D                 BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_D)
+#define HIT_WRITEBACK_SD                BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_SD)
+
+#define HIT_SET_VIRTUAL_SI		BUILD_CACHE_OP(HIT_SET_VIRTUAL,CACHE_SI)
+#define HIT_SET_VIRTUAL_SD              BUILD_CACHE_OP(HIT_SET_VIRTUAL,CACHE_SD)
+
+/*> EOF regs.S <*/

c/src/lib/libbsp/mips/genmongoosev/start/regs.h

@@ -0,0 +1,148 @@
+/*
+ * regs.S -- standard MIPS register names from
+ * newlib-1.8.2/libgloss/mips and adapted.
+ *
+ * Copyright (c) 1995 Cygnus Support
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/* Standard MIPS register names: */
+#define zero    $0
+#define z0  $0
+#define v0  $2
+#define v1  $3
+#define a0  $4
+#define a1  $5
+#define a2  $6
+#define a3  $7
+#define t0  $8
+#define t1  $9
+#define t2  $10
+#define t3  $11
+#define t4  $12
+#define t5  $13
+#define t6  $14
+#define t7  $15
+#define s0  $16
+#define s1  $17
+#define s2  $18
+#define s3  $19
+#define s4  $20
+#define s5  $21
+#define s6  $22
+#define s7  $23
+#define t8  $24
+#define t9  $25
+#define k0  $26 /* kernel private register 0 */
+#define k1  $27 /* kernel private register 1 */
+#define gp  $28 /* global data pointer */
+#define sp  $29 /* stack-pointer */
+#define fp  $30 /* frame-pointer */
+#define ra  $31 /* return address */
+#define pc  $pc /* pc, used on mips16 */
+
+#define fp0 $f0
+#define fp1 $f1
+
+#define WATCHDOG    0xBE000000
+
+/* Useful memory constants: */
+#define K0BASE      0x80000000
+#ifndef __mips64
+   #define K1BASE       0xA0000000
+#else
+#define K1BASE      0xFFFFFFFFA0000000LL
+#endif
+
+#define PHYS_TO_K1(a)   ((unsigned)(a) | K1BASE)
+
+/* Standard Co-Processor 0 register numbers: */
+#define C0_DCIC     $7      /* debug & cache invalidate control */
+#define C0_COUNT    $9      /* Count Register */
+#define C0_SR           $12         /* Status Register */
+#define C0_CAUSE    $13     /* last exception description */
+#define C0_EPC      $14         /* Exception error address */
+#define C0_CONFIG   $16     /* CPU configuration */
+
+/* Standard Status Register bitmasks: */
+#define SR_CU0          0x10000000
+#define SR_CU1      0x20000000  /* Mark CP1 as usable */
+#define SR_FR       0x04000000  /* Enable MIPS III FP registers */
+#define SR_BEV      0x00400000  /* Controls location of exception vectors */
+#define SR_PE       0x00100000  /* Mark soft reset (clear parity error) */
+
+/* defined differently for Mongoose5- we don't use these anymore */
+#if UNUSED
+#define SR_KX     0x00000080  /* Kernel extended addressing enabled */
+#define SR_SX     0x00000040  /* Supervisor extended addressing enabled */
+#define SR_UX     0x00000020  /* User extended addressing enabled */
+#endif
+
+/* R3000 */
+#define SR_ISC      0x00010000  /* Isolate data cache */
+
+/* Standard (R4000) cache operations. Taken from "MIPS R4000
+   Microprocessor User's Manual" 2nd edition: */
+
+#define CACHE_I     (0) /* primary instruction */
+#define CACHE_D     (1) /* primary data */
+#define CACHE_SI    (2) /* secondary instruction */
+#define CACHE_SD    (3) /* secondary data (or combined instruction/data) */
+
+#define INDEX_INVALIDATE        (0) /* also encodes WRITEBACK if CACHE_D or CACHE_SD */
+#define INDEX_LOAD_TAG          (1)
+#define INDEX_STORE_TAG         (2)
+#define CREATE_DIRTY_EXCLUSIVE      (3) /* CACHE_D and CACHE_SD only */
+#define HIT_INVALIDATE          (4)
+#define CACHE_FILL          (5) /* CACHE_I only */
+#define HIT_WRITEBACK_INVALIDATE    (5) /* CACHE_D and CACHE_SD only */
+#define HIT_WRITEBACK           (6) /* CACHE_I, CACHE_D and CACHE_SD only */
+#define HIT_SET_VIRTUAL         (7) /* CACHE_SI and CACHE_SD only */
+
+#define BUILD_CACHE_OP(o,c)     (((o) << 2) | (c))
+
+/* Individual cache operations: */
+#define INDEX_INVALIDATE_I      BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_I)
+#define INDEX_WRITEBACK_INVALIDATE_D    BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_D)
+#define INDEX_INVALIDATE_SI             BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_SI)
+#define INDEX_WRITEBACK_INVALIDATE_SD   BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_SD)
+
+#define INDEX_LOAD_TAG_I        BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_I)
+#define INDEX_LOAD_TAG_D                BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_D)
+#define INDEX_LOAD_TAG_SI               BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_SI)
+#define INDEX_LOAD_TAG_SD               BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_SD)
+
+#define INDEX_STORE_TAG_I               BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_I)
+#define INDEX_STORE_TAG_D               BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_D)
+#define INDEX_STORE_TAG_SI              BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_SI)
+#define INDEX_STORE_TAG_SD              BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_SD)
+
+#define CREATE_DIRTY_EXCLUSIVE_D        BUILD_CACHE_OP(CREATE_DIRTY_EXCLUSIVE,CACHE_D)
+#define CREATE_DIRTY_EXCLUSIVE_SD       BUILD_CACHE_OP(CREATE_DIRTY_EXCLUSIVE,CACHE_SD)
+
+#define HIT_INVALIDATE_I                BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_I)
+#define HIT_INVALIDATE_D                BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_D)
+#define HIT_INVALIDATE_SI               BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_SI)
+#define HIT_INVALIDATE_SD               BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_SD)
+
+#define CACHE_FILL_I                    BUILD_CACHE_OP(CACHE_FILL,CACHE_I)
+#define HIT_WRITEBACK_INVALIDATE_D      BUILD_CACHE_OP(HIT_WRITEBACK_INVALIDATE,CACHE_D)
+#define HIT_WRITEBACK_INVALIDATE_SD     BUILD_CACHE_OP(HIT_WRITEBACK_INVALIDATE,CACHE_SD)
+
+#define HIT_WRITEBACK_I                 BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_I)
+#define HIT_WRITEBACK_D                 BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_D)
+#define HIT_WRITEBACK_SD                BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_SD)
+
+#define HIT_SET_VIRTUAL_SI      BUILD_CACHE_OP(HIT_SET_VIRTUAL,CACHE_SI)
+#define HIT_SET_VIRTUAL_SD              BUILD_CACHE_OP(HIT_SET_VIRTUAL,CACHE_SD)
+
+/*> EOF regs.S <*/

c/src/lib/libbsp/mips/hurricane/ChangeLog

@@ -1,3 +1,12 @@
+2009-03-12	Joel Sherrill <joel.sherrill@OARcorp.com>
+
+	PR 1385/cpukit
+	* startup/exception.S: When the type rtems_boolean was switched to the
+	C99 bool, the size changed from 4 bytes to 1 byte. The interrupt
+	dispatching code accesses two boolean variables for scheduling
+	purposes and the assembly implementations of this code did not get
+	updated.
+
 2008-12-08	Ralf Corsépius <ralf.corsepius@rtems.org>
 
 	* bsp_specs: Backport from CVS-HEAD.

c/src/lib/libbsp/mips/hurricane/liblnk/regs.h

@@ -0,0 +1,137 @@
+/*
+ * regs.S -- standard MIPS register names.
+ *
+ * Copyright (c) 1995 Cygnus Support
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/* Standard MIPS register names: */
+#define zero	$0
+#define z0	$0
+#define v0	$2
+#define v1	$3
+#define a0	$4
+#define a1	$5
+#define a2	$6
+#define a3	$7
+#define t0	$8
+#define t1	$9
+#define t2	$10
+#define t3	$11
+#define t4	$12
+#define t5	$13
+#define t6	$14
+#define t7	$15
+#define s0	$16
+#define s1	$17
+#define s2	$18
+#define s3	$19
+#define s4	$20
+#define s5	$21
+#define s6	$22
+#define s7	$23
+#define t8	$24
+#define t9	$25
+#define k0	$26	/* kernel private register 0 */
+#define k1	$27	/* kernel private register 1 */
+#define gp	$28	/* global data pointer */
+#define sp 	$29	/* stack-pointer */
+#define fp	$30	/* frame-pointer */
+#define ra	$31	/* return address */
+#define pc	$pc	/* pc, used on mips16 */
+
+#define fp0	$f0
+#define fp1	$f1
+
+/* Useful memory constants: */
+#define K0BASE		0x80000000
+#ifndef __mips64
+#define K1BASE		0xA0000000
+#else
+#define K1BASE		0xFFFFFFFFA0000000LL
+#endif
+
+#define PHYS_TO_K1(a)   ((unsigned)(a) | K1BASE)
+
+/* Standard Co-Processor 0 register numbers: */
+#define C0_COUNT	$9		/* Count Register */
+#define C0_SR		$12		/* Status Register */
+#define C0_CAUSE	$13		/* last exception description */
+#define C0_EPC		$14		/* Exception error address */
+#define C0_CONFIG	$16		/* CPU configuration */
+
+/* Standard Status Register bitmasks: */
+#define SR_CU1		0x20000000	/* Mark CP1 as usable */
+#define SR_FR		0x04000000	/* Enable MIPS III FP registers */
+#define SR_BEV		0x00400000	/* Controls location of exception vectors */
+#define SR_PE		0x00100000	/* Mark soft reset (clear parity error) */
+
+#define SR_KX		0x00000080	/* Kernel extended addressing enabled */
+#define SR_SX		0x00000040	/* Supervisor extended addressing enabled */
+#define SR_UX		0x00000020	/* User extended addressing enabled */
+
+/* Standard (R4000) cache operations. Taken from "MIPS R4000
+   Microprocessor User's Manual" 2nd edition: */
+
+#define CACHE_I		(0)	/* primary instruction */
+#define CACHE_D		(1)	/* primary data */
+#define CACHE_SI	(2)	/* secondary instruction */
+#define CACHE_SD	(3)	/* secondary data (or combined instruction/data) */
+
+#define INDEX_INVALIDATE		(0)	/* also encodes WRITEBACK if CACHE_D or CACHE_SD */
+#define INDEX_LOAD_TAG			(1)
+#define INDEX_STORE_TAG			(2)
+#define CREATE_DIRTY_EXCLUSIVE		(3)	/* CACHE_D and CACHE_SD only */
+#define HIT_INVALIDATE			(4)
+#define CACHE_FILL			(5)	/* CACHE_I only */
+#define HIT_WRITEBACK_INVALIDATE	(5)	/* CACHE_D and CACHE_SD only */
+#define HIT_WRITEBACK			(6)	/* CACHE_I, CACHE_D and CACHE_SD only */
+#define HIT_SET_VIRTUAL			(7)	/* CACHE_SI and CACHE_SD only */
+
+#define BUILD_CACHE_OP(o,c)		(((o) << 2) | (c))
+
+/* Individual cache operations: */
+#define INDEX_INVALIDATE_I		BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_I)
+#define INDEX_WRITEBACK_INVALIDATE_D	BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_D)
+#define INDEX_INVALIDATE_SI             BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_SI)
+#define INDEX_WRITEBACK_INVALIDATE_SD	BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_SD)
+
+#define INDEX_LOAD_TAG_I		BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_I)
+#define INDEX_LOAD_TAG_D                BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_D)
+#define INDEX_LOAD_TAG_SI               BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_SI)
+#define INDEX_LOAD_TAG_SD               BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_SD)
+
+#define INDEX_STORE_TAG_I              	BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_I)
+#define INDEX_STORE_TAG_D               BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_D)
+#define INDEX_STORE_TAG_SI              BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_SI)
+#define INDEX_STORE_TAG_SD              BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_SD)
+
+#define CREATE_DIRTY_EXCLUSIVE_D        BUILD_CACHE_OP(CREATE_DIRTY_EXCLUSIVE,CACHE_D)
+#define CREATE_DIRTY_EXCLUSIVE_SD       BUILD_CACHE_OP(CREATE_DIRTY_EXCLUSIVE,CACHE_SD)
+
+#define HIT_INVALIDATE_I                BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_I)
+#define HIT_INVALIDATE_D                BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_D)
+#define HIT_INVALIDATE_SI               BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_SI)
+#define HIT_INVALIDATE_SD               BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_SD)
+
+#define CACHE_FILL_I                    BUILD_CACHE_OP(CACHE_FILL,CACHE_I)
+#define HIT_WRITEBACK_INVALIDATE_D      BUILD_CACHE_OP(HIT_WRITEBACK_INVALIDATE,CACHE_D)
+#define HIT_WRITEBACK_INVALIDATE_SD     BUILD_CACHE_OP(HIT_WRITEBACK_INVALIDATE,CACHE_SD)
+
+#define HIT_WRITEBACK_I                 BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_I)
+#define HIT_WRITEBACK_D                 BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_D)
+#define HIT_WRITEBACK_SD                BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_SD)
+
+#define HIT_SET_VIRTUAL_SI		BUILD_CACHE_OP(HIT_SET_VIRTUAL,CACHE_SI)
+#define HIT_SET_VIRTUAL_SD              BUILD_CACHE_OP(HIT_SET_VIRTUAL,CACHE_SD)
+
+/*> EOF regs.S <*/

c/src/lib/libbsp/mips/hurricane/startup/exception.S

@@ -97,8 +97,8 @@ name:;                                          \
 
 EXTERN(_ISR_Nest_level, 4)
 EXTERN(_Thread_Dispatch_disable_level,4)
-EXTERN(_Context_Switch_necessary,4)
-EXTERN(_ISR_Signals_to_thread_executing,4)
+EXTERN(_Context_Switch_necessary,1)
+EXTERN(_ISR_Signals_to_thread_executing,1)
 .extern _Thread_Dispatch
 .extern _ISR_Vector_table
 
@@ -281,10 +281,10 @@ _ISR_Handler_cleanup:
    *  if ( !_Context_Switch_necessary && !_ISR_Signals_to_thread_executing )
    *    goto the label "exit interrupt (simple case)"
    */
-        lw	t0,_Context_Switch_necessary
-        lw	t1,_ISR_Signals_to_thread_executing
+        lb	t0,_Context_Switch_necessary
+        lb	t1,_ISR_Signals_to_thread_executing
 	NOP
-        or	t0,t0,t1
+        or 	t0,t0,t1
         beq	t0,zero,_ISR_Handler_exit
         NOP
 
@@ -416,6 +416,7 @@ USC_isr:
         sll     k0,(31-21)	/* test bit 21 (HBI) */
         
         bgez	k0,USC_isr2	/* branch if not a heartbeat interrupt */
+	NOP
 
 	/* clear the heartbeat interrupt */
 	la      k0,INT_STAT

c/src/lib/libbsp/mips/jmr3904/start/regs.h

@@ -0,0 +1,138 @@
+/*
+ * regs.S -- standard MIPS register names from
+ * newlib-1.8.2/libgloss/mips and adapted.
+ *
+ * Copyright (c) 1995 Cygnus Support
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/* Standard MIPS register names: */
+#define zero	$0
+#define z0	$0
+#define v0	$2
+#define v1	$3
+#define a0	$4
+#define a1	$5
+#define a2	$6
+#define a3	$7
+#define t0	$8
+#define t1	$9
+#define t2	$10
+#define t3	$11
+#define t4	$12
+#define t5	$13
+#define t6	$14
+#define t7	$15
+#define s0	$16
+#define s1	$17
+#define s2	$18
+#define s3	$19
+#define s4	$20
+#define s5	$21
+#define s6	$22
+#define s7	$23
+#define t8	$24
+#define t9	$25
+#define k0	$26	/* kernel private register 0 */
+#define k1	$27	/* kernel private register 1 */
+#define gp	$28	/* global data pointer */
+#define sp 	$29	/* stack-pointer */
+#define fp	$30	/* frame-pointer */
+#define ra	$31	/* return address */
+#define pc	$pc	/* pc, used on mips16 */
+
+#define fp0	$f0
+#define fp1	$f1
+
+/* Useful memory constants: */
+#define K0BASE		0x80000000
+#ifndef __mips64
+#define K1BASE		0xA0000000
+#else
+#define K1BASE		0xFFFFFFFFA0000000LL
+#endif
+
+#define PHYS_TO_K1(a)   ((unsigned)(a) | K1BASE)
+
+/* Standard Co-Processor 0 register numbers: */
+#define C0_COUNT	$9		/* Count Register */
+#define C0_SR		$12		/* Status Register */
+#define C0_CAUSE	$13		/* last exception description */
+#define C0_EPC		$14		/* Exception error address */
+#define C0_CONFIG	$16		/* CPU configuration */
+
+/* Standard Status Register bitmasks: */
+#define SR_CU1		0x20000000	/* Mark CP1 as usable */
+#define SR_FR		0x04000000	/* Enable MIPS III FP registers */
+#define SR_BEV		0x00400000	/* Controls location of exception vectors */
+#define SR_PE		0x00100000	/* Mark soft reset (clear parity error) */
+
+#define SR_KX		0x00000080	/* Kernel extended addressing enabled */
+#define SR_SX		0x00000040	/* Supervisor extended addressing enabled */
+#define SR_UX		0x00000020	/* User extended addressing enabled */
+
+/* Standard (R4000) cache operations. Taken from "MIPS R4000
+   Microprocessor User's Manual" 2nd edition: */
+
+#define CACHE_I		(0)	/* primary instruction */
+#define CACHE_D		(1)	/* primary data */
+#define CACHE_SI	(2)	/* secondary instruction */
+#define CACHE_SD	(3)	/* secondary data (or combined instruction/data) */
+
+#define INDEX_INVALIDATE		(0)	/* also encodes WRITEBACK if CACHE_D or CACHE_SD */
+#define INDEX_LOAD_TAG			(1)
+#define INDEX_STORE_TAG			(2)
+#define CREATE_DIRTY_EXCLUSIVE		(3)	/* CACHE_D and CACHE_SD only */
+#define HIT_INVALIDATE			(4)
+#define CACHE_FILL			(5)	/* CACHE_I only */
+#define HIT_WRITEBACK_INVALIDATE	(5)	/* CACHE_D and CACHE_SD only */
+#define HIT_WRITEBACK			(6)	/* CACHE_I, CACHE_D and CACHE_SD only */
+#define HIT_SET_VIRTUAL			(7)	/* CACHE_SI and CACHE_SD only */
+
+#define BUILD_CACHE_OP(o,c)		(((o) << 2) | (c))
+
+/* Individual cache operations: */
+#define INDEX_INVALIDATE_I		BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_I)
+#define INDEX_WRITEBACK_INVALIDATE_D	BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_D)
+#define INDEX_INVALIDATE_SI             BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_SI)
+#define INDEX_WRITEBACK_INVALIDATE_SD	BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_SD)
+
+#define INDEX_LOAD_TAG_I		BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_I)
+#define INDEX_LOAD_TAG_D                BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_D)
+#define INDEX_LOAD_TAG_SI               BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_SI)
+#define INDEX_LOAD_TAG_SD               BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_SD)
+
+#define INDEX_STORE_TAG_I              	BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_I)
+#define INDEX_STORE_TAG_D               BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_D)
+#define INDEX_STORE_TAG_SI              BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_SI)
+#define INDEX_STORE_TAG_SD              BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_SD)
+
+#define CREATE_DIRTY_EXCLUSIVE_D        BUILD_CACHE_OP(CREATE_DIRTY_EXCLUSIVE,CACHE_D)
+#define CREATE_DIRTY_EXCLUSIVE_SD       BUILD_CACHE_OP(CREATE_DIRTY_EXCLUSIVE,CACHE_SD)
+
+#define HIT_INVALIDATE_I                BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_I)
+#define HIT_INVALIDATE_D                BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_D)
+#define HIT_INVALIDATE_SI               BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_SI)
+#define HIT_INVALIDATE_SD               BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_SD)
+
+#define CACHE_FILL_I                    BUILD_CACHE_OP(CACHE_FILL,CACHE_I)
+#define HIT_WRITEBACK_INVALIDATE_D      BUILD_CACHE_OP(HIT_WRITEBACK_INVALIDATE,CACHE_D)
+#define HIT_WRITEBACK_INVALIDATE_SD     BUILD_CACHE_OP(HIT_WRITEBACK_INVALIDATE,CACHE_SD)
+
+#define HIT_WRITEBACK_I                 BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_I)
+#define HIT_WRITEBACK_D                 BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_D)
+#define HIT_WRITEBACK_SD                BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_SD)
+
+#define HIT_SET_VIRTUAL_SI		BUILD_CACHE_OP(HIT_SET_VIRTUAL,CACHE_SI)
+#define HIT_SET_VIRTUAL_SD              BUILD_CACHE_OP(HIT_SET_VIRTUAL,CACHE_SD)
+
+/*> EOF regs.S <*/

c/src/lib/libbsp/mips/rbtx4925/ChangeLog

@@ -1,3 +1,12 @@
+2009-03-12	Joel Sherrill <joel.sherrill@OARcorp.com>
+
+	PR 1385/cpukit
+	* startup/exception.S: When the type rtems_boolean was switched to the
+	C99 bool, the size changed from 4 bytes to 1 byte. The interrupt
+	dispatching code accesses two boolean variables for scheduling
+	purposes and the assembly implementations of this code did not get
+	updated.
+
 2008-12-08	Ralf Corsépius <ralf.corsepius@rtems.org>
 
 	* bsp_specs: Backport from CVS-HEAD.

c/src/lib/libbsp/mips/rbtx4925/liblnk/regs.h

@@ -0,0 +1,137 @@
+/*
+ * regs.S -- standard MIPS register names.
+ *
+ * Copyright (c) 1995 Cygnus Support
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/* Standard MIPS register names: */
+#define zero	$0
+#define z0	$0
+#define v0	$2
+#define v1	$3
+#define a0	$4
+#define a1	$5
+#define a2	$6
+#define a3	$7
+#define t0	$8
+#define t1	$9
+#define t2	$10
+#define t3	$11
+#define t4	$12
+#define t5	$13
+#define t6	$14
+#define t7	$15
+#define s0	$16
+#define s1	$17
+#define s2	$18
+#define s3	$19
+#define s4	$20
+#define s5	$21
+#define s6	$22
+#define s7	$23
+#define t8	$24
+#define t9	$25
+#define k0	$26	/* kernel private register 0 */
+#define k1	$27	/* kernel private register 1 */
+#define gp	$28	/* global data pointer */
+#define sp 	$29	/* stack-pointer */
+#define fp	$30	/* frame-pointer */
+#define ra	$31	/* return address */
+#define pc	$pc	/* pc, used on mips16 */
+
+#define fp0	$f0
+#define fp1	$f1
+
+/* Useful memory constants: */
+#define K0BASE		0x80000000
+#ifndef __mips64
+#define K1BASE		0xA0000000
+#else
+#define K1BASE		0xFFFFFFFFA0000000LL
+#endif
+
+#define PHYS_TO_K1(a)   ((unsigned)(a) | K1BASE)
+
+/* Standard Co-Processor 0 register numbers: */
+#define C0_COUNT	$9		/* Count Register */
+#define C0_SR		$12		/* Status Register */
+#define C0_CAUSE	$13		/* last exception description */
+#define C0_EPC		$14		/* Exception error address */
+#define C0_CONFIG	$16		/* CPU configuration */
+
+/* Standard Status Register bitmasks: */
+#define SR_CU1		0x20000000	/* Mark CP1 as usable */
+#define SR_FR		0x04000000	/* Enable MIPS III FP registers */
+#define SR_BEV		0x00400000	/* Controls location of exception vectors */
+#define SR_PE		0x00100000	/* Mark soft reset (clear parity error) */
+
+#define SR_KX		0x00000080	/* Kernel extended addressing enabled */
+#define SR_SX		0x00000040	/* Supervisor extended addressing enabled */
+#define SR_UX		0x00000020	/* User extended addressing enabled */
+
+/* Standard (R4000) cache operations. Taken from "MIPS R4000
+   Microprocessor User's Manual" 2nd edition: */
+
+#define CACHE_I		(0)	/* primary instruction */
+#define CACHE_D		(1)	/* primary data */
+#define CACHE_SI	(2)	/* secondary instruction */
+#define CACHE_SD	(3)	/* secondary data (or combined instruction/data) */
+
+#define INDEX_INVALIDATE		(0)	/* also encodes WRITEBACK if CACHE_D or CACHE_SD */
+#define INDEX_LOAD_TAG			(1)
+#define INDEX_STORE_TAG			(2)
+#define CREATE_DIRTY_EXCLUSIVE		(3)	/* CACHE_D and CACHE_SD only */
+#define HIT_INVALIDATE			(4)
+#define CACHE_FILL			(5)	/* CACHE_I only */
+#define HIT_WRITEBACK_INVALIDATE	(5)	/* CACHE_D and CACHE_SD only */
+#define HIT_WRITEBACK			(6)	/* CACHE_I, CACHE_D and CACHE_SD only */
+#define HIT_SET_VIRTUAL			(7)	/* CACHE_SI and CACHE_SD only */
+
+#define BUILD_CACHE_OP(o,c)		(((o) << 2) | (c))
+
+/* Individual cache operations: */
+#define INDEX_INVALIDATE_I		BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_I)
+#define INDEX_WRITEBACK_INVALIDATE_D	BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_D)
+#define INDEX_INVALIDATE_SI             BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_SI)
+#define INDEX_WRITEBACK_INVALIDATE_SD	BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_SD)
+
+#define INDEX_LOAD_TAG_I		BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_I)
+#define INDEX_LOAD_TAG_D                BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_D)
+#define INDEX_LOAD_TAG_SI               BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_SI)
+#define INDEX_LOAD_TAG_SD               BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_SD)
+
+#define INDEX_STORE_TAG_I              	BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_I)
+#define INDEX_STORE_TAG_D               BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_D)
+#define INDEX_STORE_TAG_SI              BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_SI)
+#define INDEX_STORE_TAG_SD              BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_SD)
+
+#define CREATE_DIRTY_EXCLUSIVE_D        BUILD_CACHE_OP(CREATE_DIRTY_EXCLUSIVE,CACHE_D)
+#define CREATE_DIRTY_EXCLUSIVE_SD       BUILD_CACHE_OP(CREATE_DIRTY_EXCLUSIVE,CACHE_SD)
+
+#define HIT_INVALIDATE_I                BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_I)
+#define HIT_INVALIDATE_D                BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_D)
+#define HIT_INVALIDATE_SI               BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_SI)
+#define HIT_INVALIDATE_SD               BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_SD)
+
+#define CACHE_FILL_I                    BUILD_CACHE_OP(CACHE_FILL,CACHE_I)
+#define HIT_WRITEBACK_INVALIDATE_D      BUILD_CACHE_OP(HIT_WRITEBACK_INVALIDATE,CACHE_D)
+#define HIT_WRITEBACK_INVALIDATE_SD     BUILD_CACHE_OP(HIT_WRITEBACK_INVALIDATE,CACHE_SD)
+
+#define HIT_WRITEBACK_I                 BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_I)
+#define HIT_WRITEBACK_D                 BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_D)
+#define HIT_WRITEBACK_SD                BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_SD)
+
+#define HIT_SET_VIRTUAL_SI		BUILD_CACHE_OP(HIT_SET_VIRTUAL,CACHE_SI)
+#define HIT_SET_VIRTUAL_SD              BUILD_CACHE_OP(HIT_SET_VIRTUAL,CACHE_SD)
+
+/*> EOF regs.S <*/

c/src/lib/libbsp/mips/rbtx4925/startup/exception.S

@@ -96,8 +96,8 @@ name:;                                          \
 
 EXTERN(_ISR_Nest_level, 4)
 EXTERN(_Thread_Dispatch_disable_level,4)
-EXTERN(_Context_Switch_necessary,4)
-EXTERN(_ISR_Signals_to_thread_executing,4)
+EXTERN(_Context_Switch_necessary,1)
+EXTERN(_ISR_Signals_to_thread_executing,1)
 .extern _Thread_Dispatch
 .extern _ISR_Vector_table
 
@@ -321,10 +321,10 @@ _ISR_Handler_cleanup:
    *  if ( !_Context_Switch_necessary && !_ISR_Signals_to_thread_executing )
    *    goto the label "exit interrupt (simple case)"
    */
-        lw	t0,_Context_Switch_necessary
-        lw	t1,_ISR_Signals_to_thread_executing
+        lb	t0,_Context_Switch_necessary
+        lb	t1,_ISR_Signals_to_thread_executing
 	NOP
-        or	t0,t0,t1
+        or 	t0,t0,t1
         beq	t0,zero,_ISR_Handler_exit
         NOP
 

c/src/lib/libbsp/mips/rbtx4938/ChangeLog

@@ -1,3 +1,12 @@
+2009-03-12	Joel Sherrill <joel.sherrill@OARcorp.com>
+
+	PR 1385/cpukit
+	* startup/exception.S: When the type rtems_boolean was switched to the
+	C99 bool, the size changed from 4 bytes to 1 byte. The interrupt
+	dispatching code accesses two boolean variables for scheduling
+	purposes and the assembly implementations of this code did not get
+	updated.
+
 2008-12-08	Ralf Corsépius <ralf.corsepius@rtems.org>
 
 	* bsp_specs: Backport from CVS-HEAD.

c/src/lib/libbsp/mips/rbtx4938/liblnk/regs.h

@@ -0,0 +1,137 @@
+/*
+ * regs.S -- standard MIPS register names.
+ *
+ * Copyright (c) 1995 Cygnus Support
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/* Standard MIPS register names: */
+#define zero	$0
+#define z0	$0
+#define v0	$2
+#define v1	$3
+#define a0	$4
+#define a1	$5
+#define a2	$6
+#define a3	$7
+#define t0	$8
+#define t1	$9
+#define t2	$10
+#define t3	$11
+#define t4	$12
+#define t5	$13
+#define t6	$14
+#define t7	$15
+#define s0	$16
+#define s1	$17
+#define s2	$18
+#define s3	$19
+#define s4	$20
+#define s5	$21
+#define s6	$22
+#define s7	$23
+#define t8	$24
+#define t9	$25
+#define k0	$26	/* kernel private register 0 */
+#define k1	$27	/* kernel private register 1 */
+#define gp	$28	/* global data pointer */
+#define sp 	$29	/* stack-pointer */
+#define fp	$30	/* frame-pointer */
+#define ra	$31	/* return address */
+#define pc	$pc	/* pc, used on mips16 */
+
+#define fp0	$f0
+#define fp1	$f1
+
+/* Useful memory constants: */
+#define K0BASE		0x80000000
+#ifndef __mips64
+#define K1BASE		0xA0000000
+#else
+#define K1BASE		0xFFFFFFFFA0000000LL
+#endif
+
+#define PHYS_TO_K1(a)   ((unsigned)(a) | K1BASE)
+
+/* Standard Co-Processor 0 register numbers: */
+#define C0_COUNT	$9		/* Count Register */
+#define C0_SR		$12		/* Status Register */
+#define C0_CAUSE	$13		/* last exception description */
+#define C0_EPC		$14		/* Exception error address */
+#define C0_CONFIG	$16		/* CPU configuration */
+
+/* Standard Status Register bitmasks: */
+#define SR_CU1		0x20000000	/* Mark CP1 as usable */
+#define SR_FR		0x04000000	/* Enable MIPS III FP registers */
+#define SR_BEV		0x00400000	/* Controls location of exception vectors */
+#define SR_PE		0x00100000	/* Mark soft reset (clear parity error) */
+
+#define SR_KX		0x00000080	/* Kernel extended addressing enabled */
+#define SR_SX		0x00000040	/* Supervisor extended addressing enabled */
+#define SR_UX		0x00000020	/* User extended addressing enabled */
+
+/* Standard (R4000) cache operations. Taken from "MIPS R4000
+   Microprocessor User's Manual" 2nd edition: */
+
+#define CACHE_I		(0)	/* primary instruction */
+#define CACHE_D		(1)	/* primary data */
+#define CACHE_SI	(2)	/* secondary instruction */
+#define CACHE_SD	(3)	/* secondary data (or combined instruction/data) */
+
+#define INDEX_INVALIDATE		(0)	/* also encodes WRITEBACK if CACHE_D or CACHE_SD */
+#define INDEX_LOAD_TAG			(1)
+#define INDEX_STORE_TAG			(2)
+#define CREATE_DIRTY_EXCLUSIVE		(3)	/* CACHE_D and CACHE_SD only */
+#define HIT_INVALIDATE			(4)
+#define CACHE_FILL			(5)	/* CACHE_I only */
+#define HIT_WRITEBACK_INVALIDATE	(5)	/* CACHE_D and CACHE_SD only */
+#define HIT_WRITEBACK			(6)	/* CACHE_I, CACHE_D and CACHE_SD only */
+#define HIT_SET_VIRTUAL			(7)	/* CACHE_SI and CACHE_SD only */
+
+#define BUILD_CACHE_OP(o,c)		(((o) << 2) | (c))
+
+/* Individual cache operations: */
+#define INDEX_INVALIDATE_I		BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_I)
+#define INDEX_WRITEBACK_INVALIDATE_D	BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_D)
+#define INDEX_INVALIDATE_SI             BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_SI)
+#define INDEX_WRITEBACK_INVALIDATE_SD	BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_SD)
+
+#define INDEX_LOAD_TAG_I		BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_I)
+#define INDEX_LOAD_TAG_D                BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_D)
+#define INDEX_LOAD_TAG_SI               BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_SI)
+#define INDEX_LOAD_TAG_SD               BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_SD)
+
+#define INDEX_STORE_TAG_I              	BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_I)
+#define INDEX_STORE_TAG_D               BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_D)
+#define INDEX_STORE_TAG_SI              BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_SI)
+#define INDEX_STORE_TAG_SD              BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_SD)
+
+#define CREATE_DIRTY_EXCLUSIVE_D        BUILD_CACHE_OP(CREATE_DIRTY_EXCLUSIVE,CACHE_D)
+#define CREATE_DIRTY_EXCLUSIVE_SD       BUILD_CACHE_OP(CREATE_DIRTY_EXCLUSIVE,CACHE_SD)
+
+#define HIT_INVALIDATE_I                BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_I)
+#define HIT_INVALIDATE_D                BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_D)
+#define HIT_INVALIDATE_SI               BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_SI)
+#define HIT_INVALIDATE_SD               BUILD_CACHE_OP(HIT_INVALIDATE,CACHE_SD)
+
+#define CACHE_FILL_I                    BUILD_CACHE_OP(CACHE_FILL,CACHE_I)
+#define HIT_WRITEBACK_INVALIDATE_D      BUILD_CACHE_OP(HIT_WRITEBACK_INVALIDATE,CACHE_D)
+#define HIT_WRITEBACK_INVALIDATE_SD     BUILD_CACHE_OP(HIT_WRITEBACK_INVALIDATE,CACHE_SD)
+
+#define HIT_WRITEBACK_I                 BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_I)
+#define HIT_WRITEBACK_D                 BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_D)
+#define HIT_WRITEBACK_SD                BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_SD)
+
+#define HIT_SET_VIRTUAL_SI		BUILD_CACHE_OP(HIT_SET_VIRTUAL,CACHE_SI)
+#define HIT_SET_VIRTUAL_SD              BUILD_CACHE_OP(HIT_SET_VIRTUAL,CACHE_SD)
+
+/*> EOF regs.S <*/

c/src/lib/libbsp/mips/rbtx4938/startup/exception.S

@@ -96,8 +96,8 @@ name:;                                          \
 
 EXTERN(_ISR_Nest_level, 4)
 EXTERN(_Thread_Dispatch_disable_level,4)
-EXTERN(_Context_Switch_necessary,4)
-EXTERN(_ISR_Signals_to_thread_executing,4)
+EXTERN(_Context_Switch_necessary,1)
+EXTERN(_ISR_Signals_to_thread_executing,1)
 .extern _Thread_Dispatch
 .extern _ISR_Vector_table
 
@@ -321,10 +321,10 @@ _ISR_Handler_cleanup:
    *  if ( !_Context_Switch_necessary && !_ISR_Signals_to_thread_executing )
    *    goto the label "exit interrupt (simple case)"
    */
-        lw	t0,_Context_Switch_necessary
-        lw	t1,_ISR_Signals_to_thread_executing
+        lb	t0,_Context_Switch_necessary
+        lb	t1,_ISR_Signals_to_thread_executing
 	NOP
-        or	t0,t0,t1
+        or 	t0,t0,t1
         beq	t0,zero,_ISR_Handler_exit
         NOP
 

c/src/lib/libbsp/powerpc/ChangeLog

@@ -1,3 +1,30 @@
+2010-02-01	Till Straumann <strauman@slac.stanford.edu>
+
+	PR 1492/bsps
+	* shared/startup/sbrk.c: When BSP_sbrk_policy had the value (-1)
+	(-> give all memory to the heap initially) then the computation
+	of the remaining heap size was wrong.
+
+2009-03-12	Joel Sherrill <joel.sherrill@OARcorp.com>
+
+	PR 1385/cpukit
+	* shared/irq/irq_asm.S: When the type rtems_boolean was switched to the
+	C99 bool, the size changed from 4 bytes to 1 byte. The interrupt
+	dispatching code accesses two boolean variables for scheduling
+	purposes and the assembly implementations of this code did not get
+	updated.
+
+2009-03-05	Sebastian Huber <sebastian.huber@embedded-brains.de>
+
+	* shared/clock/clock.c: Standard decrementer exception is now more
+	robust against erroneous external exception disable times.
+
+2009-02-11	Matt Rippa <mrippa@gemini.edu>
+
+	PR 1352/bsps
+	* shared/console/reboot.c, shared/motorola/motorola.c: Include support
+	for mvme2600/mvme2700.
+
 2008-11-03	Till Straumann <strauman@slac.stanford.edu>
 
 	PR 1332: call BSP_uart_termios_set()/BSP_uart_intr_ctrl()

c/src/lib/libbsp/powerpc/ep1a/ChangeLog

@@ -1,3 +1,16 @@
+2009-10-16	Jennifer Averett <jennifer@OARcorp.com>
+
+	* Makefile.am, configure.ac, preinstall.am, console/alloc360.c,
+	console/config.c, console/console.c, console/m68360.h,
+	console/mc68360_scc.c, console/rsPMCQ1.c, console/rsPMCQ1.h,
+	include/bsp.h, irq/irq_init.c, irq/openpic_xxx_irq.c, start/start.S,
+	startup/bspstart.c, startup/linkcmds, vme/VMEConfig.h: 
+        Updated and tested against RTEMS 4.9. Updated README file to latest
+        source status. Modified to use the shared irq source code. Turned off
+	debugging, cleaned up warnings, removed unused code. Tested with two
+	PMCQ1 serial cards. Tested MC68360 serial ports and VME using
+	external tests.
+	* README, irq/irq.h, vme/vmeconfig.c: New files.
 2008-12-08	Ralf Corsépius <ralf.corsepius@rtems.org>
 
 	* bsp_specs: Backport from CVS-HEAD.

c/src/lib/libbsp/powerpc/ep1a/Makefile.am

@@ -22,37 +22,38 @@ include_bspdir = $(includedir)/bsp
 dist_project_lib_DATA += startup/linkcmds
 
 startup_SOURCES = startup/bspstart.c ../../shared/bootcard.c \
-    ../../shared/bsppost.c ../../shared/bsppredriverhook.c \
-    ../../shared/bsplibc.c ../../powerpc/shared/startup/sbrk.c \
-    ../../shared/bspclean.c ../../shared/gnatinstallhandler.c \
-    ../../powerpc/shared/startup/pgtbl_setup.c \
-    ../../powerpc/shared/startup/pgtbl_activate.c \
-    ../../powerpc/shared/showbats.c
+    ../../shared/bspclean.c ../../shared/bsplibc.c \
+    ../../shared/sbrk.c \
+    ../../shared/gnatinstallhandler.c \
+    ../../powerpc/shared/showbats.c  \
+    ../../shared/bsppost.c ../../shared/bsppredriverhook.c 
+
 
 pclock_SOURCES = ../../powerpc/shared/clock/p_clock.c
-
-include_bsp_HEADERS = ../../powerpc/shared/console/uart.h \
-    ../../powerpc/shared/motorola/motorola.h \
-    ../../powerpc/shared/residual/residual.h \
-    ../../powerpc/shared/residual/pnp.h \
-    ../../powerpc/shared/console/consoleIo.h console/rsPMCQ1.h
 console_SOURCES = console/console.c console/ns16550cfg.c \
     console/mc68360_scc.c console/rsPMCQ1.c console/alloc360.c \
     console/init68360.c
 
-include_bsp_HEADERS += ../../powerpc/shared/openpic/openpic.h
-openpic_SOURCES = ../../powerpc/shared/openpic/openpic.h \
-    ../../powerpc/shared/openpic/openpic.c
+include_bsp_HEADERS = ../../powerpc/shared/pci/pci.h \
+    ../../powerpc/shared/motorola/motorola.h \
+     ../../powerpc/shared/residual/residual.h \
+    ../../powerpc/shared/residual/pnp.h \
+    ../../powerpc/shared/console/consoleIo.h console/rsPMCQ1.h
 
-include_bsp_HEADERS += ../../powerpc/shared/pci/pci.h
 pci_SOURCES = pci/no_host_bridge.c ../../powerpc/shared/pci/pci.c \
-    ../../powerpc/shared/pci/pcifinddevice.c
+        ../../powerpc/shared/pci/pcifinddevice.c
 
-include_bsp_HEADERS += ../../powerpc/shared/irq/irq.h \
+include_bsp_HEADERS += irq/irq.h \
 	../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/ppc_exc_bspsupp.h \
 	../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/vectors.h \
 	../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/irq_supp.h
-irq_SOURCES = irq/irq_init.c irq/openpic_xxx_irq.c ../../powerpc/shared/irq/i8259.c 
+
+irq_SOURCES =  irq/irq.h  irq/irq_init.c irq/openpic_xxx_irq.c \
+    ../../powerpc/shared/irq/i8259.c 
+    
+include_bsp_HEADERS += ../../powerpc/shared/openpic/openpic.h
+
+openpic_SOURCES = ../../powerpc/shared/openpic/openpic.c
 
 include_bsp_HEADERS += ../../shared/vmeUniverse/vmeUniverse.h \
     vme/VMEConfig.h \
@@ -64,7 +65,7 @@ include_bsp_HEADERS += ../../shared/vmeUniverse/vmeUniverse.h \
 
 vme_SOURCES = ../../shared/vmeUniverse/vmeUniverse.c \
     ../../shared/vmeUniverse/bspVmeDmaList.c \
-    ../shared/vme/vmeconfig.c \
+    vme/vmeconfig.c \
     ../shared/vme/vme_universe.c \
     ../../shared/vmeUniverse/vme_am_defs.h
 
@@ -78,9 +79,12 @@ rtems_crti.$(OBJEXT): ../../powerpc/shared/start/rtems_crti.S
 	$(CPPASCOMPILE) -o $@ -c $<
 project_lib_DATA += rtems_crti.$(OBJEXT)
 
+EXTRA_DIST += README
+
 noinst_LIBRARIES = libbsp.a
-libbsp_a_SOURCES = $(startup_SOURCES) $(pclock_SOURCES) $(console_SOURCES) \
-    $(openpic_SOURCES) $(pci_SOURCES) $(irq_SOURCES) $(vme_SOURCES)
+libbsp_a_SOURCES =  $(pclock_SOURCES) $(console_SOURCES) $(irq_SOURCES) \
+    $(pci_SOURCES) $(vectors_SOURCES) $(startup_SOURCES) \
+    $(openpic_SOURCES) $(vme_SOURCES) 
 
 libbsp_a_LIBADD = \
     ../../../libcpu/@RTEMS_CPU@/shared/cpuIdent.rel \

c/src/lib/libbsp/powerpc/ep1a/README

@@ -0,0 +1,46 @@
+#
+#  $Id$
+#
+
+BSP NAME:           ep1a
+BOARD:              RADSTONE EP1A
+BUS:                N/A
+CPU FAMILY:         ppc
+CPU:                PowerPC 8245
+COPROCESSORS:       N/A
+MODE:               32 bit mode
+
+DEBUG MONITOR:      see note.
+
+PERIPHERALS
+===========
+TIMERS:             PPC internal Timebase register
+  RESOLUTION:         
+SERIAL PORTS:       1 onboard QUIC, optional 2 mezannes with QUIC chips
+REAL-TIME CLOCK:    xxx
+DMA:                none
+VIDEO:              none
+SCSI:               none
+NETWORKING:         none
+
+DRIVER INFORMATION
+==================
+CLOCK DRIVER:       PPC internal
+IOSUPP DRIVER:      N/A
+SHMSUPP:            N/A
+TIMER DRIVER:       PPC internal
+TTY DRIVER:         PPC internal
+
+STDIO
+=====
+PORT:               Console port 0
+ELECTRICAL:         na
+BAUD:               9600
+BITS PER CHARACTER: 8
+PARITY:             n
+STOP BITS:          1
+
+Notes
+=====
+This bsp has been tested with an custom ep1a, which had two 
+PMCQ1 Daughter cards attached.

c/src/lib/libbsp/powerpc/ep1a/configure.ac

@@ -15,6 +15,21 @@ RTEMS_PROG_CC_FOR_TARGET([-ansi -fasm])
 RTEMS_CANONICALIZE_TOOLS
 RTEMS_PROG_CCAS
 
+RTEMS_BSPOPTS_SET([CONSOLE_USE_INTERRUPTS],[*],[1])
+RTEMS_BSPOPTS_HELP([CONSOLE_USE_INTERRUPTS],
+[whether using console interrupts])
+
+RTEMS_BSPOPTS_SET([INITIALIZE_COM_PORTS],[*],[0])
+RTEMS_BSPOPTS_HELP([INITIALIZE_COM_PORTS],
+[FIXME: Missing explanation])
+
+RTEMS_BSPOPTS_SET([PPC_USE_SPRG],[*],[0])
+RTEMS_BSPOPTS_HELP([PPC_USE_SPRG],
+[If defined, then the PowerPC specific code in RTEMS will use some
+of the special purpose registers to slightly optimize interrupt
+response time.  The use of these registers can conflict with
+other tools like debuggers.])
+
 RTEMS_BSPOPTS_SET([PPC_USE_DATA_CACHE],[*],[0])
 RTEMS_BSPOPTS_HELP([PPC_USE_DATA_CACHE],
 [If defined, then the PowerPC specific code in RTEMS will use
@@ -24,14 +39,10 @@ RTEMS_BSPOPTS_HELP([PPC_USE_DATA_CACHE],
  of PowerPC 603e revisions and emulator versions.
  The BSP actually contains the call that enables this.])
 
-RTEMS_BSPOPTS_SET([INSTRUCTION_CACHE_ENABLE],[*],[0])
-RTEMS_BSPOPTS_HELP([INSTRUCTION_CACHE_ENABLE],
-[If defined, the instruction cache will be enabled after address translation
- is turned on.])
-
-RTEMS_BSPOPTS_SET([CONSOLE_USE_INTERRUPTS],[*],[0])
-RTEMS_BSPOPTS_HELP([CONSOLE_USE_INTERRUPTS],
-[whether using console interrupts])
+RTEMS_BSPOPTS_SET([PPC_VECTOR_FILE_BASE],[*],[0x0100])
+RTEMS_BSPOPTS_HELP([PPC_VECTOR_FILE_BASE],
+[This defines the base address of the exception table.
+ NOTE: Vectors are actually at 0xFFF00000 but file starts at offset.])
 
 RTEMS_CHECK_NETWORKING
 AM_CONDITIONAL(HAS_NETWORKING,test "$HAS_NETWORKING" = "yes")

c/src/lib/libbsp/powerpc/ep1a/console/alloc360.c

@@ -34,23 +34,40 @@ void M360SetupMemory( M68360_t ptr ){
 
 #if DEBUG_PRINT
 printk("m360->mcr:0x%08x  Q1_360_SIM_MCR:0x%08x\n", 
-       (unsigned int)&(m360->mcr), ((unsigned int)m360+Q1_360_SIM_MCR));
+       (uint32_t)&(m360->mcr), ((uint32_t)m360+Q1_360_SIM_MCR));
 #endif
-  ptr->bdregions[0].base = (char *)&m360->dpram1[0];
+  ptr->bdregions[0].base = (uint8_t *)&m360->dpram1[0];
   ptr->bdregions[0].size = sizeof m360->dpram1;
   ptr->bdregions[0].used = 0;
+#if DEBUG_PRINT
+printk("%d) base 0x%x size %d used %d\n", 0,
+       (uint32_t)ptr->bdregions[0].base, ptr->bdregions[0].size, ptr->bdregions[0].used );
+#endif
 
-  ptr->bdregions[1].base = (char *)&m360->dpram3[0];
+  ptr->bdregions[1].base = (uint8_t *)&m360->dpram3[0];
   ptr->bdregions[1].size = sizeof m360->dpram3;
   ptr->bdregions[1].used = 0;
+#if DEBUG_PRINT
+printk("%d) base 0x%x size %d used %d\n", 1,
+       (uint32_t)ptr->bdregions[1].base, ptr->bdregions[1].size, ptr->bdregions[1].used );
+#endif
 
-  ptr->bdregions[2].base = (char *)&m360->dpram0[0];
+  ptr->bdregions[2].base = (uint8_t *)&m360->dpram0[0];
   ptr->bdregions[2].size = sizeof m360->dpram0;
   ptr->bdregions[2].used = 0;
+#if DEBUG_PRINT
+printk("%d) base 0x%x size %d used %d\n", 2,
+       (uint32_t)ptr->bdregions[2].base, ptr->bdregions[2].size, ptr->bdregions[2].used );
+#endif
 
-  ptr->bdregions[3].base = (char *)&m360->dpram2[0];
+  ptr->bdregions[3].base = (uint8_t *)&m360->dpram2[0];
   ptr->bdregions[3].size = sizeof m360->dpram2;
   ptr->bdregions[3].used = 0;
+#if DEBUG_PRINT
+printk("%d) base 0x%x size %d used %d\n", 3,
+       (uint32_t)ptr->bdregions[3].base, ptr->bdregions[3].size, ptr->bdregions[3].used );
+#endif
+
 }
 
 
@@ -60,11 +77,11 @@ printk("m360->mcr:0x%08x  Q1_360_SIM_MCR:0x%08x\n",
 void *
 M360AllocateBufferDescriptors (M68360_t ptr, int count)
 {
-  unsigned int i;
+  uint32_t     i;
   ISR_Level    level;
   void         *bdp  = NULL;
-  unsigned int want  = count * sizeof(m360BufferDescriptor_t);
-  int          have;
+  uint32_t      want  = count * sizeof(m360BufferDescriptor_t);
+  uint32_t      have;
 
   /*
    * Running with interrupts disabled is usually considered bad
@@ -81,15 +98,27 @@ M360AllocateBufferDescriptors (M68360_t ptr, int count)
      * less dual-port RAM.
      */
     if (ptr->bdregions[i].used == 0) {
-      volatile unsigned char *cp = ptr->bdregions[i].base;
+      volatile uint8_t *cp = ptr->bdregions[i].base;
+      uint8_t data;
+
       *cp = 0xAA;
-      if (*cp != 0xAA) {
+      data = *cp;
+      if (data != 0xAA) {
         ptr->bdregions[i].used = ptr->bdregions[i].size;
+#if DEBUG_PRINT
+printk("%d) base 0x%x used %d expected 0xAA read 0x%x\n",i, 
+       (uint32_t)ptr->bdregions[i].base, ptr->bdregions[0].used, data );
+#endif
         continue;
       }
       *cp = 0x55;
-      if (*cp != 0x55) {
+      data = *cp;
+      if (data != 0x55) {
         ptr->bdregions[i].used = ptr->bdregions[i].size;
+#if DEBUG_PRINT
+printk("%d) base 0x%x used %d expected 0x55 read 0x%x\n",i, 
+       (uint32_t)ptr->bdregions[i].base, ptr->bdregions[0].used, data );
+#endif
         continue;
       }
       *cp = 0x0;

c/src/lib/libbsp/powerpc/ep1a/console/config.c

@@ -1,7 +1,7 @@
 /*
  *  This file contains the TTY driver table for the EP1A
  * 
- *  COPYRIGHT (c) 1989-1999.
+ *  COPYRIGHT (c) 1989-2009.
  *  On-Line Applications Research Corporation (OAR).
  *
  *  The license and distribution terms for this file may be
@@ -21,7 +21,12 @@
  *  or interrupt driven IO.
  */
 
+#if 1 
 #define NS16550_FUNCTIONS &ns16550_fns_polled
+#else
+#define NS16550_FUNCTIONS &ns16550_fns
+#endif
+
 #define MC68360_SCC_FUNCTIONS &mc68360_scc_fns
 
 /*
@@ -122,6 +127,7 @@ console_tbl	Console_Port_Tbl[] = {
                 7372800,                        /* ulClock */
                 0                               /* ulIntVector */
         },
+
         /*
          * Up to 12 serial ports are provided by MC68360 SCC ports.
          *     EP1A may have one MC68360 providing 4 ports (A,B,C,D).
@@ -431,3 +437,8 @@ static bool config_68360_scc_base_probe_12( int minor ) {
   return config_68360_scc_base_probe( minor, 0, 15, 4);
 }
 
+
+void Force_mc8360_interrupt( int d ) {
+  mc68360_sccInterruptHandler( M68360_chips->next );
+}
+

c/src/lib/libbsp/powerpc/ep1a/console/console.c

@@ -1,4 +1,4 @@
-/*XXX
+/*
  *  This file contains the TTY driver for the ep1a 
  *
  *  This driver uses the termios pseudo driver.
@@ -212,6 +212,11 @@ rtems_device_driver console_initialize(
     Console_Port_Tbl[minor].pDeviceFns->deviceInitialize(
       Console_Port_Minor);
 
+  /*
+   * NOTE:  We must probe ALL possible devices, which initializes
+   *        the address information in the config.c tables.
+   */
+
   for(minor++;minor<Console_Port_Count;minor++)
   {
     /*
@@ -241,83 +246,6 @@ rtems_device_driver console_initialize(
 
   return RTEMS_SUCCESSFUL;
 }
-#if 0
-/* PAGE
- *
- *  DEBUG_puts
- *
- *  This should be safe in the event of an error.  It attempts to ensure
- *  that no TX empty interrupts occur while it is doing polled IO.  Then
- *  it restores the state of that external interrupt.
- *
- *  Input parameters:
- *    string  - pointer to debug output string
- *
- *  Output parameters:  NONE
- *
- *  Return values:      NONE
- */
-
-void DEBUG_puts(
-	char *string
-)
-{
-	char *s;
-	unsigned32	Irql;
-
-	rtems_interrupt_disable(Irql);
-
-	for ( s = string ; *s ; s++ ) 
-	{
-		Console_Port_Tbl[Console_Port_Minor].pDeviceFns->
-			deviceWritePolled(Console_Port_Minor, *s);
-	}
-
-	rtems_interrupt_enable(Irql);
-}
-
-/* PAGE
- *
- *  DEBUG_puth
- *
- *  This should be safe in the event of an error.  It attempts to ensure
- *  that no TX empty interrupts occur while it is doing polled IO.  Then
- *  it restores the state of that external interrupt.
- *
- *  Input parameters:
- *    ulHexNum - value to display
- *
- *  Output parameters:  NONE
- *
- *  Return values:      NONE
- */
-void
-DEBUG_puth(
-    unsigned32 ulHexNum
-    )
-{
-	unsigned long i,d;
-	unsigned32 Irql;
-
-	rtems_interrupt_disable(Irql);
-	
-	Console_Port_Tbl[Console_Port_Minor].pDeviceFns->
-		deviceWritePolled(Console_Port_Minor, '0');
-	Console_Port_Tbl[Console_Port_Minor].pDeviceFns->
-		deviceWritePolled(Console_Port_Minor, 'x');
-
-	for(i=32;i;)
-	{
-		i-=4;
-		d=(ulHexNum>>i)&0xf;
-		Console_Port_Tbl[Console_Port_Minor].pDeviceFns->
-			deviceWritePolled(Console_Port_Minor,
-					  (d<=9) ? d+'0' : d+'a'-0xa);
-	}
-
-	rtems_interrupt_enable(Irql);
-}
-#endif
 
 /* const char arg to be compatible with BSP_output_char decl. */
 void

c/src/lib/libbsp/powerpc/ep1a/console/m68360.h

@@ -16,7 +16,7 @@
  *      eric@skatter.usask.ca                      
  *                                            
  *
- *  COPYRIGHT (c) 1989-1999.
+ *  COPYRIGHT (c) 1989-2009.
  *  On-Line Applications Research Corporation (OAR).
  *
  *  The license and distribution terms for this file may be
@@ -935,9 +935,9 @@ typedef struct m360_ {
 } m360_t;
 
 struct bdregions_t {
-  char            *base;
-  unsigned int    size;
-  unsigned int    used;
+  uint8_t     *base;
+  uint32_t    size;
+  uint32_t    used;
 };
 
 #define M68360_RX_BUF_SIZE        1
@@ -977,6 +977,8 @@ void *M360AllocateBufferDescriptors (M68360_t ptr, int count);
 void M360ExecuteRISC( volatile m360_t *m360, uint16_t command);
 int mc68360_scc_create_chip( PPMCQ1BoardData BoardData, uint8_t int_vector );
 
+void mc68360_sccInterruptHandler( void *ptr);
+
 #if 0
 extern volatile m360_t *m360;
 #endif

c/src/lib/libbsp/powerpc/ep1a/console/mc68360_scc.c

@@ -1,7 +1,7 @@
 /*  This file contains the termios TTY driver for the
  *  Motorola MC68360 SCC ports.
  *
- *  COPYRIGHT (c) 1989-2008.
+ *  COPYRIGHT (c) 1989-2009.
  *  On-Line Applications Research Corporation (OAR).
  *
  *  The license and distribution terms for this file may be
@@ -25,7 +25,7 @@
 #include <rtems/bspIo.h>
 #include <string.h>
 
-#if 0
+#if 0 
 #define DEBUG_360
 #endif
 
@@ -77,10 +77,10 @@ void scc_write8(
   uint8_t           value
 )
 {
+  *address = value;
 #ifdef DEBUG_360
   printk( "WR8 %s 0x%08x 0x%02x\n", name, address, value );
 #endif
-  *address = value;
 }
 
 
@@ -108,10 +108,10 @@ void scc_write16(
   uint16_t           value
 )
 {
+  *address = value;
 #ifdef DEBUG_360
   printk( "WR16 %s 0x%08x 0x%04x\n", name, address, value );
 #endif
-  *address = value;
 }
 
 
@@ -139,10 +139,11 @@ void scc_write32(
   uint32_t           value
 )
 {
+  *address = value;
+  Processor_Synchronize();
 #ifdef DEBUG_360
   printk( "WR32 %s 0x%08x 0x%08x\n", name, address, value );
 #endif
-  *address = value;
 }
 
 void mc68360_sccShow_Regs(int minor){
@@ -155,9 +156,9 @@ void mc68360_sccShow_Regs(int minor){
 }
 
 #define TX_BUFFER_ADDRESS( _ptr ) \
-  ((char *)ptr->txBuf - (char *)ptr->chip->board_data->baseaddr)
+  ((uint8_t *)ptr->txBuf - (uint8_t *)ptr->chip->board_data->baseaddr)
 #define RX_BUFFER_ADDRESS( _ptr ) \
-  ((char *)ptr->rxBuf - (char *)ptr->chip->board_data->baseaddr)
+  ((uint8_t *)ptr->rxBuf - (uint8_t *)ptr->chip->board_data->baseaddr)
 
 
 /**************************************************************************
@@ -239,8 +240,9 @@ mc68360_sccBRGC(int baud, int m360_clock_rate)
  *    none                                                                *
  *                                                                        *
  **************************************************************************/
-void mc68360_sccInterruptHandler( M68360_t chip )
+void mc68360_sccInterruptHandler( void *ptr)
 {
+  M68360_t           chip   = ptr;
   volatile m360_t    *m360;
   int                port;
   uint16_t           status;
@@ -250,8 +252,8 @@ void mc68360_sccInterruptHandler( M68360_t chip )
   int                clear_isr;
 
 
-#ifdef DEBUG_360
-  printk("mc68360_sccInterruptHandler\n");
+#ifdef DEBUG_360 
+  printk("mc68360_sccInterruptHandler with 0x%x \n", ptr);
 #endif
   for (port=0; port<4; port++) {
 
@@ -275,8 +277,8 @@ void mc68360_sccInterruptHandler( M68360_t chip )
         while ((status & M360_BD_EMPTY) == 0)
         {
            length= scc_read16("sccRxBd->length",&chip->port[port].sccRxBd->length);
-if (length > 1)
-  EP1A_READ_LENGTH_GREATER_THAN_1 = length;
+           if (length > 1)
+             EP1A_READ_LENGTH_GREATER_THAN_1 = length;
 
            for (i=0;i<length;i++) {
              data= chip->port[port].rxBuf[i];
@@ -302,21 +304,19 @@ if (length > 1)
         if ((status & M360_BD_EMPTY) == 0)
         {
            scc_write16("sccTxBd->status",&chip->port[port].sccTxBd->status,0);
-#if 1
            rtems_termios_dequeue_characters(
              Console_Port_Data[chip->port[port].minor].termios_data, 
-             chip->port[port].sccTxBd->length);
-#else
-           mc68360_scc_write_support_int(chip->port[port].minor,"*****", 5); 
-#endif
+             chip->port[port].sccTxBd->length
+           );
         }
       }
 
       /*
        * Clear SCC interrupt-in-service bit.
        */
-      if ( clear_isr )
+      if ( clear_isr ) {
         scc_write32( "cisr", &m360->cisr, (0x80000000 >> chip->port[port].channel) );
+      }
   }
 }
 
@@ -339,10 +339,9 @@ int mc68360_scc_open(
   uint32_t               data;
 
 #ifdef DEBUG_360
-  printk("mc68360_scc_open %d\n", minor);
+  printk("mc68360_scc_open %s (%d)\n", Console_Port_Tbl[minor].sDeviceName, minor);
 #endif
 
-
   ptr   = Console_Port_Tbl[minor].pDeviceParams;
   m360  = ptr->chip->m360;
 
@@ -368,8 +367,8 @@ int mc68360_scc_open(
 
 uint32_t mc68360_scc_calculate_pbdat( M68360_t chip )
 {
-  uint32_t               i;
-  uint32_t               pbdat_data;
+  int                    i;
+  uint32_t               pbdat_data = 0x03;
   int                    minor;
   uint32_t               type422data[4] = {
     0x00440,  0x00880,  0x10100,  0x20200
@@ -378,13 +377,15 @@ uint32_t mc68360_scc_calculate_pbdat( M68360_t chip )
   pbdat_data = 0x3;
   for (i=0; i<4; i++) {
     minor = chip->port[i].minor;
-    if mc68360_scc_Is_422( minor ) 
+    if mc68360_scc_Is_422( minor ){
       pbdat_data |= type422data[i];
+    }
   }
 
   return pbdat_data;
 }
 
+
 /*
  *  mc68360_scc_initialize_interrupts
  *
@@ -400,7 +401,7 @@ void mc68360_scc_initialize_interrupts(int minor)
   uint32_t               buffers_start;
   uint32_t               tmp_u32;
 
-#ifdef DEBUG_360
+#ifdef DEBUG_360 
   printk("mc68360_scc_initialize_interrupts: minor %d\n", minor );
   printk("Console_Port_Tbl[minor].pDeviceParams 0x%08x\n",
     Console_Port_Tbl[minor].pDeviceParams );
@@ -409,7 +410,7 @@ void mc68360_scc_initialize_interrupts(int minor)
   ptr   = Console_Port_Tbl[minor].pDeviceParams;
   m360  = ptr->chip->m360;
   
-#ifdef DEBUG_360
+#ifdef DEBUG_360 
   printk("m360 0x%08x baseaddr 0x%08x\n",
      m360, ptr->chip->board_data->baseaddr);
 #endif
@@ -464,6 +465,7 @@ void mc68360_scc_initialize_interrupts(int minor)
   /*
    * XXX
    */
+
   scc_write16( "papar", &m360->papar, 0xffff );
   scc_write16( "padir", &m360->padir, 0x5500 ); /* From Memo    */
   scc_write16( "paodr", &m360->paodr, 0x0000 );
@@ -664,6 +666,11 @@ int mc68360_scc_write_support_int(
   rtems_interrupt_level  Irql;
   M68360_serial_ports_t  ptr;
 
+#ifdef DEBUG_360
+  printk("mc68360_scc_write_support_int: char 0x%x length %d\n",
+       (unsigned int)*buf, len );
+#endif
+
 #if 1
   mc68360_length_array[ mc68360_length_count ] = len;
   mc68360_length_count++;
@@ -681,18 +688,13 @@ int mc68360_scc_write_support_int(
   if ( !len )
     return 0;
 
-  /*
-   *
-   */
-#ifdef DEBUG_360
-  printk("mc68360_scc_write_support_int: char 0x%x length %d\n",
-       (unsigned int)*buf, len );
-#endif
   /*
    *  We must copy the data from the global memory space to MC68360 space
    */
-
   rtems_interrupt_disable(Irql);
+#ifdef DEBUG_360
+  printk("mc68360_scc_write_support_int: disable irq 0x%x\n", Irql );
+#endif
 
   scc_write16( "sccTxBd->status", &ptr->sccTxBd->status, 0 );
   memcpy((void *) ptr->txBuf, buf, len);
@@ -702,6 +704,9 @@ int mc68360_scc_write_support_int(
   scc_write16( "sccTxBd->status", &ptr->sccTxBd->status, 
                (M360_BD_READY | M360_BD_WRAP | M360_BD_INTERRUPT) );
 
+#ifdef DEBUG_360
+  printk("mc68360_scc_write_support_int: enable irq 0x%x\n", Irql );
+#endif
   rtems_interrupt_enable(Irql);
 
   return len;
@@ -897,12 +902,14 @@ int mc68360_scc_create_chip( PPMCQ1BoardData BoardData, uint8_t int_vector )
    * XXX - Note Does this need to be moved up to if a QUICC is fitted
    *       section?
    */
-  if ((chip = malloc(sizeof(struct _m68360_per_chip))) == NULL)
+
+  if ((chip = calloc( 1, sizeof(struct _m68360_per_chip))) == NULL)
   {
     printk("Error Unable to allocate memory for _m68360_per_chip\n");
     return RTEMS_IO_ERROR;
+  } else {
+    printk("Allocate memory for _m68360_per_chip at 0x%x\n", chip );
   }
-
   chip->next                    = M68360_chips;
   chip->m360                    = (void *)BoardData->baseaddr;
   chip->m360_interrupt          = int_vector;
@@ -945,7 +952,6 @@ int mc68360_scc_create_chip( PPMCQ1BoardData BoardData, uint8_t int_vector )
     /*
      * Allocate buffer descriptors.
      */
-
     chip->port[i-1].sccRxBd = M360AllocateBufferDescriptors(chip, 1);
     chip->port[i-1].sccTxBd = M360AllocateBufferDescriptors(chip, 1);
   }
@@ -957,7 +963,6 @@ int mc68360_scc_create_chip( PPMCQ1BoardData BoardData, uint8_t int_vector )
     &mc68360_sccInterruptHandler,
     chip 
   );
-
   return RTEMS_SUCCESSFUL;
 }
 

c/src/lib/libbsp/powerpc/ep1a/console/rsPMCQ1.c

@@ -27,7 +27,7 @@ These functions are responsible for scanning for PMCQ1's and setting up
 the Motorola MC68360's if present.
 
 USAGE
-call rsPMCQ1Init() to perform ba  sic initialisation of the PMCQ1's.
+call rsPMCQ1Init() to perform basic initialisation of the PMCQ1's.
 */
 
 /* includes */
@@ -41,8 +41,8 @@ call rsPMCQ1Init() to perform ba  sic initialisation of the PMCQ1's.
 #include "m68360.h"
 
 /* defines */
-#if 1
-#define DEBUG_360
+#if 0 
+#define DEBUG_360     TRUE
 #endif
 
 /* Local data */
@@ -82,27 +82,61 @@ static unsigned char rsPMCQ1eeprom[] =
 
 void MsDelay(void)
 {
-  printk(".");
+  printk("..");
 }
 
 void write8( int addr, int data ){
-  out_8((void *)addr, (unsigned char)data);
+  out_8((volatile void *)addr, (unsigned char)data);
+  Processor_Synchronize();
 }
 
 void write16( int addr, int data ) {
-  out_be16((void *)addr, (short)data );
+  out_be16((volatile void *)addr, (short)data );
+  Processor_Synchronize();
 }
 
 void write32( int addr, int data ) {
-  out_be32((unsigned int *)addr, data );
+  out_be32((volatile unsigned int *)addr, data );
+  Processor_Synchronize();
 }
 
 int read32( int addr){
-  return in_be32((unsigned int *)addr);
+  int value = in_be32((volatile unsigned int *)addr);
+  Processor_Synchronize();
+  return value;
+}
+
+void rsPMCQ1_scc_On(const struct __rtems_irq_connect_data__ *ptr) 
+{
+
+}
+
+void rsPMCQ1_scc_Off(const struct __rtems_irq_connect_data__ *ptr) 
+{
+
+}
+
+int rsPMCQ1_scc_except_always_enabled(const struct __rtems_irq_connect_data__ *ptr)
+{
+  return TRUE;
 }
 
 
-void rsPMCQ1_scc_nullFunc(void) {}
+void rsPMCQ1ShowIntrStatus(void )
+{
+  unsigned long   status;
+  unsigned long   mask;
+  PPMCQ1BoardData boardData;
+
+  for (boardData = pmcq1BoardData; boardData; boardData = boardData->pNext)
+  {
+
+    status = PMCQ1_Read_EPLD(boardData->baseaddr, PMCQ1_INT_STATUS );
+    mask   = PMCQ1_Read_EPLD(boardData->baseaddr, PMCQ1_INT_MASK );
+    printk("rsPMCQ1ShowIntrStatus: interrupt status 0x%x) 0x%x with mask: 0x%x\n", boardData->quiccInt, status, mask);
+  }
+}
+
   
 /*******************************************************************************
 * rsPMCQ1Int - handle a PMCQ1 interrupt
@@ -116,48 +150,57 @@ void rsPMCQ1_scc_nullFunc(void) {}
 void rsPMCQ1Int( void *ptr )
 {
   unsigned long   status;
-  unsigned long   status1;
+  static unsigned long   status1;
   unsigned long   mask;
   uint32_t        data;
   PPMCQ1BoardData boardData = ptr;
+  volatile unsigned long *hrdwr;
+  unsigned long           value;
 
   status = PMCQ1_Read_EPLD(boardData->baseaddr, PMCQ1_INT_STATUS );
   mask   = PMCQ1_Read_EPLD(boardData->baseaddr, PMCQ1_INT_MASK );
 
-  if (((mask & PMCQ1_INT_MASK_QUICC) == 0) && (status & PMCQ1_INT_STATUS_QUICC))
+
+  if (((mask & PMCQ1_INT_MASK_QUICC) == 0) && ((status & PMCQ1_INT_STATUS_QUICC) != 0 ))
   {
     /* If there is a handler call it otherwise mask the interrupt */
     if (boardData->quiccInt) {
       boardData->quiccInt(boardData->quiccArg);
     } else {
-      *(volatile unsigned long *)(boardData->baseaddr + PMCQ1_INT_MASK) |= PMCQ1_INT_MASK_QUICC;
+      printk("No handler - Masking interrupt\n");
+      hrdwr = (volatile unsigned long *)(boardData->baseaddr + PMCQ1_INT_MASK);
+      value = (*hrdwr) | PMCQ1_INT_MASK_QUICC;
+      *hrdwr = value;
     }
   }
 
   if (((mask & PMCQ1_INT_MASK_MA) == 0) && (status & PMCQ1_INT_STATUS_MA))
   {
+
     /* If there is a handler call it otherwise mask the interrupt */
     if (boardData->maInt) {
       boardData->maInt(boardData->maArg);
-
       data = PMCQ1_Read_EPLD(boardData->baseaddr, PMCQ1_INT_STATUS );
-      data &= (~PMCQ1_INT_STATUS_MA);
+      data = data & (~PMCQ1_INT_STATUS_MA);
       PMCQ1_Write_EPLD(boardData->baseaddr, PMCQ1_INT_STATUS, data );
-
-    } else {
-     *(volatile unsigned long *)(boardData->baseaddr + PMCQ1_INT_MASK) |= PMCQ1_INT_MASK_MA;
+    } else { 
+      printk("No handler - Masking interrupt\n");
+      hrdwr = (volatile unsigned long *)(boardData->baseaddr + PMCQ1_INT_MASK);
+      value = (*hrdwr) | PMCQ1_INT_MASK_MA;
+      *hrdwr = value;
     }
   }
 
   RTEMS_COMPILER_MEMORY_BARRIER();
 
   /* Clear Interrupt on QSPAN */
-  *(volatile unsigned long *)(boardData->bridgeaddr + 0x600) = 0x00001000;
+  hrdwr = (volatile unsigned long *)(boardData->bridgeaddr + 0x600);
+  *hrdwr = 0x00001000;
 
   /* read back the status register to ensure that the pci write has completed */
-  status1 = *(volatile unsigned long *)(boardData->bridgeaddr + 0x600);
-  RTEMS_COMPILER_MEMORY_BARRIER();
+  status1 = *hrdwr;
 
+  RTEMS_COMPILER_MEMORY_BARRIER();
 }
 
 
@@ -175,8 +218,8 @@ unsigned int rsPMCQ1MaIntConnect (
     unsigned long	busNo,	/* Pci Bus number of PMCQ1 */
     unsigned long	slotNo,	/* Pci Slot number of PMCQ1 */
     unsigned long	funcNo,	/* Pci Function number of PMCQ1 */
-    FUNCION_PTR	routine,/* interrupt routine */
-    int		arg	/* argument to pass to interrupt routine */
+    PMCQ1_FUNCTION_PTR	routine,/* interrupt routine */
+    void * 	        arg	/* argument to pass to interrupt routine */
 )
 {
   PPMCQ1BoardData boardData;
@@ -231,7 +274,7 @@ unsigned int rsPMCQ1MaIntDisconnect(
         (boardData->funcNo == funcNo))
     {
       boardData->maInt = NULL;
-      *(unsigned long *)(boardData->baseaddr + PMCQ1_INT_MASK) |= PMCQ1_INT_MASK_MA;
+      *(volatile unsigned long *)(boardData->baseaddr + PMCQ1_INT_MASK) |= PMCQ1_INT_MASK_MA;
       status = RTEMS_SUCCESSFUL;
       break;
     }
@@ -251,11 +294,11 @@ unsigned int rsPMCQ1MaIntDisconnect(
 */
 
 unsigned int rsPMCQ1QuiccIntConnect(
-    unsigned long	busNo,	/* Pci Bus number of PMCQ1 */
-    unsigned long	slotNo,	/* Pci Slot number of PMCQ1 */
-    unsigned long	funcNo,	/* Pci Function number of PMCQ1 */
-    FUNCION_PTR	routine,/* interrupt routine */
-    int		arg	/* argument to pass to interrupt routine */
+  unsigned long         busNo,	 /* Pci Bus number of PMCQ1 */ 
+  unsigned long         slotNo,  /* Pci Slot number of PMCQ1 */
+  unsigned long         funcNo,  /* Pci Function number of PMCQ1 */
+  PMCQ1_FUNCTION_PTR    routine, /* interrupt routine */
+  void *                arg      /* argument to pass to interrupt routine */
 )
 {
   PPMCQ1BoardData boardData;
@@ -300,7 +343,7 @@ unsigned int rsPMCQ1QuiccIntDisconnect(
         (boardData->funcNo == funcNo))
     {
       boardData->quiccInt = NULL;
-      *(unsigned long *)(boardData->baseaddr + PMCQ1_INT_MASK) |= PMCQ1_INT_MASK_QUICC;
+      *(volatile unsigned long *)(boardData->baseaddr + PMCQ1_INT_MASK) |= PMCQ1_INT_MASK_QUICC;
       status = RTEMS_SUCCESSFUL;
       break;
     }
@@ -323,25 +366,22 @@ unsigned int rsPMCQ1Init(void)
 {
   int busNo;
   int slotNo;
-  unsigned int baseaddr = 0;
-  unsigned int bridgeaddr = 0;
+  uint32_t baseaddr = 0;
+  uint32_t bridgeaddr = 0;
   unsigned long pbti0_ctl;
   int i;
   unsigned char int_vector;
   int fun;
-  int temp;
+  uint32_t temp;
   PPMCQ1BoardData       boardData;
-  rtems_irq_connect_data IrqData = {0,
-                                    rsPMCQ1Int,
-                                    rsPMCQ1_scc_nullFunc,
-                                    rsPMCQ1_scc_nullFunc,
-                                    rsPMCQ1_scc_nullFunc,
-                                    NULL};
+  rtems_irq_connect_data *IrqData = NULL;
 
   if (rsPMCQ1Initialized)
   {
+    printk("rsPMCQ1Init: Already Initialized\n");
     return RTEMS_SUCCESSFUL;
-  }
+  } 
+
   for (i=0;;i++){
     if ( pci_find_device(PCI_VEN_ID_RADSTONE, PCI_DEV_ID_PMCQ1, i, &busNo, &slotNo, &fun) != 0 )
       break;
@@ -349,17 +389,17 @@ unsigned int rsPMCQ1Init(void)
     pci_read_config_dword(busNo, slotNo, 0, PCI_BASE_ADDRESS_2, &baseaddr);
     pci_read_config_dword(busNo, slotNo, 0, PCI_BASE_ADDRESS_0, &bridgeaddr);
 #ifdef DEBUG_360
-  printk("PMCQ1 baseaddr 0x%08x bridgeaddr 0x%08x\n", baseaddr, bridgeaddr );
+  printk("rsPMCQ1Init: PMCQ1 baseaddr 0x%08x bridgeaddr 0x%08x\n", baseaddr, bridgeaddr );
 #endif
 
     /* Set function code to normal mode and enable window */
-    pbti0_ctl = *(unsigned long *)(bridgeaddr + 0x100) & 0xff0fffff;
+    pbti0_ctl = (*(unsigned long *)(bridgeaddr + 0x100)) & 0xff0fffff;
     eieio();
-    *(unsigned long *)(bridgeaddr + 0x100) = pbti0_ctl | 0x00500080;
+    *(volatile unsigned long *)(bridgeaddr + 0x100) = pbti0_ctl | 0x00500080;
     eieio();
 
     /* Assert QBUS reset */
-    *(unsigned long *)(bridgeaddr + 0x800) |= 0x00000080;
+    *(volatile unsigned long *)(bridgeaddr + 0x800) |= 0x00000080;
     eieio();
 
     /*
@@ -368,7 +408,7 @@ unsigned int rsPMCQ1Init(void)
     MsDelay();
 
     /* Take QBUS out of reset */
-    *(unsigned long *)(bridgeaddr + 0x800) &= ~0x00000080;
+    *(volatile unsigned long *)(bridgeaddr + 0x800) &= ~0x00000080;
     eieio();
 
     MsDelay();
@@ -377,19 +417,19 @@ unsigned int rsPMCQ1Init(void)
     if (PMCQ1_Read_EPLD(baseaddr, PMCQ1_BUILD_OPTION) & PMCQ1_QUICC_FITTED)
     {
 #ifdef DEBUG_360 
-  printk(" Found QUICC busNo %d slotNo %d\n", busNo, slotNo);
+  printk("rsPMCQ1Init: Found QUICC busNo %d slotNo %d\n", busNo, slotNo);
 #endif
 
       /* Initialise MBAR (must use function code of 7) */
-      *(unsigned long *)(bridgeaddr + 0x100) = pbti0_ctl | 0x00700080;
+      *(volatile unsigned long *)(bridgeaddr + 0x100) = pbti0_ctl | 0x00700080;
       eieio();
 
       /* place internal 8K SRAM and registers at address 0x0 */
-      *(unsigned long *)(baseaddr + Q1_360_MBAR) = 0x1;
+      *(volatile unsigned long *)(baseaddr + Q1_360_MBAR) = 0x1;
       eieio();
 
       /* Set function code to normal mode */
-      *(unsigned long *)(bridgeaddr + 0x100) = pbti0_ctl | 0x00500080;
+      *(volatile unsigned long *)(bridgeaddr + 0x100) = pbti0_ctl | 0x00500080;
       eieio();
 
       /* Disable the SWT and perform basic initialisation */
@@ -425,15 +465,15 @@ unsigned int rsPMCQ1Init(void)
      */
     pci_read_config_dword(busNo, slotNo, 0, PCI_BASE_ADDRESS_3, &temp);
     if (temp) {
-      *(unsigned long *)(bridgeaddr + 0x110) |= 0x00500880;
+      *(volatile unsigned long *)(bridgeaddr + 0x110) |= 0x00500880;
     }
 
     /*
      * Create descriptor structure for this card
      */
-    if ((boardData = malloc(sizeof(struct _PMCQ1BoardData))) == NULL)
+    if ((boardData = calloc(1, sizeof(struct _PMCQ1BoardData))) == NULL)
     {
-      printk("Error Unable to allocate memory for _PMCQ1BoardData\n");
+      printk("rsPMCQ1Init: Error Unable to allocate memory for _PMCQ1BoardData\n");
       return(RTEMS_IO_ERROR);
     }
 
@@ -446,6 +486,7 @@ unsigned int rsPMCQ1Init(void)
     boardData->quiccInt = NULL;
     boardData->maInt = NULL;
     pmcq1BoardData = boardData;
+
     mc68360_scc_create_chip( boardData, int_vector );
 
     /*
@@ -453,11 +494,22 @@ unsigned int rsPMCQ1Init(void)
      */
     pci_read_config_byte(busNo, slotNo, 0, 0x3c, &int_vector);
 #ifdef DEBUG_360
-    printk("PMCQ1 int_vector %d\n", int_vector);
+    printk("rsPMCQ1Init: PMCQ1 int_vector %d\n", int_vector);
 #endif
-    IrqData.name  = ((unsigned int)BSP_PCI_IRQ0 + int_vector);
-    IrqData.handle = boardData;
-    if (!BSP_install_rtems_shared_irq_handler (&IrqData)) {
+
+    if ((IrqData = calloc( 1, sizeof(rtems_irq_connect_data) )) == NULL )
+    {
+      printk("rsPMCQ1Init: Error Unable to allocate memory for rtems_irq_connect_data\n");
+      return(RTEMS_IO_ERROR);
+    }
+    IrqData->name   = ((unsigned int)BSP_PCI_IRQ0 + int_vector);
+    IrqData->hdl    = rsPMCQ1Int;
+    IrqData->handle = boardData;
+    IrqData->on     = rsPMCQ1_scc_On;
+    IrqData->off    = rsPMCQ1_scc_Off;
+    IrqData->isOn   = rsPMCQ1_scc_except_always_enabled;
+
+    if (!BSP_install_rtems_shared_irq_handler (IrqData)) {
         printk("Error installing interrupt handler!\n");
         rtems_fatal_error_occurred(1);
     }
@@ -465,11 +517,10 @@ unsigned int rsPMCQ1Init(void)
     /*
      * Enable PMCQ1 Interrupts from QSPAN-II
      */
-        
-    *(unsigned long *)(bridgeaddr + 0x600) = 0x00001000;
+    *(volatile unsigned long *)(bridgeaddr + 0x600) = 0x00001000;
     eieio();
-    *(unsigned long *)(bridgeaddr + 0x604) |= 0x00001000;
-
+    Processor_Synchronize();
+    *(volatile unsigned long *)(bridgeaddr + 0x604) |= 0x00001000;
     eieio();
   }
 
@@ -512,9 +563,9 @@ unsigned int rsPMCQ1Commission( unsigned long busNo, unsigned long slotNo )
      * A real PMCQ1 also has the sub vendor ID set up.
      */
     if ((busNo == 0) && (slotNo == 1)) {
-      *(unsigned long *)rsPMCQ1eeprom = 0;
+      *(volatile unsigned long *)rsPMCQ1eeprom = 0;
     } else {
-      *(unsigned long *)rsPMCQ1eeprom = PCI_ID(PCI_VEN_ID_RADSTONE, PCI_DEV_ID_PMCQ1);
+      *(volatile unsigned long *)rsPMCQ1eeprom = PCI_ID(PCI_VEN_ID_RADSTONE, PCI_DEV_ID_PMCQ1);
     }
 
     for (i = 0; i < 23; i++) {
@@ -558,20 +609,27 @@ unsigned int rsPMCQ1Commission( unsigned long busNo, unsigned long slotNo )
 
 uint32_t PMCQ1_Read_EPLD( uint32_t base, uint32_t reg )
 {
-  uint32_t data;
+  uint32_t           data;
+  volatile uint32_t *ptr;
 
-  data = ( *((unsigned long *) (base + reg)) );
+  Processor_Synchronize();
+  ptr =  (volatile uint32_t *)(base + reg);
+  data =  *ptr ;
 #ifdef DEBUG_360
-  printk("EPLD Read 0x%x: 0x%08x\n", reg + base, data );
+  printk("EPLD Read 0x%x: 0x%08x\n", ptr, data );
 #endif
   return data;
 }
 
 void PMCQ1_Write_EPLD( uint32_t base, uint32_t reg, uint32_t data )
 {
-  *((unsigned long *) (base + reg)) = data;
+  volatile uint32_t *ptr;
+
+  ptr = (volatile uint32_t *) (base + reg);
+  *ptr = data;
+  Processor_Synchronize();
 #ifdef DEBUG_360
-  printk("EPLD Write 0x%x: 0x%08x\n", reg+base, data );
+  printk("EPLD Write 0x%x: 0x%08x\n", ptr, data );
 #endif
 }
 

c/src/lib/libbsp/powerpc/ep1a/console/rsPMCQ1.h

@@ -30,8 +30,8 @@
    01a,20Dec00,jpb         created
  */
 
-#ifndef __INCPMCQ1H
-#define __INCPMCQ1H
+#ifndef __RSPMCQ1_H
+#define __RSPMCQ1_H
 
 /*
  * PMCQ1 definitions
@@ -95,10 +95,6 @@
 #define PMCQ1_MINIACE_MEM       0x00100000
 #define PMCQ1_RAM               0x00200000
 
-/*
-#define PMCQ1_Read_EPLD( _base, _reg ) ( *((unsigned long *) ((unsigned32)_base + _reg)) )
-#define PMCQ1_Write_EPLD( _base, _reg, _data ) *((unsigned long *) ((unsigned32)_base + _reg)) = _data
-*/
 uint32_t PMCQ1_Read_EPLD( uint32_t base, uint32_t reg );
 void     PMCQ1_Write_EPLD( uint32_t base, uint32_t reg, uint32_t data );
 
@@ -108,7 +104,7 @@ void     PMCQ1_Write_EPLD( uint32_t base, uint32_t reg, uint32_t data );
 
 #define QSPAN2_INT_STATUS	0x00000600
 
-typedef void (*FUNCION_PTR) (int);
+typedef void (*PMCQ1_FUNCTION_PTR) (void *);
 
 #define PCI_ID(v, d) ((d << 16) | v)
 
@@ -125,16 +121,16 @@ typedef void (*FUNCION_PTR) (int);
 
 typedef struct _PMCQ1BoardData 
 {
-    struct _PMCQ1BoardData   		*pNext;     
-    unsigned long			busNo;
-    unsigned long			slotNo;
-    unsigned long			funcNo;
-    unsigned long			baseaddr;
-    unsigned long			bridgeaddr;
-    FUNCION_PTR				quiccInt;
-    int					quiccArg;
-    FUNCION_PTR				maInt;
-    int					maArg;
+    struct _PMCQ1BoardData              *pNext;     
+    unsigned long                       busNo;
+    unsigned long                       slotNo;
+    unsigned long                       funcNo;
+    unsigned long                       baseaddr;
+    unsigned long                       bridgeaddr;
+    PMCQ1_FUNCTION_PTR                  quiccInt;
+    void *                              quiccArg;
+    PMCQ1_FUNCTION_PTR                  maInt;
+    void *                              maArg;
 } PMCQ1BoardData, *PPMCQ1BoardData;
 
 extern PPMCQ1BoardData  pmcq1BoardData;
@@ -146,16 +142,18 @@ extern unsigned int rsPMCQ1QuiccIntConnect(
   unsigned long         busNo, 
   unsigned long         slotNo, 
   unsigned long         funcNo, 
-  FUNCION_PTR           routine, 
-  int                   arg
+  PMCQ1_FUNCTION_PTR    routine, 
+  void *                arg
 );
 unsigned int rsPMCQ1Init();
 unsigned int rsPMCQ1MaIntConnect (
     unsigned long       busNo,  /* Pci Bus number of PMCQ1 */
     unsigned long       slotNo, /* Pci Slot number of PMCQ1 */
     unsigned long       funcNo, /* Pci Function number of PMCQ1 */
-    FUNCION_PTR         routine,/* interrupt routine */
-    int                 arg     /* argument to pass to interrupt routine */
+    PMCQ1_FUNCTION_PTR  routine,/* interrupt routine */
+    void *              arg     /* argument to pass to interrupt routine */
 );
 
-#endif				/* __INCPMCQ1H */
+void rsPMCQ1ShowIntrStatus(void );
+
+#endif				/* __RSPMCQ1_H */

c/src/lib/libbsp/powerpc/ep1a/include/bsp.h

@@ -1,6 +1,6 @@
 /*
  *
- *  COPYRIGHT (c) 1989-1999.
+ *  COPYRIGHT (c) 1989-2009.
  *  On-Line Applications Research Corporation (OAR).
  *
  *  The license and distribution terms for this file may be
@@ -13,6 +13,9 @@
 #ifndef _BSP_H
 #define _BSP_H
 
+
+#define BSP_ZERO_WORKSPACE_AUTOMATICALLY TRUE
+
 #include <bspopts.h>
 
 #include <rtems.h>

c/src/lib/libbsp/powerpc/ep1a/irq/irq.h

@@ -0,0 +1,110 @@
+/* 
+ *
+ *  This include file describe the data structure and the functions implemented
+ *  by RTEMS to write interrupt handlers.
+ *
+ *  Copyright (C) 1999 valette@crf.canon.fr
+ *
+ *  This code is heavilly inspired by the public specification of STREAM V2
+ *  that can be found at :
+ *
+ *      <http://www.chorus.com/Documentation/index.html> by following
+ *  the STREAM API Specification Document link.
+ *
+ *  The license and distribution terms for this file may be
+ *  found in found in the file LICENSE in this distribution or at
+ *  http://www.rtems.com/license/LICENSE.
+ *
+ *  $Id$
+ */
+
+#ifndef BSP_POWERPC_IRQ_H
+#define BSP_POWERPC_IRQ_H
+
+#define BSP_SHARED_HANDLER_SUPPORT      1
+#include <rtems/irq.h>
+
+/* PIC's command and mask registers */
+#define PIC_MASTER_COMMAND_IO_PORT 0x20 /* Master PIC command register */
+#define PIC_SLAVE_COMMAND_IO_PORT  0xa0 /* Slave PIC command register */
+#define PIC_MASTER_IMR_IO_PORT     0x21 /* Master PIC Interrupt Mask Register */
+#define PIC_SLAVE_IMR_IO_PORT      0xa1 /* Slave PIC Interrupt Mask Register */
+
+/* Command for specific EOI (End Of Interrupt): Interrupt acknowledge */
+#define PIC_EOSI        0x60  /* End of Specific Interrupt (EOSI) */
+#define SLAVE_PIC_EOSI  0x62 /* End of Specific Interrupt (EOSI) for cascade */
+#define PIC_EOI         0x20  /* Generic End of Interrupt (EOI) */
+
+#ifndef ASM
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * rtems_irq_number Definitions
+ */
+
+/*
+ * ISA IRQ handler related definitions
+ */
+#define BSP_ISA_IRQ_NUMBER         (16)
+#define BSP_ISA_IRQ_LOWEST_OFFSET  (0)
+#define BSP_ISA_IRQ_MAX_OFFSET \
+        (BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER - 1)
+/*
+ * PCI IRQ handlers related definitions
+ * CAUTION : BSP_PCI_IRQ_LOWEST_OFFSET should be equal to OPENPIC_VEC_SOURCE
+ */
+#define BSP_PCI_IRQ_NUMBER        (26)
+#define BSP_PCI_IRQ_LOWEST_OFFSET (BSP_ISA_IRQ_NUMBER)
+#define BSP_PCI_IRQ_MAX_OFFSET    \
+        (BSP_PCI_IRQ_LOWEST_OFFSET + BSP_PCI_IRQ_NUMBER - 1)
+
+/*
+ * PowerPC exceptions handled as interrupt where an RTEMS managed interrupt
+ * handler might be connected
+ */
+#define BSP_PROCESSOR_IRQ_NUMBER        (1)
+#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_PCI_IRQ_MAX_OFFSET + 1)
+#define BSP_PROCESSOR_IRQ_MAX_OFFSET \
+        (BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER - 1)
+/*
+ * Misc vectors for OPENPIC irqs (IPI, timers)
+ */
+#define BSP_MISC_IRQ_NUMBER        (8)
+#define BSP_MISC_IRQ_LOWEST_OFFSET (BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 1)
+#define BSP_MISC_IRQ_MAX_OFFSET \
+        (BSP_MISC_IRQ_LOWEST_OFFSET + BSP_MISC_IRQ_NUMBER - 1)
+/*
+ * Summary
+ */
+#define BSP_IRQ_NUMBER      (BSP_MISC_IRQ_MAX_OFFSET + 1)
+#define BSP_LOWEST_OFFSET   (BSP_ISA_IRQ_LOWEST_OFFSET)
+#define BSP_MAX_OFFSET      (BSP_MISC_IRQ_MAX_OFFSET)
+
+
+/*
+ * Some PCI IRQ symbolic name definition
+ */
+#define BSP_PCI_IRQ0      (BSP_PCI_IRQ_LOWEST_OFFSET)
+
+/*
+ * Some Processor execption handled as RTEMS IRQ symbolic name definition
+ */
+#define BSP_DECREMENTER   (BSP_PROCESSOR_IRQ_LOWEST_OFFSET)
+
+/*
+ * Type definition for RTEMS managed interrupts
+ */
+typedef unsigned short rtems_i8259_masks;
+extern  volatile rtems_i8259_masks i8259s_cache;
+
+/* Stuff in irq_supp.h should eventually go into <rtems/irq.h> */
+#include <bsp/irq_supp.h>
+
+#ifdef __cplusplus
+};
+#endif
+
+#endif
+#endif

c/src/lib/libbsp/powerpc/ep1a/irq/irq_init.c

@@ -5,13 +5,13 @@
  *
  *  CopyRight (C) 1999 valette@crf.canon.fr
  *
- * Enhanced by Jay Kulpinski <jskulpin@eng01.gdds.com>
- * to make it valid for MVME2300 Motorola boards.
+ *  Enhanced by Jay Kulpinski <jskulpin@eng01.gdds.com>
+ *  to make it valid for MVME2300 Motorola boards.
  *
- * Till Straumann <strauman@slac.stanford.edu>, 12/20/2001:
- * Use the new interface to openpic_init
+ *  Till Straumann <strauman@slac.stanford.edu>, 12/20/2001:
+ *  Use the new interface to openpic_init
  *
- *  COPYRIGHT (c) 1989-1999.
+ *  COPYRIGHT (c) 1989-2009.
  *  On-Line Applications Research Corporation (OAR).
  *
  *  The license and distribution terms for this file may be
@@ -32,74 +32,91 @@
 #include <bsp/motorola.h>
 #include <rtems/bspIo.h>
 
-/*
-#define SHOW_ISA_PCI_BRIDGE_SETTINGS
-*/
-#define TRACE_IRQ_INIT
+#if 0 
+#define TRACE_IRQ_INIT 1   /* XXX */
+#endif
 
-/*
- * default on/off function
- */
-static void nop_func(void){}
-/*
- * default isOn function
- */
-static int not_connected(void) {return 0;}
-/*
- * default possible isOn function
- */
-static int connected(void) {return 1;}
+typedef struct {
+  unsigned char bus;	/* few chance the PCI/ISA bridge is not on first bus but ... */
+  unsigned char device;
+  unsigned char function;
+} pci_isa_bridge_device;
 
+pci_isa_bridge_device* via_82c586 = 0;
+#if 0
+static pci_isa_bridge_device bridge;
+#endif
+
+
+
+extern unsigned int external_exception_vector_prolog_code_size[];
+extern void external_exception_vector_prolog_code();
+extern unsigned int decrementer_exception_vector_prolog_code_size[];
+extern void decrementer_exception_vector_prolog_code();
+
+
+static void IRQ_Default_rtems_irq_hdl( rtems_irq_hdl_param ptr ) { printk("IRQ_Default_rtems_irq_hdl\n"); }
+static void IRQ_Default_rtems_irq_enable (const struct __rtems_irq_connect_data__ *ptr)   {}
+static void IRQ_Default_rtems_irq_disable(const struct __rtems_irq_connect_data__ *ptr)   {}
+static int  IRQ_Default_rtems_irq_is_enabled(const struct __rtems_irq_connect_data__ *ptr){ return 1; }
 static rtems_irq_connect_data     	rtemsIrq[BSP_IRQ_NUMBER];
 static rtems_irq_global_settings     	initial_config;
 static rtems_irq_connect_data     	defaultIrq = {
-  /* vectorIdex,	 hdl		, handle	, on		, off		, isOn */
-  0, 			 nop_func	, NULL		, nop_func	, nop_func	, not_connected
+/*name,	 hdl				handle	on				off				isOn */
+  0,	 IRQ_Default_rtems_irq_hdl,	NULL,	IRQ_Default_rtems_irq_enable,	IRQ_Default_rtems_irq_disable,	IRQ_Default_rtems_irq_is_enabled
 };
+
+
+/*
+ *  If the BSP_IRQ_NUMBER changes the following if will force the tables to be corrected.
+ */
+#if ( (BSP_ISA_IRQ_NUMBER == 16)      && \
+      (BSP_PCI_IRQ_NUMBER == 26)      && \
+      (BSP_PROCESSOR_IRQ_NUMBER == 1) && \
+      (BSP_MISC_IRQ_NUMBER == 8) )
+
+
 static rtems_irq_prio irqPrioTable[BSP_IRQ_NUMBER]={
-  /*
-   * actual rpiorities for interrupt :
-   *	0   means that only current interrupt is masked
-   *	255 means all other interrupts are masked
-   */
   /*
    * ISA interrupts.
-   * The second entry has a priority of 255 because
-   * it is the slave pic entry and is should always remain
-   * unmasked.
    */
-  0,0,
-  255,
+  0, 0,
+  (OPENPIC_NUM_PRI-1),
   0, 0, 0, 0,  0,  0,  0,  0,  0,  0,  0,  0,  0,
+
   /*
    * PCI Interrupts
    */
-  8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, /* for raven prio 0 means unactive... */
+  8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 
+  8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 
+
   /*
    * Processor exceptions handled as interrupts
    */
-  0
+  8,
+ 
+  8, 8, 8, 8, 8, 8, 8, 8
 };
 
-static unsigned char mcp750_openpic_initpolarities[] = {
+static unsigned char mpc8245_openpic_initpolarities[] = {
     1,  /*  0 8259 cascade */
-    0,	/*  1 all the rest of them */
-    0,  /*  2 all the rest of them */
-    0,  /*  3 all the rest of them */
-    0,  /*  4 all the rest of them */
-    0,  /*  5 all the rest of them */
-    0,  /*  6 all the rest of them */
-    0,  /*  7 all the rest of them */
-    0,  /*  8 all the rest of them */
-    0,  /*  9 all the rest of them */
-    0,  /* 10 all the rest of them */
-    0,  /* 11 all the rest of them */
-    0,  /* 12 all the rest of them */
-    0,  /* 13 all the rest of them */
-    0,  /* 14 all the rest of them */
-    0,  /* 15 all the rest of them */
-    0,  /* 16 all the rest of them */
-    0,  /* 17 all the rest of them */
+    0,	/*  1 */
+    0,  /*  2 */
+    0,  /*  3 */
+    0,  /*  4 */
+    0,  /*  5 */
+    0,  /*  6 */
+    0,  /*  7 */
+    0,  /*  8 */
+    0,  /*  9 */
+    0,  /* 10 */
+    0,  /* 11 */
+    0,  /* 12 */
+    0,  /* 13 */
+    0,  /* 14 */
+    0,  /* 15 */
+    0,  /* 16 */
+    0,  /* 17 */
     1,  /* 18 all the rest of them */
     1,  /* 19 all the rest of them */
     1,  /* 20 all the rest of them */
@@ -108,25 +125,78 @@ static unsigned char mcp750_openpic_initpolarities[] = {
     1,  /* 23 all the rest of them */
     1,  /* 24 all the rest of them */
     1,  /* 25 all the rest of them */
+    1,  /* 26 all the rest of them */
+    1,	/* 27 all the rest of them */
+    1,  /* 28 all the rest of them */
+    1,  /* 29 all the rest of them */
+    1,  /* 30 all the rest of them */
+    1,  /* 31 all the rest of them */
+    1,  /* 32 all the rest of them */
+    1,  /* 33 all the rest of them */
+    1,  /* 34 all the rest of them */
+    1,  /* 35 all the rest of them */
+    1,  /* 36 all the rest of them */
+    1,  /* 37 all the rest of them */
+    1,  /* 38 all the rest of them */
+    1,  /* 39 all the rest of them */
+    1,  /* 40 all the rest of them */
+    1,  /* 41 all the rest of them */
+    1,  /* 42 all the rest of them */
+    1,  /* 43 all the rest of them */
+    1,  /* 44 all the rest of them */
+    1,  /* 45 all the rest of them */
+    1,  /* 46 all the rest of them */
+    1,  /* 47 all the rest of them */
+    1,  /* 48 all the rest of them */
+    1,  /* 49 all the rest of them */
+    1,  /* 50 all the rest of them */
+    1,  /* 51 all the rest of them */
+
 };
 
-static unsigned char mcp750_openpic_initsenses[] = {
-    1,	/* 0 MCP750_INT_PCB(8259) */
-    0,	/* 1 MCP750_INT_FALCON_ECC_ERR */
-    1,	/* 2 MCP750_INT_PCI_ETHERNET */
-    1,	/* 3 MCP750_INT_PCI_PMC */
-    1,	/* 4 MCP750_INT_PCI_WATCHDOG_TIMER1 */
-    1,	/* 5 MCP750_INT_PCI_PRST_SIGNAL */
-    1,	/* 6 MCP750_INT_PCI_FALL_SIGNAL */
-    1,	/* 7 MCP750_INT_PCI_DEG_SIGNAL */
-    1,	/* 8 MCP750_INT_PCI_BUS1_INTA */
-    1,	/* 9 MCP750_INT_PCI_BUS1_INTB */
-    1,	/*10 MCP750_INT_PCI_BUS1_INTC */
-    1,	/*11 MCP750_INT_PCI_BUS1_INTD */
-    1,	/*12 MCP750_INT_PCI_BUS2_INTA */
-    1,	/*13 MCP750_INT_PCI_BUS2_INTB */
-    1,	/*14 MCP750_INT_PCI_BUS2_INTC */
-    1,	/*15 MCP750_INT_PCI_BUS2_INTD */
+static unsigned char mpc8245_openpic_initsenses[] = {
+    1,	/* 0  */
+    0,	/* 1  */
+    1,	/* 2  */
+    1,	/* 3  */
+    1,	/* 4  */
+    1,	/* 5  */
+    1,	/* 6  */
+    1,	/* 7  */
+    1,	/* 8  */
+    1,	/* 9  */
+    1,	/*10  */
+    1,	/*11  */
+    1,	/*12  */
+    1,	/*13  */
+    1,	/*14  */
+    1,	/*15  */
+    1,
+    1, 
+    1,
+    1,
+    1,
+    1,
+    1,
+    1,
+    1,
+    1,
+    1,
+    1,
+    1,
+    1,
+    1,
+    1,
+    1,
+    1,
+    1,
+    1,
+    1,
+    1,
+    1,
+    1,
+    1,
+    1,
     1,
     1, 
     1,
@@ -138,6 +208,7 @@ static unsigned char mcp750_openpic_initsenses[] = {
     1,
     1
 };
+#endif
 
   /*
    * This code assumes the exceptions management setup has already
@@ -147,24 +218,41 @@ static unsigned char mcp750_openpic_initsenses[] = {
    */
 void BSP_rtems_irq_mng_init(unsigned cpuId)
 {
-  int i;
+  int                           i;
 
   /*
    * First initialize the Interrupt management hardware
    */
 #ifdef TRACE_IRQ_INIT  
-  printk("Going to initialize openpic compliant device\n");
-#endif       
+  uint32_t                      msr;
+
+  _CPU_MSR_GET( msr );
+  printk("BSP_rtems_irq_mng_init: Initialize openpic compliant device with MSR %x \n", msr);
+  printk(" BSP_ISA_IRQ_NUMBER %d\n",BSP_ISA_IRQ_NUMBER );
+  printk(" BSP_ISA_IRQ_LOWEST_OFFSET %d\n",BSP_ISA_IRQ_LOWEST_OFFSET );
+  printk(" BSP_ISA_IRQ_MAX_OFFSET %d\n", BSP_ISA_IRQ_MAX_OFFSET);
+  printk(" BSP_PCI_IRQ_NUMBER %d\n",BSP_PCI_IRQ_NUMBER );
+  printk(" BSP_PCI_IRQ_LOWEST_OFFSET %d\n",BSP_PCI_IRQ_LOWEST_OFFSET );
+  printk(" BSP_PCI_IRQ_MAX_OFFSET %d\n",BSP_PCI_IRQ_MAX_OFFSET );
+  printk(" BSP_PROCESSOR_IRQ_NUMBER %d\n",BSP_PROCESSOR_IRQ_NUMBER );
+  printk(" BSP_PROCESSOR_IRQ_LOWEST_OFFSET %d\n",BSP_PROCESSOR_IRQ_LOWEST_OFFSET );
+  printk(" BSP_PROCESSOR_IRQ_MAX_OFFSET %d\n", BSP_PROCESSOR_IRQ_MAX_OFFSET);
+  printk(" BSP_MISC_IRQ_NUMBER %d\n", BSP_MISC_IRQ_NUMBER);
+  printk(" BSP_MISC_IRQ_LOWEST_OFFSET %d\n", BSP_MISC_IRQ_LOWEST_OFFSET);
+  printk(" BSP_MISC_IRQ_MAX_OFFSET %d\n",BSP_MISC_IRQ_MAX_OFFSET );
+  printk(" BSP_IRQ_NUMBER %d\n",BSP_IRQ_NUMBER );
+  printk(" BSP_LOWEST_OFFSET %d\n",BSP_LOWEST_OFFSET );
+  printk(" BSP_MAX_OFFSET %d\n",BSP_MAX_OFFSET );
+#endif
+       
   /* FIXME (t.s.): we should probably setup the EOI delay by
    * passing a non-zero 'epic_freq' argument (frequency of the
    * EPIC serial interface) but I don't know the value on this
    * board (8245 SDRAM freq, IIRC)...
+   *
+   * When tested this appears to work correctly.
    */
-  openpic_init(1, mcp750_openpic_initpolarities, mcp750_openpic_initsenses, 0, 16, 0 /* epic_freq */);
-
-#ifdef TRACE_IRQ_INIT  
-  printk("Going to initialize the PCI/ISA bridge IRQ related setting (VIA 82C586)\n");
-#endif
+  openpic_init(1, mpc8245_openpic_initpolarities, mpc8245_openpic_initsenses, 0, 0, 0);
 
   /*
    * Initialize Rtems management interrupt table
@@ -175,7 +263,11 @@ void BSP_rtems_irq_mng_init(unsigned cpuId)
     for (i = 0; i < BSP_IRQ_NUMBER; i++) {
       rtemsIrq[i]      = defaultIrq;
       rtemsIrq[i].name = i;
+#ifdef BSP_SHARED_HANDLER_SUPPORT
+      rtemsIrq[i].next_handler = NULL;
+#endif
     }
+
     /*
      * Init initial Interrupt management config
      */
@@ -185,14 +277,20 @@ void BSP_rtems_irq_mng_init(unsigned cpuId)
     initial_config.irqBase	= BSP_LOWEST_OFFSET;
     initial_config.irqPrioTbl	= irqPrioTable;
 
-printk("Call BSP_rtems_irq_mngt_set\n");
+
+#ifdef TRACE_IRQ_INIT  
+    _CPU_MSR_GET( msr );
+    printk("BSP_rtems_irq_mng_init: Set initial configuration with MSR %x\n", msr);
+#endif
     if (!BSP_rtems_irq_mngt_set(&initial_config)) {
       /*
        * put something here that will show the failure...
        */
       BSP_panic("Unable to initialize RTEMS interrupt Management!!! System locked\n");
+    }  else {
+      printk(" Initialized RTEMS Interrupt Manager\n");
     }
-  
+
 #ifdef TRACE_IRQ_INIT  
     printk("RTEMS IRQ management is now operationnal\n");
 #endif

c/src/lib/libbsp/powerpc/ep1a/irq/openpic_xxx_irq.c

@@ -23,7 +23,7 @@
 #include <bsp/vectors.h>
 #include <stdlib.h>
 
-#include <rtems/bspIo.h> /* for printk */
+#include <rtems/bspIo.h> 
 #define RAVEN_INTR_ACK_REG 0xfeff0030
 
 #ifdef BSP_PCI_ISA_BRIDGE_IRQ
@@ -41,28 +41,31 @@ rtems_i8259_masks 	irq_mask_or_tbl[BSP_IRQ_NUMBER];
 /*
  * default handler connected on each irq after bsp initialization
  */
-static rtems_irq_connect_data	default_rtems_entry;
+static rtems_irq_connect_data	   default_rtems_entry;
+static rtems_irq_connect_data*	   rtems_hdl_tbl;
 
-static rtems_irq_connect_data*		rtems_hdl_tbl;
-
-#ifdef BSP_PCI_ISA_BRIDGE_IRQ
 /*
  * Check if IRQ is an ISA IRQ
  */
 static inline int is_isa_irq(const rtems_irq_number irqLine)
 {
-  return (((int) irqLine <= BSP_ISA_IRQ_MAX_OFFSET) &
+  if  ( BSP_ISA_IRQ_NUMBER == 0 )
+    return FALSE;
+
+  return (((int) irqLine <= BSP_ISA_IRQ_MAX_OFFSET) &&
 	  ((int) irqLine >= BSP_ISA_IRQ_LOWEST_OFFSET)
 	 );
 }
-#endif
 
 /*
  * Check if IRQ is an OPENPIC IRQ
  */
 static inline int is_pci_irq(const rtems_irq_number irqLine)
 {
-  return (((int) irqLine <= BSP_PCI_IRQ_MAX_OFFSET) &
+  if ( BSP_PCI_IRQ_NUMBER == 0 )
+    return FALSE;
+
+  return (((int) irqLine <= BSP_PCI_IRQ_MAX_OFFSET) &&
 	  ((int) irqLine >= BSP_PCI_IRQ_LOWEST_OFFSET)
 	 );
 }
@@ -98,46 +101,34 @@ static void compute_i8259_masks_from_prio (rtems_irq_global_settings* config)
 }
 #endif
 
-void
-BSP_enable_irq_at_pic(const rtems_irq_number name)
+void BSP_enable_irq_at_pic(const rtems_irq_number name)
 {
-#ifdef BSP_PCI_ISA_BRIDGE_IRQ
-    if (is_isa_irq(name)) {
-      /*
-       * Enable interrupt at PIC level
-       */
-printk("ERROR BSP_irq_enable_at_i8259s Being Called for %d\n", (int)name);
-      BSP_irq_enable_at_i8259s ((int) name);
-    }
-#endif
-    
-    if (is_pci_irq(name)) {
-      /*
-       * Enable interrupt at OPENPIC level
-       */
-printk(" openpic_enable_irq %d\n", (int)name );
-       openpic_enable_irq ((int) name);
-    }
+  if (is_isa_irq(name)) {
+    printk("BSP_enable_irq_at_pic: called with isa irq\n");
+  }
+  if (is_pci_irq(name)) {
+    /*
+     * enable interrupt at OPENPIC level.
+     */
+    openpic_enable_irq ( ((int)name - BSP_PCI_IRQ_LOWEST_OFFSET) + 16 );  
+  }
 }
 
-int
-BSP_disable_irq_at_pic(const rtems_irq_number name)
+int BSP_disable_irq_at_pic(const rtems_irq_number name)
 {
-#ifdef BSP_PCI_ISA_BRIDGE_IRQ
     if (is_isa_irq(name)) {
       /*
        * disable interrupt at PIC level
        */
-      return BSP_irq_disable_at_i8259s ((int) name);
+      printk("BSP_disable_irq_at_pic: called with isa irq\n");
     }
-#endif
     if (is_pci_irq(name)) {
       /*
        * disable interrupt at OPENPIC level
        */
-      return openpic_disable_irq ((int) name );
+      return openpic_disable_irq (((int) name - BSP_PCI_IRQ_LOWEST_OFFSET) + 16  );
     }
-	return -1;
+    return -1;
 }
 
 /*
@@ -146,23 +137,23 @@ BSP_disable_irq_at_pic(const rtems_irq_number name)
 int BSP_setup_the_pic(rtems_irq_global_settings* config)
 {
     int i;
+
    /*
     * Store various code accelerators
     */
     default_rtems_entry	= config->defaultEntry;
-    rtems_hdl_tbl 		= config->irqHdlTbl;
-
+    rtems_hdl_tbl 	= config->irqHdlTbl;
+    
     /*
      * set up internal tables used by rtems interrupt prologue
      */
-#if 0
 #ifdef BSP_PCI_ISA_BRIDGE_IRQ
     /*
      * start with ISA IRQ
      */
     compute_i8259_masks_from_prio (config);
 
-    for (i=BSP_ISA_IRQ_LOWEST_OFFSET; i < BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER; i++) {
+    for (i=BSP_ISA_IRQ_LOWEST_OFFSET; (i < (BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER)); i++) {
       if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) {
          BSP_irq_enable_at_i8259s (i);
       }
@@ -177,7 +168,6 @@ int BSP_setup_the_pic(rtems_irq_global_settings* config)
 		 */
 		BSP_irq_enable_at_i8259s (2);
 	}
-#endif
 #endif
 
     /*
@@ -190,27 +180,26 @@ int BSP_setup_the_pic(rtems_irq_global_settings* config)
       openpic_set_source_priority(i - BSP_PCI_IRQ_LOWEST_OFFSET,
 				  config->irqPrioTbl[i]);
       if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) {
-         openpic_enable_irq ((int) i );
+         openpic_enable_irq ((int) i - BSP_PCI_IRQ_LOWEST_OFFSET);
       }
       else {
-         openpic_disable_irq ((int) i );
+         openpic_disable_irq ((int) i - BSP_PCI_IRQ_LOWEST_OFFSET);
       }
     }
 
 #ifdef BSP_PCI_ISA_BRIDGE_IRQ
 	if ( BSP_ISA_IRQ_NUMBER > 0 ) {
-    	/*
-	     * Must enable PCI/ISA bridge IRQ
-	     */
-    	openpic_enable_irq (0);
+          /*
+           * Must enable PCI/ISA bridge IRQ
+           */
+          openpic_enable_irq (0);
 	}
 #endif
-
+    
     return 1;
 }
 
 int _BSP_vme_bridge_irq = -1;
-
 unsigned BSP_spuriousIntr = 0;
 
 /*
@@ -224,29 +213,24 @@ int C_dispatch_irq_handler (BSP_Exception_frame *frame, unsigned int excNum)
   register unsigned oldMask = 0;	      /* old isa pic masks */
   register unsigned newMask;                  /* new isa pic masks */
 #endif
-
   if (excNum == ASM_DEC_VECTOR) {
-/* printk("ASM_DEC_VECTOR\n"); */
-  	bsp_irq_dispatch_list(rtems_hdl_tbl, BSP_DECREMENTER, default_rtems_entry.hdl);
-
+    bsp_irq_dispatch_list_base(rtems_hdl_tbl, BSP_DECREMENTER, default_rtems_entry.hdl);
     return 0;
 
   }
   irq = openpic_irq(0);
   if (irq == OPENPIC_VEC_SPURIOUS) {
-/* printk("OPENPIC_VEC_SPURIOUS interrupt %d\n", OPENPIC_VEC_SPURIOUS ); */
-     ++BSP_spuriousIntr;
+    printk("OPENPIC_VEC_SPURIOUS interrupt %d\n", OPENPIC_VEC_SPURIOUS );
+    ++BSP_spuriousIntr;
     return 0;
   }
 
   /* some BSPs might want to use a different numbering... */
-  irq = irq - OPENPIC_VEC_SOURCE + BSP_PCI_IRQ_LOWEST_OFFSET;
-/* printk("OpenPic Irq: %d\n", irq); */
+  irq = irq - OPENPIC_VEC_SOURCE ;
 
 #ifdef BSP_PCI_ISA_BRIDGE_IRQ
   isaIntr = (irq == BSP_PCI_ISA_BRIDGE_IRQ);
   if (isaIntr)  {
-/* printk("BSP_PCI_ISA_BRIDGE_IRQ\n"); */
     /*
      * Acknowledge and read 8259 vector
      */
@@ -264,30 +248,28 @@ int C_dispatch_irq_handler (BSP_Exception_frame *frame, unsigned int excNum)
   }
 #endif
 
-
   /* dispatch handlers */
-/* printk("dispatch\n"); */
-irq -=16;
-  bsp_irq_dispatch_list(rtems_hdl_tbl, irq, default_rtems_entry.hdl);
-/* printk("Back from dispatch\n"); */
+  bsp_irq_dispatch_list_base(rtems_hdl_tbl, irq, default_rtems_entry.hdl);
 
 #ifdef BSP_PCI_ISA_BRIDGE_IRQ
-  if (isaIntr)  {\
+  if (isaIntr)  {
     i8259s_cache = oldMask;
     outport_byte(PIC_MASTER_IMR_IO_PORT, i8259s_cache & 0xff);
     outport_byte(PIC_SLAVE_IMR_IO_PORT, ((i8259s_cache & 0xff00) >> 8));
   }
   else
 #endif
+
   {
 #ifdef BSP_PCI_VME_DRIVER_DOES_EOI
-	/* leave it to the VME bridge driver to do EOI, so
+    /* leave it to the VME bridge driver to do EOI, so
      * it can re-enable the openpic while handling
      * VME interrupts (-> VME priorities in software)
-	 */
-	if (_BSP_vme_bridge_irq != irq)
+     */
+    if (_BSP_vme_bridge_irq != irq)
 #endif
-    		openpic_eoi(0);
+      openpic_eoi(0);
   }
   return 0;
+
 }

c/src/lib/libbsp/powerpc/ep1a/preinstall.am

@@ -57,9 +57,9 @@ $(PROJECT_LIB)/linkcmds: startup/linkcmds $(PROJECT_LIB)/$(dirstamp)
 	$(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds
 PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds
 
-$(PROJECT_INCLUDE)/bsp/uart.h: ../../powerpc/shared/console/uart.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
-	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/uart.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/uart.h
+$(PROJECT_INCLUDE)/bsp/pci.h: ../../powerpc/shared/pci/pci.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/pci.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/pci.h
 
 $(PROJECT_INCLUDE)/bsp/motorola.h: ../../powerpc/shared/motorola/motorola.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
 	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/motorola.h
@@ -81,15 +81,7 @@ $(PROJECT_INCLUDE)/bsp/rsPMCQ1.h: console/rsPMCQ1.h $(PROJECT_INCLUDE)/bsp/$(dir
 	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/rsPMCQ1.h
 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/rsPMCQ1.h
 
-$(PROJECT_INCLUDE)/bsp/openpic.h: ../../powerpc/shared/openpic/openpic.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
-	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/openpic.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/openpic.h
-
-$(PROJECT_INCLUDE)/bsp/pci.h: ../../powerpc/shared/pci/pci.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
-	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/pci.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/pci.h
-
-$(PROJECT_INCLUDE)/bsp/irq.h: ../../powerpc/shared/irq/irq.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+$(PROJECT_INCLUDE)/bsp/irq.h: irq/irq.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
 	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq.h
 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq.h
 
@@ -105,6 +97,10 @@ $(PROJECT_INCLUDE)/bsp/irq_supp.h: ../../../libcpu/@RTEMS_CPU@/@exceptions@/bsps
 	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq_supp.h
 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq_supp.h
 
+$(PROJECT_INCLUDE)/bsp/openpic.h: ../../powerpc/shared/openpic/openpic.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/openpic.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/openpic.h
+
 $(PROJECT_INCLUDE)/bsp/vmeUniverse.h: ../../shared/vmeUniverse/vmeUniverse.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
 	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/vmeUniverse.h
 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/vmeUniverse.h

c/src/lib/libbsp/powerpc/ep1a/start/start.S

@@ -114,6 +114,10 @@ __rtems_entry_point:
 	lis	sp,__stack@h
 	ori	sp,sp,__stack@l
 
+        lis	r13,_SDA_BASE_@ha
+	la	r13,_SDA_BASE_@l(r13)  		/* Read-write small data */
+
+
 	/* set up initial stack frame */
 	addi	sp,sp,-4		/* make sure we don't overwrite debug mem */
 	lis	r0,0

c/src/lib/libbsp/powerpc/ep1a/startup/bspstart.c

@@ -4,7 +4,7 @@
  *  The generic CPU dependent initialization has been performed
  *  before this routine is invoked.
  *
- *  COPYRIGHT (c) 1989-2007.
+ *  COPYRIGHT (c) 1989-2009.
  *  On-Line Applications Research Corporation (OAR).
  *
  *  The license and distribution terms for this file may be
@@ -14,7 +14,7 @@
  *  $Id$
  */
 
-#warning The interrupt disable mask is now stored in SPRG0, please verify that this is compatible to this BSP (see also bootcard.c).
+#define SHOW_MORE_INIT_SETTINGS
 
 #include <string.h>
 
@@ -33,6 +33,7 @@
 #include <libcpu/cpuIdent.h>
 #include <bsp/vectors.h>
 #include <rtems/powerpc/powerpc.h>
+#include <bsp/ppc_exc_bspsupp.h>
 
 extern unsigned long __rtems_end[];
 extern void L1_caches_enables(void);
@@ -93,6 +94,13 @@ uint32_t VME_Slot1 = FALSE;
 extern int   RAM_END;  
 unsigned int BSP_mem_size = (unsigned int)&RAM_END;
 
+/*
+ * Where the heap starts; is used by bsp_pretasking_hook;
+ */
+unsigned int BSP_heap_start;
+uint32_t BSP_intrStackStart;
+uint32_t BSP_intrStackSize;
+
 /*
  * PCI Bus Frequency
  */
@@ -105,13 +113,15 @@ unsigned int BSP_processor_frequency;
 
 /*
  * Time base divisior (how many tick for 1 second).
+ * Calibrated by outputing a 20 ms pulse.
  */
-unsigned int BSP_time_base_divisor = 1000;  /* XXX - Just a guess */
+unsigned int BSP_time_base_divisor = 1320;  
 
 /*
  * system init stack 
  */
-#define INIT_STACK_SIZE 0x1000
+#define INIT_STACK_SIZE 0x2000
+#define INTR_STACK_SIZE rtems_configuration_get_interrupt_stack_size()
 
 void BSP_panic(char *s)
 {
@@ -170,6 +180,38 @@ void BSP_FLASH_set_page(
  
 void bsp_libc_init( void *, uint32_t, int );
 
+
+void ShowMemoryLayout(){
+  extern unsigned long __bss_start[], __SBSS_START__[], __SBSS_END__[];
+  extern unsigned long __SBSS2_START__[], __SBSS2_END__[];
+  extern unsigned long __bss_start[];
+  extern unsigned long __bss_end[];
+  extern unsigned long __stack[];
+  extern unsigned long __stackLow[];
+  extern uint32_t end;
+  /* extern uint32_t BSP_intrStackStart; */
+  /* extern uint32_t BSP_intrStackSize; */
+  /* Configuration.work_space_start     */
+  /* rtems_configuration_get_work_space_size() */
+  printk(" bss start: 0x%x\n", __bss_start);
+  printk(" bss end: 0x%x\n",  __bss_end);
+  printk(" rtems end: 0x%x\n",  __rtems_end);
+  printk(" stack    : 0x%x\n",  __stack);
+  printk(" stack Low: 0x%x\n",  __stackLow);
+  printk(" end      : 0x%x\n",  &end);
+  printk(" Intr Stack: 0x%x\n", BSP_intrStackStart);
+  printk(" Intr Stack Size: 0x%x\n", BSP_intrStackSize);
+  printk(" Heap start: %x\n", BSP_heap_start);
+
+  printk(" workspace start: 0x%x\n", Configuration.work_space_start);
+  printk(" workspace size: 0x%x\n", rtems_configuration_get_work_space_size() );
+
+}
+
+
+
+
+
 /*
  *  Function:   bsp_pretasking_hook
  *  Created:    95/03/10
@@ -186,28 +228,30 @@ void bsp_libc_init( void *, uint32_t, int );
  
 void bsp_pretasking_hook(void)
 {
-  uint32_t        heap_start;    
+  uint32_t        heap_start = BSP_heap_start;    
   uint32_t        heap_size;
   uint32_t        heap_sbrk_spared;
-
   extern uint32_t _bsp_sbrk_init(uint32_t, uint32_t*);
-  
-  heap_start = ((uint32_t) __rtems_end) +
-    INIT_STACK_SIZE + rtems_configuration_get_interrupt_stack_size();
-  if (heap_start & (CPU_ALIGNMENT-1))
-    heap_start = (heap_start + CPU_ALIGNMENT) & ~(CPU_ALIGNMENT-1);
+  extern uint32_t end;
 
-  heap_size = (BSP_mem_size - heap_start) - rtems_configuration_get_work_space_size();
+  heap_start = (BSP_heap_start + CPU_ALIGNMENT - 1) & ~(CPU_ALIGNMENT-1);
+  heap_size = (uint32_t) &RAM_END;
+  heap_size = heap_size - heap_start - Configuration.work_space_size;
+  heap_size &= 0xfffffff0;  /* keep it as a multiple of 16 bytes */
 
-  heap_sbrk_spared=_bsp_sbrk_init(heap_start, &heap_size);
+#if 0  /*XXXXXXX */
+    heap_size = Configuration.work_space_start - (void *)&end;
+    heap_size &= 0xfffffff0;  /* keep it as a multiple of 16 bytes */
+#endif
 
 #ifdef SHOW_MORE_INIT_SETTINGS
-  printk(" HEAP start %x  size %x (%x bytes spared for sbrk)\n", 
-    heap_start, heap_size, heap_sbrk_spared);
+  printk(" HEAP start 0x%x  size %x \n", 
+    heap_start, heap_size, 0 );
 #endif    
 
-  bsp_libc_init((void *) 0, heap_size, heap_sbrk_spared);
+  bsp_libc_init((void *)heap_start, heap_size, 0);
   rsPMCQ1Init();
+  ShowMemoryLayout();
 }
 
 void zero_bss()
@@ -232,21 +276,8 @@ void save_boot_params(RESIDUAL* r3, void *r4, void* r5, char *additional_boot_op
 unsigned int EUMBBAR;
 
 unsigned int get_eumbbar() {
-  register int a, e;
-
-  asm volatile( "lis %0,0xfec0; ori  %0,%0,0x0000": "=r" (a) );
-  asm volatile("sync");
-                                                                
-  asm volatile("lis %0,0x8000; ori %0,%0,0x0078": "=r"(e) ); 
-  asm volatile("stwbrx  %0,0x0,%1": "=r"(e): "r"(a));  
-  asm volatile("sync");
-
-  asm volatile("lis %0,0xfee0; ori %0,%0,0x0000": "=r" (a) ); 
-  asm volatile("sync");
-                                                         
-  asm volatile("lwbrx %0,0x0,%1": "=r" (e): "r" (a));
-  asm volatile("isync");
-  return e;
+  out_le32( (uint32_t*)0xfec00000, 0x80000078 );
+  return in_le32( (uint32_t*)0xfee00000 );
 }
 
 void Read_ep1a_config_registers( ppc_cpu_id_t myCpu ) {
@@ -317,6 +348,7 @@ void Read_ep1a_config_registers( ppc_cpu_id_t myCpu ) {
       BSP_bus_frequency       =  33000000;
       break;
   }
+  printk("Processor Frequency %d  Bus Frequency: %d\n", BSP_processor_frequency, BSP_bus_frequency );
 }
 
 /*
@@ -328,8 +360,6 @@ void Read_ep1a_config_registers( ppc_cpu_id_t myCpu ) {
 void bsp_start( void )
 {
   unsigned char *stack;
-  uint32_t intrStackStart;
-  uint32_t intrStackSize;
   unsigned char *work_space_start;
   ppc_cpu_id_t myCpu;
   ppc_cpu_revision_t myCpuRevision;
@@ -346,15 +376,22 @@ void bsp_start( void )
   EUMBBAR = get_eumbbar(); 
   printk("EUMBBAR 0x%08x\n", EUMBBAR );
 
+  /*
+   * Init MMU block address translation to enable hardware
+   * access
+   */
+  setdbat(1, 0xf0000000, 0xf0000000, 0x10000000, IO_PAGE);
+  setdbat(2, 0x80000000, 0x80000000, 0x10000000, IO_PAGE);
+  setdbat(3, 0x90000000, 0x90000000, 0x10000000, IO_PAGE);
+ShowBATS();
+
   /* 
    * Note this sets BSP_processor_frequency based upon register settings.
    * It must be done prior to setting up hooks.
    */
   Read_ep1a_config_registers( myCpu );
-
   bsp_clicks_per_usec = BSP_processor_frequency/(BSP_time_base_divisor * 1000);
 
-ShowBATS();
 #if 0   /* XXX - Add back in cache enable when we get this up and running!! */
   /*
    * enables L1 Cache. Note that the L1_caches_enables() codes checks for
@@ -363,41 +400,35 @@ ShowBATS();
   L1_caches_enables();
 #endif
 
-  /*
-   * the initial stack  has aready been set to this value in start.S
-   * so there is no need to set it in r1 again... It is just for info
-   * so that It can be printed without accessing R1.
-   */
-  stack = ((unsigned char*) __rtems_end) + INIT_STACK_SIZE - PPC_MINIMUM_STACK_FRAME_SIZE;
-
- /* tag the bottom (T. Straumann 6/36/2001 <strauman@slac.stanford.edu>) */
-  *((uint32_t *)stack) = 0;
-
   /*
    * Initialize the interrupt related settings.
    */
-  intrStackStart = (uint32_t) __rtems_end + INIT_STACK_SIZE;
-  intrStackSize = rtems_configuration_get_interrupt_stack_size();
+  BSP_intrStackStart = (uint32_t) __rtems_end + INIT_STACK_SIZE;
+  BSP_intrStackSize = rtems_configuration_get_interrupt_stack_size();
+  BSP_heap_start = BSP_intrStackStart + BSP_intrStackSize;
+  printk("Interrupt Stack Start: 0x%x Size: 0x%x  Heap Start: 0x%x\n",
+    BSP_intrStackStart, BSP_intrStackSize, BSP_heap_start
+  );
+
+  /* tag the bottom (T. Straumann 6/36/2001 <strauman@slac.stanford.edu>) */
+  *((uint32_t *)BSP_intrStackStart) = 0;
 
   /*
    * Initialize default raw exception hanlders.
    */
-  ppc_exc_initialize(
-    PPC_INTERRUPT_DISABLE_MASK_DEFAULT,
-    intrStackStart,
-    intrStackSize
-  );
-
-  /*
-   * Init MMU block address translation to enable hardware
-   * access
-   */
-  setdbat(1, 0xf0000000, 0xf0000000, 0x10000000, IO_PAGE);
-  setdbat(3, 0x90000000, 0x90000000, 0x10000000, IO_PAGE);
-
 
 #ifdef SHOW_MORE_INIT_SETTINGS
-  printk("Going to start PCI buses scanning and initialization\n");
+  printk("bsp_start: Initialize Exceptions\n");
+#endif  
+  ppc_exc_cache_wb_check = 0; 
+  ppc_exc_initialize(
+    PPC_INTERRUPT_DISABLE_MASK_DEFAULT,
+    BSP_intrStackStart,
+    BSP_intrStackSize
+  );
+
+#ifdef SHOW_MORE_INIT_SETTINGS
+  printk("bsp_start: Going to start PCI buses scanning and initialization\n");
 #endif  
   pci_initialize();
 
@@ -405,7 +436,7 @@ ShowBATS();
   printk("Number of PCI buses found is : %d\n", pci_bus_count());
 #endif
 #ifdef TEST_RAW_EXCEPTION_CODE  
-  printk("Testing exception handling Part 1\n");
+  printk("bsp_start: Testing exception handling Part 1\n");
 
   /*
    * Cause a software exception
@@ -415,28 +446,45 @@ ShowBATS();
   /*
    * Check we can still catch exceptions and returned coorectly.
    */
-  printk("Testing exception handling Part 2\n");
+  printk("bsp_start: Testing exception handling Part 2\n");
   __asm__ __volatile ("sc");
 #endif  
 
 #ifdef SHOW_MORE_INIT_SETTINGS
-  printk("rtems_configuration_get_work_space_size() = %x\n", 
+  printk("bsp_start: rtems_configuration_get_work_space_size() = %x\n", 
      rtems_configuration_get_work_space_size());
 #endif  
   work_space_start = 
-    (unsigned char *)BSP_mem_size - rtems_configuration_get_work_space_size();
-
+    (unsigned char *)&RAM_END - rtems_configuration_get_work_space_size();
   if ( work_space_start <= ((unsigned char *)__rtems_end) + 
         INIT_STACK_SIZE + rtems_configuration_get_interrupt_stack_size()) {
     printk( "bspstart: Not enough RAM!!!\n" );
     bsp_cleanup();
   }
-
   Configuration.work_space_start = work_space_start;
+#ifdef SHOW_MORE_INIT_SETTINGS
+  printk("bsp_start: workspace_start = 0x%x\n", 
+     work_space_start);
+#endif  
+
+  #if ( PPC_USE_DATA_CACHE )
+    #if DEBUG
+      printk("bsp_start: cache_enable\n");
+    #endif
+    instruction_cache_enable ();
+    data_cache_enable ();
+    #if DEBUG
+      printk("bsp_start: END PPC_USE_DATA_CACHE\n");
+    #endif
+  #endif
+
 
   /*
    * Initalize RTEMS IRQ system
    */
+#ifdef  SHOW_MORE_INIT_SETTINGS
+    printk("bspstart: Call BSP_rtems_irq_mng_init\n");
+#endif
   BSP_rtems_irq_mng_init(0);
   
   /* Activate the page table mappings only after
@@ -445,7 +493,7 @@ ShowBATS();
    */           
   if (pt) {
 #ifdef  SHOW_MORE_INIT_SETTINGS
-    printk("Page table setup finished; will activate it NOW...\n");
+    printk("bspstart: Page table setup finished; will activate it NOW...\n");
 #endif
     BSP_pgtbl_activate(pt);
   }
@@ -455,7 +503,7 @@ ShowBATS();
    * and IRQ subsystems...
    */
 #ifdef SHOW_MORE_INIT_SETTINGS
-  printk("Going to initialize VME bridge\n");
+  printk("bspstart: Going to initialize VME bridge\n");
 #endif
   /* VME initialization is in a separate file so apps which don't use
    * VME or want a different configuration may link against a customized

c/src/lib/libbsp/powerpc/ep1a/startup/linkcmds

@@ -152,7 +152,9 @@ SECTIONS
    *(COMMON)
    PROVIDE (__bss_end = .);
   }
-  . =  ALIGN(8) + 0x8000;
+  . =  ALIGN(0x100);
+  PROVIDE (__stackLow = .);
+  . += 0x8000;
   PROVIDE (__stack = .);
   _end = . ;
   __rtems_end = . ;

c/src/lib/libbsp/powerpc/ep1a/vme/VMEConfig.h

@@ -77,7 +77,8 @@
  * at _VME_DRAM_OFFSET
  */
 #undef  _VME_DRAM_OFFSET
-#define _VME_DRAM_OFFSET                0xc0000000  
+/* #define _VME_DRAM_OFFSET                0xc0000000   */
+
 #define _VME_DRAM_32_OFFSET1		0x20000000
 #define _VME_DRAM_32_OFFSET2            0x20b00000
 #define _VME_DRAM_24_OFFSET1            0x00000000

c/src/lib/libbsp/powerpc/ep1a/vme/vmeconfig.c

@@ -0,0 +1,144 @@
+/* $Id$ */
+
+/* Default VME bridge configuration - note that this file
+ * is independent of the bridge driver/chip
+ */
+
+/* 
+ * Authorship
+ * ----------
+ * This software was created by
+ *     Till Straumann <strauman@slac.stanford.edu>, 3/2002,
+ * 	   Stanford Linear Accelerator Center, Stanford University.
+ * 
+ * Acknowledgement of sponsorship
+ * ------------------------------
+ * This software was produced by
+ *     the Stanford Linear Accelerator Center, Stanford University,
+ * 	   under Contract DE-AC03-76SFO0515 with the Department of Energy.
+ * 
+ * Government disclaimer of liability
+ * ----------------------------------
+ * Neither the United States nor the United States Department of Energy,
+ * nor any of their employees, makes any warranty, express or implied, or
+ * assumes any legal liability or responsibility for the accuracy,
+ * completeness, or usefulness of any data, apparatus, product, or process
+ * disclosed, or represents that its use would not infringe privately owned
+ * rights.
+ * 
+ * Stanford disclaimer of liability
+ * --------------------------------
+ * Stanford University makes no representations or warranties, express or
+ * implied, nor assumes any liability for the use of this software.
+ * 
+ * Stanford disclaimer of copyright
+ * --------------------------------
+ * Stanford University, owner of the copyright, hereby disclaims its
+ * copyright and all other rights in this software.  Hence, anyone may
+ * freely use it for any purpose without restriction.  
+ * 
+ * Maintenance of notices
+ * ----------------------
+ * In the interest of clarity regarding the origin and status of this
+ * SLAC software, this and all the preceding Stanford University notices
+ * are to remain affixed to any copy or derivative of this software made
+ * or distributed by the recipient and are to be affixed to any copy of
+ * software made or distributed by the recipient that contains a copy or
+ * derivative of this software.
+ * 
+ * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03
+ */ 
+
+#include <bsp.h>
+#include <bsp/VME.h>
+#include <bsp/VMEConfig.h>
+#ifdef BSP_VME_BAT_IDX
+#include <libcpu/bat.h>
+#endif
+#include <rtems/bspIo.h>
+
+extern int BSP_VMEInit(void);
+extern int BSP_VMEIrqMgrInstall(void);
+
+/* Use a weak alias for the VME configuration.
+ * This permits individual applications to override
+ * this routine.
+ * They may even create an 'empty'
+ *
+ *    void BSP_vme_config(void) {}
+ *
+ * which will avoid linking in the Universe driver
+ * at all :-).
+ */
+
+void BSP_vme_config(void) 
+     __attribute__ (( weak, alias("__BSP_EP1A_vme_config") ));
+
+void __BSP_EP1A_vme_config(void)
+{
+  if ( BSP_VMEInit() ) {
+	printk("Skipping VME initialization...\n");
+	return;
+  }
+
+#ifdef BSP_VME_BAT_IDX
+  printk("BSP_VME_BAT_IDX\n");
+  /* setup a PCI area to map the VME bus */
+  setdbat(BSP_VME_BAT_IDX,
+		  PCI_MEM_BASE + _VME_A32_WIN0_ON_PCI,
+		  PCI_MEM_BASE + _VME_A32_WIN0_ON_PCI,
+		  0x10000000,
+		  IO_PAGE);
+#endif
+
+  /* map VME address ranges */
+  BSP_VMEOutboundPortCfg(
+	0,
+	VME_AM_EXT_SUP_DATA,
+	_VME_A32_WIN0_ON_VME,
+	_VME_A32_WIN0_ON_PCI,
+	0x0f000000);
+  BSP_VMEOutboundPortCfg(
+	1,
+	VME_AM_STD_SUP_DATA,
+	0x00000000,
+	_VME_A24_ON_PCI,
+	0x00ff0000);
+  BSP_VMEOutboundPortCfg(
+	2,
+	VME_AM_SUP_SHORT_IO,
+	0x00000000,
+	_VME_A16_ON_PCI,
+	0x00010000);
+
+#ifdef _VME_CSR_ON_PCI
+  /* Map VME64 CSR */
+  printk("_VME_CSR_ON_PCI\n");
+  BSP_VMEOutboundPortCfg(
+		  7,
+		  VME_AM_CSR,
+		  0,
+		  _VME_CSR_ON_PCI,
+		  0x01000000);
+#endif
+
+
+#ifdef _VME_DRAM_OFFSET
+  printk("_VME_DRAM_OFFSET");
+  /* map our memory to VME giving the driver a hint that it's ordinary memory
+   * so they can enable decoupled cycles which should give better performance...
+   */
+  BSP_VMEInboundPortCfg(
+	0,
+	VME_AM_EXT_SUP_DATA | VME_AM_IS_MEMORY,
+	_VME_DRAM_OFFSET,
+	PCI_DRAM_OFFSET,
+	BSP_mem_size);
+#endif
+
+  /* stdio is not yet initialized; the driver will revert to printk */
+  BSP_VMEOutboundPortsShow(0);
+  BSP_VMEInboundPortsShow(0);
+
+  BSP_VMEIrqMgrInstall();
+}

c/src/lib/libbsp/powerpc/gen5200/ChangeLog

@@ -1,3 +1,9 @@
+2010-03-10	Joel Sherrill <joel.sherrill@oarcorp.com>
+
+	PR 1497/bsps
+	* startup/bspclean.c: Do not enable interrupts while waiting for board
+	to reset.
+
 2008-12-08	Ralf Corsépius <ralf.corsepius@rtems.org>
 
 	* bsp_specs: Backport from CVS-HEAD.

c/src/lib/libbsp/powerpc/gen5200/network_5200/network.c

@@ -466,12 +466,12 @@ int mpc5200_eth_mii_read(struct mpc5200_enet_struct *sc, unsigned char phyAddr,
  *				18-wire ethernet tranceiver (PHY). Please see your PHY
  *				documentation for the register map.
  *
- * Returns:		Success (boolean)
+ * Returns:		Success (bool)
  *
  * Notes:
  *
  */
-static int mpc5200_eth_mii_write(struct mpc5200_enet_struct *sc, unsigned char phyAddr, unsigned char regAddr, unsigned short data)
+static bool mpc5200_eth_mii_write(struct mpc5200_enet_struct *sc, unsigned char phyAddr, unsigned char regAddr, unsigned short data)
   {
   unsigned long reg;					/* convenient holder for the PHY register */
   unsigned long phy;					/* convenient holder for the PHY */
@@ -514,12 +514,12 @@ static int mpc5200_eth_mii_write(struct mpc5200_enet_struct *sc, unsigned char p
  * Description:	Reset a running ethernet driver including the hardware
  *				FIFOs and the FEC.
  *
- * Returns:		Success (boolean)
+ * Returns:		Success (bool)
  *
  * Notes:
  *
  */
-static int mpc5200_fec_reset(struct mpc5200_enet_struct *sc) {
+static bool mpc5200_fec_reset(struct mpc5200_enet_struct *sc) {
   volatile int delay;
   /*
    * Clear FIFO status registers

c/src/lib/libbsp/powerpc/gen5200/startup/bspclean.c

@@ -45,9 +45,9 @@ void bsp_cleanup( void )
     /*
      * Now reset the CPU
      */
-    _ISR_Set_level( 0 );
-
     mpc5200.gpt[0].count_in = 0xf;
     mpc5200.gpt[0].emsel = 0x9004;
+
+    while(1) ;
   #endif 
 }

c/src/lib/libbsp/powerpc/gen83xx/ChangeLog

@@ -1,3 +1,8 @@
+2009-03-18	Thomas Doerfler <Thomas.Doerfler@embedded-brains.de>
+
+	* start/start.S, include/hwreg_vals.h, startup/cpuinit.c:
+	correct some init values for HSC_CM01 boards
+
 2008-12-08	Ralf Corsépius <ralf.corsepius@rtems.org>
 
 	* bsp_specs: Backport from CVS-HEAD.

c/src/lib/libbsp/powerpc/gen83xx/include/hwreg_vals.h

@@ -207,26 +207,26 @@
 #define LBLAWBAR0_VAL  bsp_rom_start
 #define LBLAWAR0_VAL   0x80000018
 #define LBLAWBAR1_VAL  (FPGA_CONFIG_START)
-#define LBLAWAR1_VAL   0x80000015
+#define LBLAWAR1_VAL   0x80000018
 #define DDRLAWBAR0_VAL bsp_ram_start
 #define DDRLAWAR0_VAL  0x8000001B
 /*
  * Local Bus (Memory) Controller
  * FIXME: decode bit settings 
  */
-#define BR0_VAL 0xFE001001
+#define BR0_VAL (0xFE000000 | 0x01001)
 #define OR0_VAL 0xFE000E54
 // fpga config access range (UPM_A) (32 kByte)
 #define BR2_VAL (FPGA_CONFIG_START | 0x01881)
-#define OR2_VAL 0xFFF80100
+#define OR2_VAL 0xFFFF9100
 
 // fpga register access range (UPM_B) (8 MByte)
 #define BR3_VAL (FPGA_REGISTER_START | 0x018A1)
-#define OR3_VAL 0xFF800100
+#define OR3_VAL 0xFF801100
 
-// fpga fifo access range (UPM_B) (8 MByte)
-#define BR4_VAL (FPGA_FIFO_START | 0x018A1)
-#define OR4_VAL 0xFF800100
+// fpga fifo access range (UPM_C) (8 MByte)
+#define BR4_VAL (FPGA_FIFO_START | 0x018C1)
+#define OR4_VAL 0xFF801100
 
 /*
  * SDRAM registers

c/src/lib/libbsp/powerpc/gen83xx/start/start.S

@@ -199,7 +199,18 @@ start_code_in_rom:
 #ifdef OR3_VAL
 	SET_IMM_REGW r31,r30,OR3_OFF,OR3_VAL
 #endif
-	
+#ifdef BR4_VAL
+	SET_IMM_REGW r31,r30,BR4_OFF,BR4_VAL
+#endif
+#ifdef OR4_VAL
+	SET_IMM_REGW r31,r30,OR4_OFF,OR4_VAL
+#endif
+#ifdef BR5_VAL
+	SET_IMM_REGW r31,r30,BR5_OFF,BR5_VAL
+#endif
+#ifdef OR5_VAL
+	SET_IMM_REGW r31,r30,OR5_OFF,OR5_VAL
+#endif
 	/*
 	 * ROM startup: init SDRAM access window
 	 */

c/src/lib/libbsp/powerpc/gen83xx/startup/cpuinit.c

@@ -235,7 +235,7 @@ void cpu_init( void)
       (uint32_t) bsp_rom_start,
       (uint32_t) bsp_rom_size,
     #endif /* HAS_UBOOT */
-    false,
+    true,
     false,
     false,
     false,

c/src/lib/libbsp/powerpc/haleakala/ChangeLog

@@ -1,3 +1,8 @@
+2008-12-18	Michael Hamel <nigel@adi.co.nz>
+
+	PR 1349/bsps
+	* startup/bspstart.c: Add missing volatile on UART access pointer.
+
 2008-09-29	Ralf Corsépius <ralf.corsepius@rtems.org>
 
 	* Makefile.am: Remove noinst_PROGRAMS (Unused).

c/src/lib/libbsp/powerpc/haleakala/startup/bspstart.c

@@ -143,7 +143,7 @@ void bsp_pretasking_hook(void)
 static void
 EarlyUARTInit(int baudRate)
 {
-	uint8_t* up = (uint8_t*)(BSP_UART_IOBASE_COM1);
+	volatile uint8_t* up = (uint8_t*)(BSP_UART_IOBASE_COM1);
 	int divider = BSP_UART_BAUD_BASE / baudRate;
 	up[LCR] = DLAB;		/* Access DLM/DLL */
 	up[DLL] = divider & 0x0FF;
@@ -206,7 +206,7 @@ void Init_FPGA(void)
 static void
 DirectUARTWrite(const char c)
 {
-	uint8_t* up = (uint8_t*)(BSP_UART_IOBASE_COM1);
+	volatile uint8_t* up = (uint8_t*)(BSP_UART_IOBASE_COM1);
 	while ((up[LSR] & THRE) == 0) { ; }
 	up[THR] = c;
 	if (c=='\n')

c/src/lib/libbsp/powerpc/mbx8xx/ChangeLog

@@ -1,3 +1,12 @@
+2009-03-12	Joel Sherrill <joel.sherrill@OARcorp.com>
+
+	PR 1385/cpukit
+	* irq/irq_asm.S: When the type rtems_boolean was switched to the C99
+	bool, the size changed from 4 bytes to 1 byte. The interrupt
+	dispatching code accesses two boolean variables for scheduling
+	purposes and the assembly implementations of this code did not get
+	updated.
+
 2008-12-08	Ralf Corsépius <ralf.corsepius@rtems.org>
 
 	* bsp_specs: Backport from CVS-HEAD.

c/src/lib/libbsp/powerpc/mbx8xx/irq/irq_asm.S

@@ -268,16 +268,16 @@ nested:
 	 * do something with the current thread...
 	 */
 	addis	r4, 0, _Context_Switch_necessary@ha
-	lwz	r5, _Context_Switch_necessary@l(r4)
+	lbz	r5, _Context_Switch_necessary@l(r4)
 	cmpwi	r5, 0
 	bne	switch
 
 	addis	r6, 0, _ISR_Signals_to_thread_executing@ha
-	lwz	r7, _ISR_Signals_to_thread_executing@l(r6)
+	lbz	r7, _ISR_Signals_to_thread_executing@l(r6)
 	cmpwi	r7, 0
 	li	r8, 0
 	beq	easy_exit
-	stw	r8, _ISR_Signals_to_thread_executing@l(r6)
+	stb	r8, _ISR_Signals_to_thread_executing@l(r6)
 	/*
 	 * going to call _ThreadProcessSignalsFromIrq
 	 * Push a complete exception like frame...

c/src/lib/libbsp/powerpc/mpc8260ads/ChangeLog

@@ -1,3 +1,16 @@
+2009-03-12	Joel Sherrill <joel.sherrill@OARcorp.com>
+
+	PR 1385/cpukit
+	* irq/irq_asm.S: When the type rtems_boolean was switched to the C99
+	bool, the size changed from 4 bytes to 1 byte. The interrupt
+	dispatching code accesses two boolean variables for scheduling
+	purposes and the assembly implementations of this code did not get
+	updated.
+
+2009-03-09	Joel Sherrill <joel.sherrill@OARcorp.com>
+
+	* include/tm27.h: Add include rtems/powerpc/powerpc.h
+
 2008-12-08	Ralf Corsépius <ralf.corsepius@rtems.org>
 
 	* bsp_specs: Backport from CVS-HEAD.

c/src/lib/libbsp/powerpc/mpc8260ads/include/tm27.h

@@ -15,6 +15,8 @@
 #ifndef __tm27_h
 #define __tm27_h
 
+#include <rtems/powerpc/powerpc.h>
+
 /*
  *  Stuff for Time Test 27
  */

c/src/lib/libbsp/powerpc/mpc8260ads/irq/irq_asm.S

@@ -226,16 +226,16 @@ nested:
 	 * do something with the current thread...
 	 */
 	addis	r4, 0, _Context_Switch_necessary@ha
-	lwz		r5, _Context_Switch_necessary@l(r4)
+	lbz		r5, _Context_Switch_necessary@l(r4)
 	cmpwi	r5, 0
 	bne		switch
 
 	addis	r6, 0, _ISR_Signals_to_thread_executing@ha
-	lwz		r7, _ISR_Signals_to_thread_executing@l(r6)
+	lbz		r7, _ISR_Signals_to_thread_executing@l(r6)
 	cmpwi	r7, 0
 	li		r8, 0
 	beq		easy_exit
-	stw		r8, _ISR_Signals_to_thread_executing@l(r6)
+	stb		r8, _ISR_Signals_to_thread_executing@l(r6)
 	/*
 	 * going to call _ThreadProcessSignalsFromIrq
 	 * Push a complete exception like frame...

c/src/lib/libbsp/powerpc/mvme3100/ChangeLog

@@ -1,3 +1,42 @@
+2009-10-20	Till Straumann <strauman@slac.stanford.edu>
+
+	* network/tsec.c: Bugfix. Broadcast address was declared
+	uint8_t instead of uint8_t [8].
+
+2009-10-13	Till Straumann <strauman@slac.stanford.edu>
+
+	PR 1451/bsps
+	* network/tsec.c: Fix mbuf leak when watchdog expires. The
+	re-initialization algorithm failed to release mbuf chains
+	held in the TX ring.
+	Also, during initialization the initial link status is determined
+	and IFF_OACTIVE set if no active link was detected.
+
+2009-08-17	Till Straumann <strauman@slac.stanford.edu>
+
+	* network/tsec.c, network/if_tsec_pub.h:
+	Fixed bugs in multicast support; added reference-count
+	for hash-table entries which allows for the implementation
+	of a 'deletion' routine.
+	NOTE: mcast support largely untested.
+
+2009-06-05	Till Straumann <strauman@slac.stanford.edu>
+
+	* irq/irq_init.c: silenced compiler warning.
+
+2009-06-05	Till Straumann <strauman@slac.stanford.edu>
+
+	* network/tsec.c, network/if_tsec_pub.h:
+	implemented multicast support.
+
+2009-03-05	Till Straumann <strauman@slac.stanford.edu>
+
+	* startup/bspstart.c: removed legacy code (inherited
+	from old mvme2307 BSP) -- for testing trapping into
+	PPCBug -- which is irrelevant on this BSP.
+	Removed warning about SPRG0 having been reassigned
+	-- this BSP is OK.
+
 2008-12-08	Ralf Corsépius <ralf.corsepius@rtems.org>
 
 	* bsp_specs: Backport from CVS-HEAD.

c/src/lib/libbsp/powerpc/mvme3100/include/.cvsignore

@@ -0,0 +1,4 @@
+stamp-h
+stamp-h.in
+bspopts.h
+bspopts.h.in

c/src/lib/libbsp/powerpc/mvme3100/irq/irq_init.c

@@ -28,7 +28,7 @@
 #include <libcpu/raw_exception.h>
 #include <rtems/bspIo.h>
 
-static void nop_func(void)
+static void nop_func(void *arg)
 {
 	printk("Unhandled IRQ\n");
 }

c/src/lib/libbsp/powerpc/mvme3100/network/if_tsec_pub.h

@@ -173,10 +173,60 @@ BSP_tsec_reset_stats(struct tsec_private *mp);
  * 'promisc'	whether to set promiscuous flag.
  * 'enaddr'		pointer to six bytes with MAC address. Read
  *				from the device if NULL.
+ * NOTE:        multicast filter is cleared by this routine.
  */
 void
 BSP_tsec_init_hw(struct tsec_private *mp, int promisc, unsigned char *enaddr);
 
+/*
+ * Clear multicast hash filter. No multicast frames are accepted
+ * after executing this routine (unless the hardware was initialized
+ * in 'promiscuous' mode).
+ *
+ * Reset reference count for all hash-table entries
+ * to zero (see BSP_tsec_mcast_filter_accept_del()).
+ */
+void
+BSP_tsec_mcast_filter_clear(struct tsec_private *mp);
+
+/*
+ * Program multicast filter to accept all multicast frames.
+ *
+ * Increment reference count for all hash-table entries
+ * by one (see BSP_tsec_mcast_filter_accept_del()).
+ */
+void
+BSP_tsec_mcast_filter_accept_all(struct tsec_private *mp);
+
+/*
+ * Add a MAC address to the multicast filter and increment
+ * the reference count for the matching hash-table entry
+ * (see BSP_tsec_mcast_filter_accept_del()).
+ * 
+ * Existing entries are not changed but note that
+ * the filter is imperfect, i.e., multiple MAC addresses
+ * may alias to a single filter entry. Hence software
+ * filtering must still be performed.
+ *
+ */
+void
+BSP_tsec_mcast_filter_accept_add(struct tsec_private *mp, unsigned char *enaddr);
+
+/*
+ * Remove a MAC address from the (imperfec) multicast
+ * filter.
+ * Note that the driver maintains an internal reference
+ * counter for each multicast hash. The hash-table
+ * entry is only cleared when the reference count
+ * reaches zero ('del' has been called the same
+ * amount of times as 'add' for an address (or
+ * any alias) that matches a given table entry.
+ * BSP_tsec_mcast_filter_clear() resets all reference
+ * counters to zero.
+ */
+void
+BSP_tsec_mcast_filter_accept_del(struct tsec_private *mp, unsigned char *enaddr);
+
 /*
  * Dump statistics to FILE 'f'. If NULL, stdout is used.
  */

c/src/lib/libbsp/powerpc/mvme3100/network/tsec.c

@@ -50,6 +50,7 @@
 #include <libcpu/byteorder.h>
 #include <inttypes.h>
 #include <stdio.h>
+#include <errno.h>
 #include <assert.h>
 #include <bsp.h>
 
@@ -113,6 +114,9 @@ phy_irq_pending(struct tsec_private *mp);
 static uint32_t
 phy_ack_irq(struct tsec_private *mp);
 
+static void
+tsec_update_mcast(struct ifnet *ifp);
+
 #if defined(PARANOIA) || defined(DEBUG)
 void tsec_dump_tring(struct tsec_private *mp);
 void tsec_dump_rring(struct tsec_private *mp);
@@ -636,6 +640,8 @@ static inline void bd_wrbuf(TSEC_BD *bd, uint32_t addr)
 
 /* Driver 'private' data */
 
+#define NUM_MC_HASHES		256
+
 struct tsec_private {
 	FEC_Enet_Base	base;            /* Controller base address                  */
 	FEC_Enet_Base	phy_base;        /* Phy base address (not necessarily identical
@@ -680,6 +686,7 @@ struct tsec_private {
 		unsigned	odrops;
 		unsigned	repack;
 	}               stats;
+	uint16_t		mc_refcnt[NUM_MC_HASHES];
 };
 
 #define NEXT_TXI(mp, i)	(((i)+1) < (mp)->tx_ring_size ? (i)+1 : 0 )
@@ -1212,7 +1219,7 @@ int i;
 static int
 mac_set_duplex(struct tsec_private *mp)
 {
-int media = 0;
+int media = IFM_MAKEWORD(0, 0, 0, 0);
 
 	if ( 0 == BSP_tsec_media_ioctl(mp, SIOCGIFMEDIA, &media)) {
 		if ( IFM_LINK_OK & media ) {
@@ -1339,9 +1346,10 @@ rtems_interrupt_level l;
 
 	for ( i=0; i<8*4; i+=4 ) {
 		fec_wr( b, TSEC_IADDR0 + i, 0 );
-		fec_wr( b, TSEC_GADDR0 + i, 0 );
 	}
 
+	BSP_tsec_mcast_filter_clear(mp);
+
 	BSP_tsec_reset_stats(mp);
 
 	fec_wr( b, TSEC_ATTR, (TSEC_ATTR_RDSEN | TSEC_ATTR_RBDSEN) );
@@ -1396,6 +1404,80 @@ rtems_interrupt_level l;
 	rtems_interrupt_enable( l );
 }
 
+static uint8_t
+hash_prog(struct tsec_private *mp, uint32_t tble, const uint8_t *enaddr, int accept)
+{
+uint8_t  s;
+uint32_t reg, bit;
+
+	s = ether_crc32_le(enaddr, ETHER_ADDR_LEN);
+
+	/* bit-reverse */
+    s = ((s&0x0f) << 4) | ((s&0xf0) >> 4);
+    s = ((s&0x33) << 2) | ((s&0xcc) >> 2);
+    s = ((s&0x55) << 1) | ((s&0xaa) >> 1);
+
+	reg = tble + ((s >> (5-2)) & ~3);
+	bit = 1 << (31 - (s & 31));
+
+	if ( accept ) {
+		if ( 0 == mp->mc_refcnt[s]++ )
+			fec_set( mp->base, reg, bit );
+	} else {
+		if ( mp->mc_refcnt[s] > 0 && 0 == --mp->mc_refcnt[s] )
+			fec_clr( mp->base, reg, bit );
+	}
+}
+
+void
+BSP_tsec_mcast_filter_clear(struct tsec_private *mp)
+{
+int i;
+	for ( i=0; i<8*4; i+=4 ) {
+		fec_wr( mp->base, TSEC_GADDR0 + i, 0 );
+	}
+	for ( i=0; i<NUM_MC_HASHES; i++ )
+		mp->mc_refcnt[i] = 0;
+}
+
+void
+BSP_tsec_mcast_filter_accept_all(struct tsec_private *mp)
+{
+int i;
+	for ( i=0; i<8*4; i+=4 ) {
+		fec_wr( mp->base, TSEC_GADDR0 + i, 0xffffffff );
+	}
+	for ( i=0; i<NUM_MC_HASHES; i++ )
+		mp->mc_refcnt[i]++;
+}
+
+static void
+mcast_filter_prog(struct tsec_private *mp, uint8_t *enaddr, int accept)
+{
+static const uint8_t bcst[6]={0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
+	if ( ! (enaddr[0] & 0x01) ) {
+		/* not a multicast address; ignore */
+		return;
+	}
+	if ( 0 == memcmp( enaddr, bcst, sizeof(bcst) ) ) {
+		/* broadcast; ignore */
+		return;
+	}
+	hash_prog(mp, TSEC_GADDR0, enaddr, accept);
+}
+
+void
+BSP_tsec_mcast_filter_accept_add(struct tsec_private *mp, uint8_t *enaddr)
+{
+	mcast_filter_prog(mp, enaddr, 1 /* accept */);
+}
+
+void
+BSP_tsec_mcast_filter_accept_del(struct tsec_private *mp, uint8_t *enaddr)
+{
+	mcast_filter_prog(mp, enaddr, 0 /* delete */);
+}
+
 void
 BSP_tsec_dump_stats(struct tsec_private *mp, FILE *f)
 {
@@ -2247,15 +2329,17 @@ unsigned long	l,o;
 static void consume_rx_mbuf(void *buf, void *arg, int len)
 {
 struct ifnet *ifp = arg;
+struct mbuf    *m = buf;
+
 	if ( len <= 0 ) {
 		ifp->if_iqdrops++;
 		if ( len < 0 ) {
 			ifp->if_ierrors++;
 		}
-		/* caller recycles mbuf */
+		if ( m )
+			m_freem(m);
 	} else {
 		struct ether_header *eh;
-		struct mbuf			*m = buf;
 
 			eh			= (struct ether_header *)(mtod(m, unsigned long) + ETH_RX_OFFSET);
 			m->m_len	= m->m_pkthdr.len = len - sizeof(struct ether_header) - ETH_RX_OFFSET - ETH_CRC_LEN;
@@ -2309,7 +2393,21 @@ tsec_init(void *arg)
 {
 struct tsec_softc	*sc  = arg;
 struct ifnet		*ifp = &sc->arpcom.ac_if;
+int                 media;
+
 	BSP_tsec_init_hw(&sc->pvt, ifp->if_flags & IFF_PROMISC, sc->arpcom.ac_enaddr);
+
+	/* Determine initial link status and block sender if there is no link */
+	media = IFM_MAKEWORD(0, 0, 0, 0);
+	if ( 0 == BSP_tsec_media_ioctl(&sc->pvt, SIOCGIFMEDIA, &media) ) {
+		if ( (IFM_LINK_OK & media) ) {
+			ifp->if_flags &= ~IFF_OACTIVE;
+		} else {
+			ifp->if_flags |=  IFF_OACTIVE;
+		}
+	}
+
+	tsec_update_mcast(ifp);
 	ifp->if_flags |= IFF_RUNNING;
 	sc->arpcom.ac_if.if_timer = 0;
 }
@@ -2348,6 +2446,31 @@ struct tsec_softc	*sc = ifp->if_softc;
 	tsec_start(ifp);
 }
 
+static void
+tsec_update_mcast(struct ifnet *ifp)
+{
+struct tsec_softc *sc = ifp->if_softc;
+struct ether_multi     *enm;
+struct ether_multistep step;
+
+	if ( IFF_ALLMULTI & ifp->if_flags ) {
+		BSP_tsec_mcast_filter_accept_all( &sc->pvt );
+	} else {
+		BSP_tsec_mcast_filter_clear( &sc->pvt );
+
+		ETHER_FIRST_MULTI(step, (struct arpcom *)ifp, enm);
+
+		while ( enm ) {
+			if ( memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN) )
+				assert( !"Should never get here; IFF_ALLMULTI should be set!" );
+
+			BSP_tsec_mcast_filter_accept_add(&sc->pvt, enm->enm_addrlo);
+
+			ETHER_NEXT_MULTI(step, enm);
+		}
+	}
+}
+
 /* bsdnet driver ioctl entry */
 static int
 tsec_ioctl(struct ifnet *ifp, ioctl_command_t cmd, caddr_t data)
@@ -2395,15 +2518,19 @@ int					f;
 			error = BSP_tsec_media_ioctl(&sc->pvt, cmd, &ifr->ifr_media);
 		break;
  
-/*
- * TODO
- *
- * 		case SIOCADDMULTI:
- * 		case SIOCDELMULTI:
- *
- *		break;
- */
+ 		case SIOCADDMULTI:
+ 		case SIOCDELMULTI:
+			error = (cmd == SIOCADDMULTI)
+		    		? ether_addmulti(ifr, &sc->arpcom)
+				    : ether_delmulti(ifr, &sc->arpcom);
 
+			if (error == ENETRESET) {
+				if (ifp->if_flags & IFF_RUNNING) {
+					tsec_update_mcast(ifp);
+				}
+				error = 0;
+			}
+		break;
 
  		case SIO_RTEMS_SHOW_STATS:
 			BSP_tsec_dump_stats( &sc->pvt, stdout );
@@ -2570,7 +2697,7 @@ struct	ifnet		*ifp;
 		ifp->if_timer			= 0;
 
 		sc->bsd.oif_flags		= /* ... */
-		ifp->if_flags			= IFF_BROADCAST | IFF_SIMPLEX;
+		ifp->if_flags			= IFF_BROADCAST | IFF_MULTICAST | IFF_SIMPLEX;
 
 		/*
 		 * if unset, this set to 10Mbps by ether_ifattach; seems to be unused by bsdnet stack;

c/src/lib/libbsp/powerpc/mvme3100/startup/bspstart.c

@@ -55,8 +55,6 @@ void bsp_cleanup(void)
     bsp_reset();
 }
 
-SPR_RW(SPRG1)
-
 /*
  * Copy Additional boot param passed by boot loader
  */
@@ -395,29 +393,6 @@ VpdBufRec          vpdData [] = {
 	}
 #endif
 
-#ifdef TEST_RAW_EXCEPTION_CODE
-	printk("Testing exception handling Part 1\n");
-	/*
-	 * Cause a software exception
-	 */
-	__asm__ __volatile ("sc");
-	/*
-	 * Check we can still catch exceptions and return coorectly.
-	 */
-	printk("Testing exception handling Part 2\n");
-	__asm__ __volatile ("sc");
-
-	/*
-	 * Somehow doing the above seems to clobber SPRG0 on the mvme2100.  The
-	 * interrupt disable mask is stored in SPRG0. Is this a problem?
-	 */
-	ppc_interrupt_set_disable_mask( PPC_INTERRUPT_DISABLE_MASK_DEFAULT);
-
-#endif
-
-/* See above */
-#warning The interrupt disable mask is now stored in SPRG0, please verify that this is compatible to this BSP (see also bootcard.c).
-
 	if ( (chpt = strstr(BSP_commandline_string,"MEMSZ=")) ) {
 		char		*endp;
 		uint32_t 	sz;

c/src/lib/libbsp/powerpc/mvme5500/ChangeLog

@@ -1,3 +1,25 @@
+2009-05-08	Joel Sherrill <joel.sherrill@oarcorp.com>
+
+	* irq/irq.c, network/if_1GHz/POSSIBLEBUG: Removed.
+
+2009-05-08	Kate Feng <feng1@bnl.gov>
+
+	PR1395/bsps
+	* Updated the changes from RTEMS-4.8.0, which were made since Oct. 2007.
+	* network/if_1GHz/if_wm.c: fixed some bugs in the 1GHz driver.
+	* pci/pci_interface.c:
+	  + Enabled PCI "Read", "Read Line", and "Read Multiple"
+	  +  Agressive Prefetch to improve the performance of the PCI based
+	     applications (e.g. 1GHz NIC).
+	* irq/BSP_irq.c : Replaced the irq/irq.c, and used GT_GPP_Value
+	register to monitor the cause of the level sensitive interrupts.
+	This unique solution solves various bugs in the 1GHz network drivers
+	Fixed bugs in compute_pic_masks_from_prio()
+	* pci/pci.c : Updated it to be consistent with the original pci.c
+	* written by Eric Valette.  There is no change in its function.
+	* irq/irq_init.c : set defaultIrq->next_handler to be 0 
+	* for BSP_SHARED_HANDLER_SUPPORT.
+
 2008-12-08	Ralf Corsépius <ralf.corsepius@rtems.org>
 
 	* bsp_specs: Backport from CVS-HEAD.

c/src/lib/libbsp/powerpc/mvme5500/GT64260/VPD.h

@@ -5,7 +5,5 @@
  *
  */
 
-extern unsigned char ConfVPD_buff[200];
-
 #define VPD_ENET0_OFFSET  0x3c
 #define VPD_ENET1_OFFSET  0x45

c/src/lib/libbsp/powerpc/mvme5500/GT64260/gtreg.h

@@ -190,7 +190,7 @@
 #define GT_MPP_Control2			0xf008
 #define GT_MPP_Control3			0xf00c
 
-/* <skf> added */
+/* <skf> added for GT64260 */
 #define GT_MPP_SerialPortMultiplex      0xf010
 
 #define	GT_GPP_IO_Control		0xf100
@@ -789,14 +789,13 @@
 #define TWSI_BAUDE_RATE		0xc00c
 #define TWSI_SFT_RST		0xc01c
 
-/* Interrupt Controller - Interrupt Controller Registers */
 /* Section 25.2 : Table 734 <skf> */
 
-#define GT_MAIN_INT_CAUSE_LO	0xc18 /* read Only */
-#define GT_MAIN_INT_CAUSE_HI   0xc68 /* read Only */
-#define GT_CPU_INT_MASK_LO 	0xc1c
-#define GT_CPU_INT_MASK_HI	0xc6c
-#define GT_CPU_SEL_CAUSE	0xc70 /* read Only */
+#define GT64260_MAIN_INT_CAUSE_LO	0xc18 /* read Only */
+#define GT64260_MAIN_INT_CAUSE_HI       0xc68 /* read Only */
+#define GT64260_CPU_INT_MASK_LO 	0xc1c
+#define GT64260_CPU_INT_MASK_HI	        0xc6c
+#define GT64260_CPU_SEL_CAUSE	0xc70 /* read Only */
 #define GT_PCI0_INT_MASK_LO	0xc24
 #define GT_PCI0_INT_MASK_HI	0xc64
 #define GT_PCI0_SEL_CAUSE	0xc74 /* read Only */

c/src/lib/libbsp/powerpc/mvme5500/Makefile.am

@@ -32,7 +32,9 @@ startup_SOURCES = startup/bspstart.c \
     ../../powerpc/shared/startup/sbrk.c ../../shared/bootcard.c \
     ../../shared/bsppredriverhook.c startup/bspclean.c \
     ../../shared/bsplibc.c ../../shared/bsppost.c \
-    ../../shared/gnatinstallhandler.c startup/reboot.c
+    ../../shared/gnatinstallhandler.c startup/reboot.c \
+    ../../powerpc/shared/startup/probeMemEnd.c
+
 pclock_SOURCES = ../../powerpc/shared/clock/p_clock.c
 
 include_bsp_HEADERS = ../../powerpc/shared/console/uart.h
@@ -45,7 +47,7 @@ pci_SOURCES = pci/pci.c pci/pci_interface.c pci/detect_host_bridge.c \
     pci/pcifinddevice.c
 
 include_bsp_HEADERS += irq/irq.h
-irq_SOURCES = irq/irq_init.c irq/irq.c 
+irq_SOURCES = irq/irq_init.c irq/BSP_irq.c 
 
 nodist_include_HEADERS += ../../shared/tod.h
 tod_SOURCES = ../../shared/tod.c tod/todcfg.c

c/src/lib/libbsp/powerpc/mvme5500/README

@@ -1,5 +1,5 @@
 #
-#  $Id: README,v 1.3.1  Shuchen Kate Feng, NSLS, BNL (08/27/07)
+#  $Id: README,v 1.4.1  Shuchen Kate Feng, NSLS, BNL (03/16/2009)
 #
 
 Please reference README.booting for the boot/load process.
@@ -7,7 +7,10 @@ Please reference README.booting for the boot/load process.
 For the priority setting of the Interrupt Requests (IRQs), please
 reference README.irq 
 
-The BSP is built and tested on the 4.7.1 and 4.7.99.2 CVS RTEMS release.
+The BSP is built and tested on the RTEMS 4.9.1 release. The
+PR1385 patch for c/src/lib/libbsp/powerpc/shared/irq/irq_asm.S
+is not needed for the mvme5500 BSP because the PowerPC BSPs
+use the shared exception framework in the RTEMS 4.9 release.
 
 I believe in valuable real-time programming, where technical neatness,
 performance and truth are.  I hope I still believe. Any suggestion,

c/src/lib/libbsp/powerpc/mvme5500/README.booting

@@ -1,8 +1,9 @@
-README.booting: written by S. Kate Feng <feng1@bnl.gov>, Aug. 28, 2007
+README.booting: written by S. Kate Feng <feng1@bnl.gov>, March 16, 2009
 
-The bootloader is adapted from Till Straumann's Generic Mini-loader,
-which he wrote originally for the SVGM powerpc board. 
-The BSP is built and tested on the 4.7 CVS RTEMS release.
+The BSP is built and tested on the RTEMS 4.9.1 release. The
+PR1385 patch for c/src/lib/libbsp/powerpc/shared/irq/irq_asm.S
+is not needed for the mvme5500 BSP because the PowerPC BSPs
+use the shared exception framework in the RTEMS 4.9 release.
 
 Booting requirement :
 -------------------------
@@ -11,12 +12,7 @@ Booting requirement :
    or /etc/dhcpd.conf (DHCP) properly to boot the system.
    (Note : EPICS needs a NTP server).
  
-2) Please copy the prebuilt RTEMS binary (e.g. misc/rtems5500-cexp.bin)
-   and perhaps others (e.g. misc/st.sys) to the /tftpboot/epics/hostname/bin/
-   directory or the TFTPBOOT one you specified in the 'tftpGet'
-   command of the boot script (as shown in the following example).
-
-3) Example of the boot script setup carried out on the MOTLoad 
+2) Example of the boot script setup carried out on the MOTLoad 
    command line : 
 
 MVME5500> gevEdit mot-script-boot
@@ -32,23 +28,14 @@ MVME5500>
 Note : (cxx.xx.xx.xx is the client IP address and 
         sxx.xx.xx.xx is the server IP address)
 
-4) Other reference web sites for mvme5500 BSP:
-http://lansce.lanl.gov/EPICS/presentations/KateFeng%20RTEMS-mvme55001.ppt
+3) Other reference web sites for mvme5500 BSP:
 http://www.nsls.bnl.gov/facility/expsys/software/EPICS/
-http://www.nsls.bnl.gov/facility/expsys/software/EPICS/FAQ.txt
 
-5) When generating code (especially C++) for this system, one should
-   use at least gcc-3.2 (preferrably a copy downloaded from the RTEMS
-   site [snapshot area] )
 
-6) To reboot the RTEMS-MVME5500 (board reset), one can invoke the
+4) To reboot the RTEMS-MVME5500 (board reset), one can invoke the
    rtemsReboot() command at Cexp> prompt.
  
-7) Please reference http://www.slac.stanford.edu/~strauman/rtems
-for the source code and installation guidance of cexp, GeSys and
-other useful utilities such as telnet, nfs, and so on. 
-
-8) To get started with RTEMS/EPICS and to build development
+5) To get started with RTEMS/EPICS and to build development
 tools and BSP, I would recommend one to reference
 http://www.aps.anl.gov/epics/base/RTEMS/tutorial/
 in additional to the RTEMS document.

c/src/lib/libbsp/powerpc/mvme5500/include/bsp.h

@@ -7,7 +7,8 @@
  *  found in found in the file LICENSE in this distribution or at
  *  http://www.rtems.com/license/LICENSE.
  *
- *  S. Kate Feng 2003-2007 : Modified it to support the mvme5500 BSP.
+ *  (C) S. Kate Feng 2003-2007 : Modified it to support the mvme5500 BSP.
+ *
  *
  */
 
@@ -22,10 +23,57 @@
 #include <libcpu/io.h>
 #include <bsp/vectors.h>
 
-#include <bsp/bspMvme5500.h>
+/* Board type */
+typedef enum {
+	undefined = 0,
+	MVME5500,
+	MVME6100
+} BSP_BoardTypes;
+
+BSP_BoardTypes BSP_getBoardType();
+
+/* Board type */
+typedef enum {
+	Undefined,
+	UNIVERSE2,
+	TSI148,
+} BSP_VMEchipTypes;
+
+BSP_VMEchipTypes BSP_getVMEchipType();
+
+/* The version of Discovery system controller */
+
+typedef enum {
+	notdefined, 
+	GT64260A,
+	GT64260B,	    
+	MV64360,
+} DiscoveryChipVersion;
+
+DiscoveryChipVersion BSP_getDiscoveryChipVersion();
+
+#define _256M           0x10000000
+#define _512M           0x20000000
+
+#define GT64x60_REG_BASE	0xf1000000  /* Base of GT64260 Reg Space */
+#define GT64x60_REG_SPACE_SIZE	0x10000     /* 64Kb Internal Reg Space */
+
+#define GT64x60_DEV1_BASE       0xf1100000  /* Device bank1(chip select 1) base
+                                             */
+#define GT64260_DEV1_SIZE 	0x00100000 /* Device bank size */
 
 /* fundamental addresses for this BSP (PREPxxx are from libcpu/io.h) */
-#define _IO_BASE GT64260_REG_BASE
+#define _IO_BASE GT64x60_REG_BASE
+
+#define BSP_NVRAM_BASE_ADDR     0xf1110000
+
+#define BSP_RTC_INTA_REG        0x7ff0
+#define BSP_RTC_SECOND	        0x7ff2  
+#define BSP_RTC_MINUTE	        0x7ff3
+#define BSP_RTC_HOUR	        0x7ff4  
+#define BSP_RTC_DATE	        0x7ff5
+#define BSP_RTC_INTERRUPTS      0x7ff6
+#define BSP_RTC_WATCHDOG        0x7ff7
 
 /* PCI0 Domain I/O space */
 #define PCI0_IO_BASE            0xf0000000
@@ -69,17 +117,15 @@
  */
 
 #define CONFIGURE_NUMBER_OF_TERMIOS_PORTS 2
+#define BSP_INTERRUPT_STACK_SIZE  (16 * 1024) /* <skf> 2/09 wants it to be adjustable by BSP */
 
 /* uart.c uses out_8 instead of outb  */
-#define BSP_UART_IOBASE_COM1	GT64260_DEV1_BASE + 0x20000
-#define BSP_UART_IOBASE_COM2	GT64260_DEV1_BASE + 0x21000
+#define BSP_UART_IOBASE_COM1	GT64x60_DEV1_BASE + 0x20000
+#define BSP_UART_IOBASE_COM2	GT64x60_DEV1_BASE + 0x21000
 
 #define BSP_CONSOLE_PORT		BSP_UART_COM1  /* console */
 #define BSP_UART_BAUD_BASE		115200
 
-/*
- * Vital Board data Start using DATA RESIDUAL
- */
 /*
  * Total memory using RESIDUAL DATA
  */
@@ -100,6 +146,7 @@ extern unsigned int BSP_time_base_divisor;
 #define BSP_Convert_decrementer( _value ) \
   ((unsigned long long) ((((unsigned long long)BSP_time_base_divisor) * 1000000ULL) /((unsigned long long) BSP_bus_frequency)) * ((unsigned long long) (_value)))
 
+extern rtems_configuration_table  BSP_Configuration;
 extern void BSP_panic(char *s);
 extern void bsp_reset(void);
 /* extern int printk(const char *, ...) __attribute__((format(printf, 1, 2))); */
@@ -118,24 +165,31 @@ extern unsigned int BSP_heap_start;
 #define RTEMS_BSP_NETWORK_DRIVER_ATTACH	rtems_i82544EI_driver_attach
 #endif
 
-extern int
-RTEMS_BSP_NETWORK_DRIVER_ATTACH(/* struct rtems_bsdnet_ifconfig * */);
+extern int RTEMS_BSP_NETWORK_DRIVER_ATTACH();
 
 /*
  *  BSP Configuration Default Overrides
  */
 #define BSP_ZERO_WORKSPACE_AUTOMATICALLY TRUE
 
-/* As per Linux, This should be in the ppc/system.h */
+#define gccMemBar() RTEMS_COMPILER_MEMORY_BARRIER()
 
+static inline void lwmemBar()
+{
+    asm volatile("lwsync":::"memory");
+}
+
+static inline void io_flush()
+{
+    asm volatile("isync":::"memory");
+}
 static inline void memBar()
 {
     asm volatile("sync":::"memory");
 }
-
 static inline void ioBar()
 {
-    asm volatile("eieio");
+    asm volatile("eieio":::"memory");
 }
 
 #endif 

c/src/lib/libbsp/powerpc/mvme5500/irq/BSP_irq.c

@@ -1,4 +1,4 @@
-/*  irq.c
+/*  BSP_irq.c
  *
  *  This file contains the implementation of the function described in irq.h
  *
@@ -8,21 +8,25 @@
  *  found in the file LICENSE in this distribution or at
  *  http://www.OARcorp.com/rtems/license.html.
  *
- *  Acknowledgement May 2004 : to Till Straumann <strauman@slac.stanford.edu>
+ *  Acknowledgement May 2004, to Till Straumann <strauman@slac.stanford.edu>
  *  for some inputs.
  *
  *  Copyright 2003, 2004, 2005, 2007  Shuchen Kate Feng <feng1@bnl.gov>,
- *                  NSLS,Brookhaven National Laboratory
- *  1) Modified and added support for the MVME5500 board.
- *  2) The implementation of picIsrTable[] is an original work by the
+ *            NSLS, Brookhaven National Laboratory. All rights reserved.
+ *
+ *  1) Used GT_GPP_Value register instead of the GT_GPP_Interrupt_Cause
+ *     register to monitor the cause of the level sensitive interrupts.
+ *     (Copyright : NDA item)
+ *  2) The implementation of picPrioTable[] is an original work by the
  *     author to optimize the software IRQ priority scheduling because
  *     Discovery controller does not provide H/W IRQ priority schedule. 
  *     It ensures the fastest/faster interrupt service to the
  *     highest/higher priority IRQ, if pendig.
  *  3) _CPU_MSR_SET() needs RTEMS_COMPILER_MEMORY_BARRIER()
- *
+ * 
  */
-  
+
+#include <stdio.h>  
 #include <rtems/system.h>
 #include <bsp.h>
 #include <bsp/irq.h>
@@ -39,9 +43,7 @@
 
 #define HI_INT_CAUSE 0x40000000
 
-#define MAX_IRQ_LOOP 30
-
-#define EDGE_TRIGGER
+#define MAX_IRQ_LOOP 20
 
 /* #define DEBUG_IRQ*/
 
@@ -57,11 +59,11 @@ static unsigned int BSP_irq_prio_mask_tbl[3][BSP_PIC_IRQ_NUMBER];
 
 /*
  * location used to store initial tables used for interrupt
- * management.
+ * management.BSP copy of the configuration 
  */
-static rtems_irq_global_settings* 	internal_config;
-/* handler table (cached copy ) */
+static rtems_irq_global_settings	BSP_config;
 static rtems_irq_connect_data*		rtems_hdl_tbl;
+
 /*
  * default handler connected on each irq after bsp initialization
  * (locally cached copy)
@@ -73,32 +75,33 @@ static volatile unsigned  *BSP_irqMask_reg[3];
 static volatile unsigned  *BSP_irqCause_reg[3];
 static volatile unsigned  BSP_irqMask_cache[3]={0,0,0}; 
 
-
-static int picIsrTblPtr=0;
+static int picPrioTblPtr=0;
 static unsigned int GPPIrqInTbl=0;
 static unsigned long long MainIrqInTbl=0;
 
 /* 
- * The software developers are forbidden to setup picIsrTable[],
+ * The software developers are forbidden to setup picPrioTable[],
  * as it is a powerful engine for the BSP to find the pending
  * highest priority IRQ at run time.  It ensures the fastest/faster
  * interrupt service to the highest/higher priority IRQ, if pendig.
  *
- * The picIsrTable[96] is updated dynamically at run time
+ * The picPrioTable[96] is updated dynamically at run time
  * based on the priority levels set at BSPirqPrioTable[96],
- * while the BSP_enable_pic_irq(), and BSP_disable_pic_irq()
+ * while the BSP_enable_irq_at_pic(), and BSP_disable_irq_at_pic()
  * commands are invoked.
  *
- * The picIsrTable[96] lists the enabled CPU main and GPP external interrupt 
+ * The picPrioTable[96] lists the enabled CPU main and GPP external interrupt 
  * numbers [0 (lowest)- 95 (highest)] starting from the highest priority
  * one to the lowest priority one. The highest priority interrupt is
- * located at picIsrTable[0], and the lowest priority interrupt is located
- * at picIsrTable[picIsrTblPtr-1].
+ * located at picPrioTable[0], and the lowest priority interrupt is located
+ * at picPrioTable[picPrioTblPtr-1].
  *
  *
  */
-/* BitNums for Main Interrupt Lo/High Cause and GPP, -1 means invalid bit */ 
-static unsigned int picIsrTable[BSP_PIC_IRQ_NUMBER]={  
+#define DynamicIsrTable
+#ifdef DynamicIsrTable
+/* BitNums for Main Interrupt Lo/High Cause, -1 means invalid bit */ 
+static unsigned int picPrioTable[BSP_PIC_IRQ_NUMBER]={ 
      -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
      -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
      -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
@@ -109,7 +112,19 @@ static unsigned int picIsrTable[BSP_PIC_IRQ_NUMBER]={
      -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
      -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
      -1, -1, -1, -1, -1, -1 };
-
+#else
+static unsigned int picPrioTable[BSP_PIC_IRQ_NUMBER]={ 
+     80, 84, 76, 77, 32, -1, -1, -1, -1, -1,
+     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+     -1, -1, -1, -1, -1, -1 };
+#endif
 
 /*
  * Check if IRQ is a MAIN CPU internal IRQ or GPP external IRQ
@@ -131,28 +146,18 @@ static inline int is_processor_irq(const rtems_irq_number irqLine)
 	 );
 }
 
-static inline unsigned int divIrq32(unsigned irq)
-{
-  return(irq/32);
-}
-
-static inline unsigned int modIrq32(unsigned irq)
-{
-   return(irq%32);
-}
-
 /*
  * ------------------------ RTEMS Irq helper functions ----------------
  */
  
 /*
- * Caution : this function assumes the variable "internal_config"
+ * Caution : this function assumes the variable "BSP_config"
  * is already set and that the tables it contains are still valid
  * and accessible.
  */
-static void compute_pic_masks_from_prio(rtems_irq_global_settings *config)
+static void compute_pic_masks_from_prio(void)
 {
-  int i,j, k;
+  int i,j, k, isGppMain;
   unsigned long long irq_prio_mask=0;
 
   /*
@@ -168,26 +173,27 @@ static void compute_pic_masks_from_prio(rtems_irq_global_settings *config)
 	    BSP_irq_prio_mask_tbl[k][i]=0;
 
         irq_prio_mask =0;
+        isGppMain =1;
         break;
       default : 
+        isGppMain =0;
         irq_prio_mask = (unsigned long long) (1LLU << i);
 	break;
     }
-    
-    if (irq_prio_mask) {
+    if ( isGppMain) continue; 
     for (j = 0; j <BSP_MAIN_IRQ_NUMBER; j++) {
         /*
          * Mask interrupts at PIC level that have a lower priority
          * or <Till Straumann> a equal priority. 
          */
-        if (config->irqPrioTbl [i] >= config->irqPrioTbl [j])
+        if (BSP_config.irqPrioTbl [i] >= BSP_config.irqPrioTbl [j])
 	   irq_prio_mask |= (unsigned long long)(1LLU << j);
     }
     
 
     BSP_irq_prio_mask_tbl[0][i] = irq_prio_mask & 0xffffffff;
     BSP_irq_prio_mask_tbl[1][i] = (irq_prio_mask>>32) & 0xffffffff;
-#ifdef DEBUG
+#if 0
     printk("irq_mask_prio_tbl[%d]:0x%8x%8x\n",i,BSP_irq_prio_mask_tbl[1][i],
 	   BSP_irq_prio_mask_tbl[0][i]);
 #endif 
@@ -195,14 +201,15 @@ static void compute_pic_masks_from_prio(rtems_irq_global_settings *config)
     BSP_irq_prio_mask_tbl[2][i] = 1<<i;
     /* Compute for the GPP priority interrupt mask */
     for (j=BSP_GPP_IRQ_LOWEST_OFFSET; j <BSP_PROCESSOR_IRQ_LOWEST_OFFSET; j++) {      
-      if (config->irqPrioTbl [i] >= config->irqPrioTbl [j])
+      if (BSP_config.irqPrioTbl [i] >= BSP_config.irqPrioTbl [j])
 	   BSP_irq_prio_mask_tbl[2][i] |= 1 << (j-BSP_GPP_IRQ_LOWEST_OFFSET); 
     }
-    }
+#if 0
+    printk("GPPirq_mask_prio_tbl[%d]:0x%8x\n",i,BSP_irq_prio_mask_tbl[2][i]);
+#endif 
   }
 }
 
-
 static void UpdateMainIrqTbl(int irqNum)
 {
   int i=0, j, shifted=0;
@@ -225,23 +232,25 @@ static void UpdateMainIrqTbl(int irqNum)
        ((irqNum>BSP_MICH_IRQ_MAX_OFFSET) && 
         (!(( 1 << (irqNum-BSP_GPP_IRQ_LOWEST_OFFSET)) & GPPIrqInTbl))))
   { 
-      while ( picIsrTable[i]!=-1) {
-        if (internal_config->irqPrioTbl[irqNum]>internal_config->irqPrioTbl[picIsrTable[i]]) {
+      while ( picPrioTable[i]!=-1) {
+        if (BSP_config.irqPrioTbl[irqNum]>BSP_config.irqPrioTbl[picPrioTable[i]]) {
           /* all other lower priority entries shifted right */
-          for (j=picIsrTblPtr;j>i; j--) 
-              picIsrTable[j]=picIsrTable[j-1];
-          picIsrTable[i]=irqNum;
+          for (j=picPrioTblPtr;j>i; j--) {
+              picPrioTable[j]=picPrioTable[j-1];
+          }
+          picPrioTable[i]=irqNum;
           shifted=1;
           break;
        }
        i++;
      }
-     if (!shifted) picIsrTable[picIsrTblPtr]=irqNum;
+     if (!shifted) picPrioTable[picPrioTblPtr] =irqNum;
+
      if (irqNum >BSP_MICH_IRQ_MAX_OFFSET)
         GPPIrqInTbl |= (1<< (irqNum-BSP_GPP_IRQ_LOWEST_OFFSET)); 
      else      
         MainIrqInTbl |= (unsigned long long)(1LLU << irqNum);
-     picIsrTblPtr++;
+     picPrioTblPtr++;
   }
 #ifdef SHOW_MORE_INIT_SETTINGS
   val2 = (MainIrqInTbl>>32) & 0xffffffff;
@@ -271,22 +280,23 @@ static void CleanMainIrqTbl(int irqNum)
         (( 1 << (irqNum-BSP_GPP_IRQ_LOWEST_OFFSET)) & GPPIrqInTbl)))
   { /* If entry in table*/
      for (i=0; i<64; i++) {
-       if (picIsrTable[i]==irqNum) {/*remove it from the entry */
+       if (picPrioTable[i]==irqNum) {/*remove it from the entry */
           /* all other lower priority entries shifted left */
-          for (j=i;j<picIsrTblPtr; j++) 
-              picIsrTable[j]=picIsrTable[j+1];
+	  for (j=i;j<picPrioTblPtr; j++) {
+              picPrioTable[j]=picPrioTable[j+1];
+          }
           if (irqNum >BSP_MICH_IRQ_MAX_OFFSET)
             GPPIrqInTbl &= ~(1<< (irqNum-BSP_GPP_IRQ_LOWEST_OFFSET)); 
           else      
             MainIrqInTbl &= ~(1LLU << irqNum);
-          picIsrTblPtr--;
+          picPrioTblPtr--;
           break;
        }
      }
   }
 }
 
-void BSP_enable_pic_irq(const rtems_irq_number irqNum)
+void BSP_enable_irq_at_pic(const rtems_irq_number irqNum)
 {
   unsigned bitNum, regNum;
   unsigned int level;
@@ -294,12 +304,14 @@ void BSP_enable_pic_irq(const rtems_irq_number irqNum)
   if ( !is_pic_irq(irqNum) )
   	return;
 
-  bitNum = modIrq32(((unsigned int)irqNum) - BSP_MICL_IRQ_LOWEST_OFFSET);
-  regNum = divIrq32(((unsigned int)irqNum) - BSP_MICL_IRQ_LOWEST_OFFSET);
+  bitNum = (((unsigned int)irqNum) - BSP_MICL_IRQ_LOWEST_OFFSET)%32;
+  regNum = (((unsigned int)irqNum) - BSP_MICL_IRQ_LOWEST_OFFSET)>>5;
 
   rtems_interrupt_disable(level); 
 
+#ifdef DynamicIsrTable
   UpdateMainIrqTbl((int) irqNum);
+#endif
   BSP_irqMask_cache[regNum] |= (1 << bitNum);
 
   out_le32(BSP_irqMask_reg[regNum], BSP_irqMask_cache[regNum]);
@@ -308,9 +320,9 @@ void BSP_enable_pic_irq(const rtems_irq_number irqNum)
   rtems_interrupt_enable(level);
 }
 
-void BSP_enable_irq_at_pic(const rtems_irq_number irqNum)
+void BSP_enable_pic_irq(const rtems_irq_number irqNum)
 {
-	BSP_enable_pic_irq(irqNum);
+	BSP_enable_irq_at_pic(irqNum);
 }
 
 int BSP_disable_irq_at_pic(const rtems_irq_number irqNum)
@@ -322,12 +334,14 @@ int BSP_disable_irq_at_pic(const rtems_irq_number irqNum)
   if ( ! is_pic_irq(irqNum) )
   	return -1;
 
-  bitNum = modIrq32(((unsigned int)irqNum) - BSP_MICL_IRQ_LOWEST_OFFSET);
-  regNum = divIrq32(((unsigned int)irqNum) - BSP_MICL_IRQ_LOWEST_OFFSET);
+  bitNum = (((unsigned int)irqNum) - BSP_MICL_IRQ_LOWEST_OFFSET)%32;
+  regNum = (((unsigned int)irqNum) - BSP_MICL_IRQ_LOWEST_OFFSET)>>5;
 
   rtems_interrupt_disable(level); 
 
+#ifdef DynamicIsrTable
   CleanMainIrqTbl((int) irqNum);
+#endif
 
   rval = BSP_irqMask_cache[regNum] & (1<<bitNum);
 
@@ -346,35 +360,29 @@ void BSP_disable_pic_irq(const rtems_irq_number irqNum)
 	(void)BSP_disable_irq_at_pic(irqNum);
 }
 
-int BSP_setup_the_pic(rtems_irq_global_settings *config)  /* adapt the same name as shared/irq */
+/* Use shared/irq : 2008 */
+int BSP_setup_the_pic(rtems_irq_global_settings* config)  
 {
     int i;
 
-	internal_config   = config;
-	default_rtems_hdl = config->defaultEntry.hdl;
-	rtems_hdl_tbl     = config->irqHdlTbl;
+    BSP_config = *config;
+    default_rtems_hdl = config->defaultEntry.hdl;
+    rtems_hdl_tbl     = config->irqHdlTbl;
 
     /* Get ready for discovery BSP */
-    BSP_irqMask_reg[0]= (volatile unsigned int *) (GT64260_REG_BASE + GT_CPU_INT_MASK_LO);
-    BSP_irqMask_reg[1]= (volatile unsigned int *) (GT64260_REG_BASE + GT_CPU_INT_MASK_HI);
-    BSP_irqMask_reg[2]= (volatile unsigned int *) (GT64260_REG_BASE + GT_GPP_Interrupt_Mask);
-
-    BSP_irqCause_reg[0]= (volatile unsigned int *) (GT64260_REG_BASE + GT_MAIN_INT_CAUSE_LO);
-    BSP_irqCause_reg[1]= (volatile unsigned int *) (GT64260_REG_BASE + GT_MAIN_INT_CAUSE_HI);
-    BSP_irqCause_reg[2]= (volatile unsigned int *) (GT64260_REG_BASE + GT_GPP_Interrupt_Cause);
-
-#ifdef EDGE_TRIGGER
+    BSP_irqMask_reg[0]= (volatile unsigned int *) (GT64x60_REG_BASE + GT64260_CPU_INT_MASK_LO);
+    BSP_irqMask_reg[1]= (volatile unsigned int *) (GT64x60_REG_BASE + GT64260_CPU_INT_MASK_HI);
+    BSP_irqCause_reg[0]= (volatile unsigned int *) (GT64x60_REG_BASE + GT64260_MAIN_INT_CAUSE_LO);
+    BSP_irqCause_reg[1]= (volatile unsigned int *) (GT64x60_REG_BASE + GT64260_MAIN_INT_CAUSE_HI);
+    BSP_irqMask_reg[2]= (volatile unsigned int *) (GT64x60_REG_BASE + GT_GPP_Interrupt_Mask);
+    BSP_irqCause_reg[2]= (volatile unsigned int *) (GT64x60_REG_BASE + GT_GPP_Value);
 
     /* Page 401, Table 598:
      * Comm Unit Arbiter Control register :
      * bit 10:GPP interrupts as level sensitive(1) or edge sensitive(0).
-     * We set the GPP interrupts to be edge sensitive.
-     * MOTload default is set as level sensitive(1).
+     * MOTload default is set as level sensitive(1). Set it agin to make sure.
      */
-    outl((inl(GT_CommUnitArb_Ctrl)& (~(1<<10))), GT_CommUnitArb_Ctrl);
-#else
-    outl((inl(GT_CommUnitArb_Ctrl)| (1<<10)), GT_CommUnitArb_Ctrl);
-#endif
+    out_le32(GT_CommUnitArb_Ctrl, (in_le32(GT_CommUnitArb_Ctrl)| (1<<10)));
 
 #if 0
     printk("BSP_irqMask_reg[0] = 0x%x, BSP_irqCause_reg[0] 0x%x\n", 
@@ -388,13 +396,13 @@ int BSP_setup_the_pic(rtems_irq_global_settings *config)  /* adapt the same name
 	   in_le32(BSP_irqCause_reg[2]));
 #endif
 
-    /* Initialize the interrupt related GT64260 registers */
+    /* Initialize the interrupt related  registers */
     for (i=0; i<3; i++) {
       out_le32(BSP_irqCause_reg[i], 0);
       out_le32(BSP_irqMask_reg[i], 0);
     }         
     in_le32(BSP_irqMask_reg[2]);
-    compute_pic_masks_from_prio(config);
+    compute_pic_masks_from_prio();
 
 #if 0
     printk("BSP_irqMask_reg[0] = 0x%x, BSP_irqCause_reg[0] 0x%x\n", 
@@ -408,74 +416,65 @@ int BSP_setup_the_pic(rtems_irq_global_settings *config)  /* adapt the same name
 	   in_le32(BSP_irqCause_reg[2]));
 #endif
 
+    /*
+     * 
+     */
+    for (i=BSP_MICL_IRQ_LOWEST_OFFSET; i < BSP_PROCESSOR_IRQ_LOWEST_OFFSET ; i++) {
+      if ( BSP_config.irqHdlTbl[i].hdl != BSP_config.defaultEntry.hdl) {
+	BSP_enable_irq_at_pic(i);
+	BSP_config.irqHdlTbl[i].on(&BSP_config.irqHdlTbl[i]);
+      }
+      else {
+	BSP_config.irqHdlTbl[i].off(&BSP_config.irqHdlTbl[i]);
+	BSP_disable_irq_at_pic(i);
+      }
+    }
+    for (i= BSP_MAIN_GPP7_0_IRQ; i < BSP_MAIN_GPP31_24_IRQ; i++) 
+      BSP_enable_irq_at_pic(i);
+    
     return(1);
 }
 
-/*
- * This function check that the value given for the irq line
- * is valid.
- */
-
 /*
  * High level IRQ handler called from shared_raw_irq_code_entry
  */
-
 int C_dispatch_irq_handler (BSP_Exception_frame *frame, unsigned int excNum)
 {
   unsigned long irqCause[3]={0, 0,0};
-  register unsigned long selectCause;
   unsigned oldMask[3]={0,0,0};
-  register unsigned i=0, j, irq=0, bitmask=0, group=0;
+  int loop=0, wloop=0, i=0, j;
+  int irq=0, group=0;
 
   if (excNum == ASM_DEC_VECTOR) {
-
-  	bsp_irq_dispatch_list( rtems_hdl_tbl, BSP_DECREMENTER, default_rtems_hdl);
-
-    return 0;
-    
+      bsp_irq_dispatch_list( rtems_hdl_tbl, BSP_DECREMENTER, default_rtems_hdl);
+      return 0;   
   }
 
   for (j=0; j<3; j++ ) oldMask[j] = BSP_irqMask_cache[j];
+  for (j=0; j<3; j++) irqCause[j] = in_le32(BSP_irqCause_reg[j]) & in_le32(BSP_irqMask_reg[j]);
 
-  if ((selectCause= in_le32((volatile unsigned *)0xf1000c70)) & HI_INT_CAUSE ){
-    irqCause[1] = (selectCause & BSP_irqMask_cache[1]);
-    irqCause[2] = in_le32(BSP_irqCause_reg[2]) & BSP_irqMask_cache[2];
-  }
-  else {
-    irqCause[0] = (selectCause & BSP_irqMask_cache[0]);
-    if ((irqCause[1] =(in_le32((volatile unsigned *)0xf1000c68)&BSP_irqMask_cache[1])))
-       irqCause[2] = in_le32(BSP_irqCause_reg[2]) & BSP_irqMask_cache[2];
-  }
-  
-  while ((irq = picIsrTable[i++])!=-1)
-  {
-    if (irqCause[group=(irq/32)] && (irqCause[group]&(bitmask=(1<<(irq % 32))))) {
+  while (((irq = picPrioTable[i++])!=-1)&& (loop++ < MAX_IRQ_LOOP))
+  {    
+    if (irqCause[group= irq/32] & ( 1<<(irq % 32))) {
       for (j=0; j<3; j++)
         BSP_irqMask_cache[j] &= (~ BSP_irq_prio_mask_tbl[j][irq]);
 
-      RTEMS_COMPILER_MEMORY_BARRIER();
-      out_le32((volatile unsigned *)0xf1000c1c, BSP_irqMask_cache[0]);
-      out_le32((volatile unsigned *)0xf1000c6c, BSP_irqMask_cache[1]);
-      out_le32((volatile unsigned *)0xf100f10c, BSP_irqMask_cache[2]);
-      in_le32((volatile unsigned *)0xf100f10c);
+      out_le32(BSP_irqMask_reg[0], BSP_irqMask_cache[0]);
+      out_le32(BSP_irqMask_reg[1], BSP_irqMask_cache[1]);
+      out_le32(BSP_irqMask_reg[2], BSP_irqMask_cache[2]);
+      in_le32(BSP_irqMask_reg[2]);
 
-#ifdef EDGE_TRIGGER
-      if (irq > BSP_MICH_IRQ_MAX_OFFSET)
-         out_le32(BSP_irqCause_reg[2], ~bitmask);/* Till Straumann: Ack the edge triggered GPP IRQ */
-#endif
+      bsp_irq_dispatch_list( rtems_hdl_tbl, irq, default_rtems_hdl);
 
-  	  bsp_irq_dispatch_list( rtems_hdl_tbl, irq, default_rtems_hdl);
-      
       for (j=0; j<3; j++ ) BSP_irqMask_cache[j] = oldMask[j];
-      break;
+ 
+      out_le32(BSP_irqMask_reg[0], oldMask[0]);
+      out_le32(BSP_irqMask_reg[1], oldMask[1]);
+      out_le32(BSP_irqMask_reg[2], oldMask[2]);
+      in_le32(BSP_irqMask_reg[2]);
     }
   }
 
-  out_le32((volatile unsigned *)0xf1000c1c, oldMask[0]);
-  out_le32((volatile unsigned *)0xf1000c6c, oldMask[1]);
-  out_le32((volatile unsigned *)0xf100f10c, oldMask[2]);
-  in_le32((volatile unsigned *)0xf100f10c);
-
   return 0;
 }
 
@@ -484,10 +483,10 @@ void BSP_printPicIsrTbl()
 {
   int i;
 
-  printk("picIsrTable[12]={");
+  printf("picPrioTable[12]={ {irq# : ");
   for (i=0; i<12; i++)
-    printk("%d,", picIsrTable[i]);
-  printk("}\n");
+    printf("%d,", picPrioTable[i]);
+  printf("}\n");
 
-  printk("GPPIrqInTbl: 0x%x :\n", GPPIrqInTbl);
+  printf("GPPIrqInTbl: 0x%x :\n", GPPIrqInTbl);
 }

c/src/lib/libbsp/powerpc/mvme5500/irq/irq_init.c

@@ -36,10 +36,18 @@ static int connected(void) {return 1;}
 
 static rtems_irq_connect_data     	rtemsIrq[BSP_IRQ_NUMBER];
 static rtems_irq_global_settings     	initial_config;
+
+#ifdef BSP_SHARED_HANDLER_SUPPORT
+static rtems_irq_connect_data     	defaultIrq = {
+  /* vectorIdex,  hdl	    ,handle  , on	, off	   , isOn      ,next_handler, */
+  0, 		  nop_func  , NULL   , nop_func	, nop_func , not_connected, 0
+};
+#else
 static rtems_irq_connect_data     	defaultIrq = {
   /* vectorIdex,	 hdl	  , handle	, on		, off		, isOn */
   0, 			 nop_func  , NULL	, nop_func	, nop_func	, not_connected
 };
+#endif
 
 rtems_irq_prio BSPirqPrioTable[BSP_PIC_IRQ_NUMBER]={
   /*
@@ -135,12 +143,6 @@ void BSP_rtems_irq_mng_init(unsigned cpuId)
 #ifdef TRACE_IRQ_INIT  
   printk("Done setup irq mngt configuration\n");
 #endif
-  
-  /* I don't really understand why all sources are enable here... (T.S) */
-  for (i= BSP_MAIN_GPP7_0_IRQ; i <= BSP_MAIN_GPP31_24_IRQ; i++) 
-      BSP_enable_pic_irq(i);
-
-  rtems_interrupt_enable(l);
 
 #ifdef TRACE_IRQ_INIT  
   printk("RTEMS IRQ management is now operationnal\n");