2005-09-01 Joel Sherrill <joel@OARcorp.com>

* VERSION: Updated to rtems-4.6.4.
2005-09-01 17:18:50 +00:00 · 2005-09-01 17:18:49 +00:00 · 2005-09-01 16:31:22 +00:00 · 2005-09-01 16:14:17 +00:00 · 2005-09-01 14:46:02 +00:00 · 2005-09-01 13:39:14 +00:00
164 changed files with 3696 additions and 1162 deletions
--- a/16
+++ b/16
@@ -1,3 +1,19 @@
+2005-09-01	Joel Sherrill <joel@OARcorp.com>
+
+	* VERSION: Updated to rtems-4.6.4.
+
+2005-09-01	Joel Sherrill <joel@OARcorp.com>
+
+	* aclocal/version.m4: Updated to rtems-4.6.4.
+
+2005-03-17	Joel Sherrill <joel@OARcorp.com>
+
+	* VERSION: Updated to rtems-4.6.3.
+
+2004-11-10	Richard Campbell <richard.campbell@oarcorp.com>
+
+	* aclocal/bsp-alias.m4: Add MVME2100 BSP.
+
 2004-10-18	Joel Sherrill <joel@OARcorp.com>

 	* VERSION: Updated to rtems-4.6.2.
--- a/2
+++ b/2
@@ -4,4 +4,4 @@
 #  $Id$
 #

-RTEMS Version 4.6.2
+RTEMS Version 4.6.4
--- a/aclocal/bsp-alias.m4
+++ b/aclocal/bsp-alias.m4
@@ -10,6 +10,7 @@ AC_DEFUN([_RTEMS_BSP_ALIAS],
    simcpu32)     $2=sim68000         ;; # BSVC CPU32 variant
    c3xsim)       $2=c4xsim           ;; # TI C3x Simulator in gdb
    mcp750)       $2=motorola_powerpc ;; # Motorola PPC board variant
+    mvme2100)     $2=motorola_powerpc ;; # Motorola PPC board variant
    mvme2307)     $2=motorola_powerpc ;; # Motorola PPC board variant
    mtx603e)      $2=motorola_powerpc ;; # Motorola PPC board variant
    mvme162lx)    $2=mvme162          ;; # m68k - mvme162 board variant
--- a/aclocal/version.m4
+++ b/aclocal/version.m4
@@ -1,2 +1,2 @@
 AC_DEFUN([RTEMS_VERSIONING],
-m4_define([_RTEMS_VERSION],[4.6.2]))
+m4_define([_RTEMS_VERSION],[4.6.4]))
--- a/c/src/lib/libbsp/i386/pc386/ChangeLog
+++ b/c/src/lib/libbsp/i386/pc386/ChangeLog
@@ -1,3 +1,12 @@
+2005-09-01	Joel Sherrill <joel@OARcorp.com>
+
+	* clock/Makefile.am, include/Makefile.am: Install tod.h
+
+2005-01-20	Joel Sherrill <joel@OARcorp.com>
+
+	PR 743/bsps
+	* clock/Makefile.am: Did not install tod.h.
+
 2004-10-13	Eric Norum <norume@aps.anl.gov>

 	PR 688/bsps
--- a/c/src/lib/libbsp/i386/pc386/include/Makefile.am
+++ b/c/src/lib/libbsp/i386/pc386/include/Makefile.am
@@ -9,11 +9,15 @@ if HAS_NETWORKING
 WD80X3 = wd80x3.h
 endif

-include_HEADERS = bsp.h crt.h coverhd.h $(WD80X3) bspopts.h
+include_HEADERS = bsp.h crt.h coverhd.h tod.h $(WD80X3) bspopts.h

 coverhd.h: $(top_srcdir)/../../shared/include/coverhd.h
 	cp $< $@
-CLEANFILES = coverhd.h
+
+tod.h: $(top_srcdir)/../../shared/tod.h
+	cp $< $@
+
+CLEANFILES = coverhd.h tod.h

 $(PROJECT_INCLUDE):
 	$(mkinstalldirs) $@
--- a/c/src/lib/libbsp/i386/shared/ChangeLog
+++ b/c/src/lib/libbsp/i386/shared/ChangeLog
@@ -1,4 +1,4 @@
-2003-11-01      Greg Menke <gregory.menke@gsfc.nasa.gov>
+2004-09-27      Greg Menke <gregory.menke@gsfc.nasa.gov>

 	PR 608/bsps
 	* pci/pcibios.c: BusCountPCI().
--- a/c/src/lib/libbsp/powerpc/ChangeLog
+++ b/c/src/lib/libbsp/powerpc/ChangeLog
@@ -1,3 +1,8 @@
+2004-11-10	Richard Campbell <richard.campbell@oarcorp.com>
+
+	* configure.ac: Add TOD support in shared as part of adding MVME2100
+	BSP.
+
 2003-08-11	Ralf Corsepius <corsepiu@faw.uni-ulm.de>

 	* configure.ac: Use rtems-bugs@rtems.com as bug report email address.
--- a/c/src/lib/libbsp/powerpc/configure.ac
+++ b/c/src/lib/libbsp/powerpc/configure.ac
@@ -33,6 +33,7 @@ shared/pci/Makefile
 shared/residual/Makefile
 shared/start/Makefile
 shared/startup/Makefile
+shared/tod/Makefile
 shared/vectors/Makefile
 shared/vme/Makefile])
 AC_OUTPUT
--- a/c/src/lib/libbsp/powerpc/helas403/ChangeLog
+++ b/c/src/lib/libbsp/powerpc/helas403/ChangeLog
@@ -1,3 +1,9 @@
+2004-10-02	Ralf Corsepius <ralf_corsepius@rtems.org>
+
+	PR 697/bsps
+	* flashentry/flashentry.S: Fix broken comments
+	(Patch by Thomas.Doerfler@imd-systems.de)
+
 2003-12-16	Ralf Corsepius <corsepiu@faw.uni-ulm.de>

 	PR 533/bsps
--- a/c/src/lib/libbsp/powerpc/helas403/flashentry/flashentry.S
+++ b/c/src/lib/libbsp/powerpc/helas403/flashentry/flashentry.S
@@ -191,7 +191,7 @@ stack_top:
 	lis	r3,0x0100       /* size  16 MB   = 0x01000000 */
 	bl	ramacc		/* test memory accessibility  */
 	cmpi	0,0,r4,0	/* memory ok? else test smaller size */
-	beq	ramcfgok	/* ok, we found configuration... +/
+	beq	ramcfgok	/* ok, we found configuration... */
 	
 	lis	r2,0x0000	/* disable BR6, config not ok */
 	mtdcr	br6,r2		/* write to DCR BR6*/	
@@ -263,7 +263,7 @@ ramcfgt18:
 	lis	r3,0x0080       /* size   8 MB   = 0x00800000 */
 	bl	ramacc		/* test memory accessibility  */
 	cmpi	0,0,r4,0	/* memory ok? else test smaller size */
-	beq	ramcfgok	/* ok, we found configuration... +/
+	beq	ramcfgok	/* ok, we found configuration... */
 	
 	lis	r2,0x0000	/* disable BR6, config not ok */
 	mtdcr	br6,r2		/* write to DCR BR6*/	
@@ -333,7 +333,7 @@ ramcfgt14:
 	lis	r3,0x0040       /* size   4 MB   = 0x00400000 */
 	bl	ramacc		/* test memory accessibility  */
 	cmpi	0,0,r4,0	/* memory ok? else test smaller size */
-	beq	ramcfgok	/* ok, we found configuration... +/
+	beq	ramcfgok	/* ok, we found configuration... */
 	
 	lis	r2,0x0000	/* disable BR6, config not ok */
 	mtdcr	br6,r2		/* write to DCR BR6*/	
--- a/c/src/lib/libbsp/powerpc/motorola_powerpc/ChangeLog
+++ b/c/src/lib/libbsp/powerpc/motorola_powerpc/ChangeLog
@@ -1,3 +1,19 @@
+2005-05-20	Ralf Corsepius <ralf_corsepius@rtems.org>
+
+	PR 717/bsps
+	* bootloader/Makefile.am: Typo results in wrong flags being used.
+
+2004-11-16	Richard Campbell <richard.campbell@OARcorp.com>
+
+	* README.MVME2100: Update to include DBAT0.
+	* bsp_specs: Fix spacing.
+
+2004-11-10	Richard Campbell <richard.campbell@oarcorp.com>
+
+	* Makefile.am, configure.ac, bootloader/Makefile.am,
+	include/Makefile.am, wrapup/Makefile.am: Add MVME2100 BSP.
+	* README.MVME2100, tod/.cvsignore, tod/Makefile.am: New files.
+
 2003-12-16	Ralf Corsepius <corsepiu@faw.uni-ulm.de>

 	PR 533/bsps
--- a/c/src/lib/libbsp/powerpc/motorola_powerpc/Makefile.am
+++ b/c/src/lib/libbsp/powerpc/motorola_powerpc/Makefile.am
@@ -7,12 +7,12 @@ ACLOCAL_AMFLAGS = -I ../../../../../../aclocal
 # wrapup is the one that actually builds and installs the library
 #  from the individual .rel files built in other directories
 SUBDIRS = include clock console pci residual openpic irq vectors start \
-    startup bootloader motorola @exceptions@ vme wrapup
+    startup bootloader motorola @exceptions@ tod vme wrapup

 include $(top_srcdir)/../../bsp.am

-EXTRA_DIST = BOOTING README.MVME2300 README.OTHERBOARDS README.dec21140 \
-    bsp_specs times.mcp750 times.mvme2307
+EXTRA_DIST = BOOTING README.MVME2100 README.MVME2300 README.OTHERBOARDS \
+    README.dec21140 bsp_specs times.mcp750 times.mvme2307

 include $(top_srcdir)/../../../../../../automake/subdirs.am
 include $(top_srcdir)/../../../../../../automake/local.am
--- a/c/src/lib/libbsp/powerpc/motorola_powerpc/README.MVME2100
+++ b/c/src/lib/libbsp/powerpc/motorola_powerpc/README.MVME2100
@@ -0,0 +1,132 @@
+#
+# $Id$
+#
+
+The MVME2100 is a Motorola VMEbus board which is similar to the other
+Motorola PowerPC boards supported by this BSP.  But it does not support
+the Motorola CPU Configuration Register.  This makes it impossible to
+dynamically probe and determine that you are executing on this board
+variant.  So this BSP variant must be explicitly built to only support
+the MVME2100.  The complete list of differences found so far is:
+
+  * No CPU Configuration Register
+  * one COM port
+  * COM port is on PCI IRQ not ISA IRQ
+  * limited on RAM (32 or 64 MB)
+  * uses the EPIC interrupt controller on the MPC8240
+  * does not have an ISA bus but has an ISA I/O address space
+  * cannot set DBAT2 in bspstart like other variants because
+    there are PCI/ISA Interrupt Acknowledge registers at this space
+    This BSP may have left some PCI memory uncovered
+  * PPCBug starts programs with vectors still in ROM
+
+Supported Features:
+  - Interrupt driven console using termios
+  - Network device driver
+  - Real-Time Clock driver
+  - Clock Tick Device Driver
+
+Things to address:
+  - Does not return to monitor
+  - Level 1 cache is disabled for now
+  - Check on trying to read CPU Configuration Register for CHRP/Prep for PCI
+    and report a failure if in the wrong mode.  May be able to set the model
+    but it may be hard to test if we break PPCBug.
+  - Use NVRAM for network configuration information
+
+BSP Features Not Implemented:
+  - VMEbus mapped in but untested
+  - OpenPIC features not required for BSP are not supported
+
+Memory Map
+==========
+                                                     BAT Mapping
+
+    ffff ffff   |------------------------------------| ----- ffff ffff
+                | ROM/FLASH Bank 0                   |   |
+    fff0 0000   |------------------------------------|   |
+                | System I/O                         |   |
+    ffe0 0000   |------------------------------------|   |
+                | Replicated ROM/FLASH Bank 0        |   |
+                | Replicated System I/O              |   |
+    ff80 0000   |------------------------------------|   |
+                | ROM/FLASH Bank 1                   | DBAT3
+    ff00 0000   |------------------------------------|  - Supervisor R/W
+                | PCI Interrupt Acknowledge          |  - Cache Inhibited
+    fef0 0000   |------------------------------------|  - Guarded
+                | PCI Configuration Data Register    |   |
+    fee0 0000   |------------------------------------|   | 
+                | PCI Configuration Address Register |   | 
+    fec0 0000   |------------------------------------|   | 
+                | PCI I/O Space                      |   | 
+    fe80 0000   |------------------------------------|   | 
+                | PCI/ISA I/O Space                  |   | 
+    fe00 0000   |------------------------------------|   | 
+                | PCI/ISA Memory Space               |   | 
+    fd00 0000   |------------------------------------|   | 
+                |                                    |   | 
+                |                      xxxxxxxxxxxxxx| ----- f000 0000
+                |                      x not mapped  |   |
+                |                      xxxxxxxxxxxxxx| ----- a000 0000 
+                |                                    |   | 
+                |                                    |   |
+                |                                    | DBAT0
+                |                                    |  - Supervisor R/W
+                |                                    |  - Cache Inhibited
+                |                                    |  - Guarded
+                |                                    |   |
+                |                                    |   | 
+                |                                    | ----- 9000 0000
+                |                                    |   |
+                |                                    |   |
+                | PCI Memory Space                   | DBAT2
+                |                                    |  - Supervisor R/W
+                |                                    |  - Cache Inhibited 
+                |                                    |  - Guarded
+                |                                    |   |
+                |                                    |   |
+                |                                    |   |
+    8000 0000   |------------------------------------| ----- 8000 0000
+                |                      x             |   
+                |                      x not mapped  |
+                | Reserved             xxxxxxxxxxxxxx| ----- 1000 0000
+                |                                    |   |
+                |                                    |   |
+    0200 0000   |------------------------------------|   |
+                |                                    |   |
+                |                                    |   |
+                |                                    |   |
+                |                                    |   |
+                | DRAM (32MB)                        | DBAT1/IBAT1
+                |                                    |  - Supervisor R/W
+                |                                    |   |
+                |                                    |   |
+                |                                    |   |
+                |                                    |   |
+    0000 0000   |------------------------------------| ----- 0000 0000
+                
+
+TTCP Performance on First Day Run
+=================================
+Fedora Core 1 on (according to /proc/cpuinfo) a 300 Mhz P3 using Netgear
+10/100 CardBus NIC on a dedicated 10BaseT LAN.  
+
+ON MVME2100:            ttcp -t -s 192.168.2.107
+REPORTED ON MVME2100:
+ttcp-t: buflen=8192, nbuf=2048, align=16384/0, port=5001  tcp  -> 192.168.2.107
+ttcp-t: socket
+ttcp-t: connect
+ttcp-t: 16777216 bytes in 20.80 real seconds = 787.69 KB/sec +++
+ttcp-t: 2048 I/O calls, msec/call = 10.40, calls/sec = 98.46
+ttcp-t: 0.0user 20.8sys 0:20real 100% 0i+0d 0maxrss 0+0pf 0+0csw
+
+ON MVME2100:            ttcp -t -s 192.168.2.107
+REPORTED ON MVME2100:
+ttcp -r -s
+ttcp-r: buflen=8192, nbuf=2048, align=16384/0, port=5001  tcp
+ttcp-r: socket
+ttcp-r: accept from 192.168.2.107
+ttcp-r: 16777216 bytes in 15.41 real seconds = 1063.21 KB/sec +++
+ttcp-r: 11588 I/O calls, msec/call = 1.36, calls/sec = 751.98
+ttcp-r: 0.0user 15.4sys 0:15real 100% 0i+0d 0maxrss 0+0pf 0+0csw
+
--- a/c/src/lib/libbsp/powerpc/motorola_powerpc/bootloader/Makefile.am
+++ b/c/src/lib/libbsp/powerpc/motorola_powerpc/bootloader/Makefile.am
@@ -24,8 +24,8 @@ LD = @LD@
 DEFAULT_INCLUDES =

 # Remove references to EABI when compiling bootloader
-BOOTLOADER_CPU_FLAGS=$(subst -msdata=eabi,,$(subst -meabi,,$(CPU_CFLAGS)))
-AM_CPPFLAGS = -D__BOOT__ -DDEBUG
+BOOTLOADER_CPU_CFLAGS=$(subst -msdata=eabi,,$(subst -meabi,,$(CPU_CFLAGS)))
+AM_CPPFLAGS = -D__BOOT__
 AM_CFLAGS = \
    $(GCC_SPECS) -specs bsp_specs -qrtems -mrelocatable \
    -msoft-float -mstrict-align -fno-builtin -Wall -mmultiple \
--- a/c/src/lib/libbsp/powerpc/motorola_powerpc/bsp_specs
+++ b/c/src/lib/libbsp/powerpc/motorola_powerpc/bsp_specs
@@ -3,11 +3,10 @@
 %rename startfile old_startfile
 %rename link old_link

-
 *lib:
 %{!qrtems: %(old_lib)} %{!nostdlib: %{qrtems: --start-group \
 %{!qrtems_debug: -lrtemsbsp -lrtemscpu} %{qrtems_debug: -lrtemsbsp_g -lrtemscpu_g} \
-lc -lgcc --end-group  \
+-lc -lgcc --end-group \
 %{!qnolinkcmds: -T linkcmds%s}}}

 *startfile:
--- a/c/src/lib/libbsp/powerpc/motorola_powerpc/configure.ac
+++ b/c/src/lib/libbsp/powerpc/motorola_powerpc/configure.ac
@@ -20,6 +20,16 @@ AM_CONDITIONAL(HAS_NETWORKING,test "$HAS_NETWORKING" = "yes")
 AS=$CC
 AM_PROG_AS

+RTEMS_BSPOPTS_SET([mvme2100],[mvme2100],[1])
+RTEMS_BSPOPTS_SET([mvme2100],[*],[])
+RTEMS_BSPOPTS_HELP([mvme2100],
+[Defined for MVME2100 -- undefined for others])
+
+RTEMS_BSPOPTS_SET([mpc8240],[mvme2100],[1])
+RTEMS_BSPOPTS_SET([mpc8240],[*],[])
+RTEMS_BSPOPTS_HELP([mpc8240],
+[Defined for boards with MPC8240 -- undefined for others])
+
 RTEMS_BSPOPTS_SET([PPC_USE_DATA_CACHE],[*],[1])
 RTEMS_BSPOPTS_HELP([PPC_USE_DATA_CACHE],
 [If defined, then the PowerPC specific code in RTEMS will use
@@ -43,6 +53,7 @@ pci/Makefile
 residual/Makefile
 start/Makefile
 startup/Makefile
+tod/Makefile
 vectors/Makefile
 vme/Makefile
 wrapup/Makefile])
--- a/c/src/lib/libbsp/powerpc/motorola_powerpc/include/Makefile.am
+++ b/c/src/lib/libbsp/powerpc/motorola_powerpc/include/Makefile.am
@@ -5,11 +5,12 @@
 include_HEADERS = bspopts.h

 include_HEADERS += ../../shared/include/nvram.h ../../shared/include/bsp.h \
-    ../../../shared/include/coverhd.h
+    ../../../shared/include/coverhd.h ../../../shared/tod.h

 include_bspdir = $(includedir)/bsp
-include_bsp_HEADERS = ../../shared/console/consoleIo.h ../../shared/console/uart.h \
-    ../../shared/irq/irq.h ../../shared/motorola/motorola.h
+include_bsp_HEADERS = ../../shared/console/consoleIo.h \
+    ../../shared/console/uart.h ../../shared/irq/irq.h \
+    ../../shared/motorola/motorola.h

 $(PROJECT_INCLUDE):
 	$(mkinstalldirs) $@
@@ -29,6 +30,9 @@ $(PROJECT_INCLUDE)/bsp.h: ../../shared/include/bsp.h
 $(PROJECT_INCLUDE)/coverhd.h: ../../../shared/include/coverhd.h
 	$(INSTALL_DATA) $< $@

+$(PROJECT_INCLUDE)/tod.h: ../../../shared/tod.h
+	$(INSTALL_DATA) $< $@
+
 $(PROJECT_INCLUDE)/bsp/consoleIo.h: ../../shared/console/consoleIo.h
 	$(INSTALL_DATA) $< $@

@@ -46,6 +50,7 @@ TMPINSTALL_FILES += $(PROJECT_INCLUDE)/bspopts.h
 TMPINSTALL_FILES += $(PROJECT_INCLUDE)/bsp.h
 TMPINSTALL_FILES += $(PROJECT_INCLUDE)/nvram.h
 TMPINSTALL_FILES += $(PROJECT_INCLUDE)/coverhd.h
+TMPINSTALL_FILES += $(PROJECT_INCLUDE)/tod.h

 TMPINSTALL_FILES += $(PROJECT_INCLUDE)/bsp
 TMPINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/motorola.h
--- a/c/src/lib/libbsp/powerpc/motorola_powerpc/tod/.cvsignore
+++ b/c/src/lib/libbsp/powerpc/motorola_powerpc/tod/.cvsignore
@@ -0,0 +1,2 @@
+Makefile
+Makefile.in
--- a/c/src/lib/libbsp/powerpc/motorola_powerpc/tod/Makefile.am
+++ b/c/src/lib/libbsp/powerpc/motorola_powerpc/tod/Makefile.am
@@ -0,0 +1,22 @@
+##
+## $Id$
+##
+
+
+VPATH = @srcdir@:@srcdir@/../../shared/tod:@srcdir@/../../../shared
+
+C_FILES = todcfg.c tod.c
+C_O_FILES = $(C_FILES:%.c=$(ARCH)/%.$(OBJEXT))
+
+OBJS = $(C_O_FILES)
+
+include $(top_srcdir)/../../../../../../automake/compile.am
+include $(top_srcdir)/../../../../../../automake/lib.am
+
+#
+# (OPTIONAL) Add local stuff here using +=
+#
+
+all-local: $(ARCH) $(OBJS)
+
+include $(top_srcdir)/../../../../../../automake/local.am
--- a/c/src/lib/libbsp/powerpc/motorola_powerpc/wrapup/Makefile.am
+++ b/c/src/lib/libbsp/powerpc/motorola_powerpc/wrapup/Makefile.am
@@ -2,7 +2,8 @@
 ## $Id$
 ##

-BSP_PIECES = clock console irq openpic pci residual startup vectors motorola vme
+BSP_PIECES = clock console irq openpic pci residual startup \
+    tod vectors motorola vme

 # bummer; have to use $foreach since % pattern subst rules only replace 1x
 OBJS = $(foreach piece, $(BSP_PIECES), ../$(piece)/$(ARCH)/*.$(OBJEXT)) \
--- a/c/src/lib/libbsp/powerpc/psim/ChangeLog
+++ b/c/src/lib/libbsp/powerpc/psim/ChangeLog
@@ -1,3 +1,29 @@
+2005-04-11      Jennifer Averett <jennifer@OARcorp.com>
+
+        PR 777/bsps
+        * include/bsp.h: Add a Processor_Synchronize command in bsp.h
+
+2005-03-17	Joel Sherrill <joel@OARcorp.com>
+
+	* irq/.cvsignore: New file.
+
+2004-11-22	Jennifer Averett <jennifer@OARcorp.com>
+
+	* Makefile.am, wrapup/Makefile.am: Pick up SHM driver when MP enabled.
+
+2004-11-22	Jennifer Averett <jennifer@OARcorp.com>
+
+	PR 617/bsps
+	PR 581/bsps
+	* Makefile.am, bsp_specs, configure.ac, clock/Makefile.am,
+	include/bsp.h, start/Makefile.am, start/start.S, startup/Makefile.am,
+	startup/bspstart.c, startup/linkcmds, vectors/Makefile.am,
+	vectors/vectors.S, wrapup/Makefile.am: Convert PSIM to new exception
+	model.
+	* irq/Makefile.am, irq/irq.c, irq/irq.h, irq/irq_asm.S,
+	irq/irq_init.c: New files.
+	* clock/clock.c: Removed.
+
 2003-12-16	Ralf Corsepius <corsepiu@faw.uni-ulm.de>

 	PR 533/bsps
--- a/c/src/lib/libbsp/powerpc/psim/Makefile.am
+++ b/c/src/lib/libbsp/powerpc/psim/Makefile.am
@@ -6,7 +6,7 @@ ACLOCAL_AMFLAGS = -I ../../../../../../aclocal

 # wrapup is the one that actually builds and installs the library
 #  from the individual .rel files built in other directories
-SUBDIRS = include start clock console startup shmsupp timer vectors \
+SUBDIRS = include start irq clock console startup shmsupp timer vectors \
    @exceptions@ wrapup \
    tools

--- a/c/src/lib/libbsp/powerpc/psim/bsp_specs
+++ b/c/src/lib/libbsp/powerpc/psim/bsp_specs
@@ -10,13 +10,13 @@
 %{!qnolinkcmds: -T linkcmds%s}}}

 *startfile:
-%{!qrtems: %(old_startfile)} %{!nostdlib: %{qrtems:  ecrti%O%s \
+%{!qrtems: %(old_startfile)} %{!nostdlib: %{qrtems:  ecrti%O%s rtems_crti%O%s  crtbegin.o%s  \
 %{!qrtems_debug: start.o%s} \
 %{qrtems_debug: start_g.o%s}}}

-*endfile:
-%{!qrtems: %(old_endfile)} %{qrtems: ecrtn%O%s}
-
 *link:
 %{!qrtems: %(old_link)} %{qrtems: -Qy -dp -Bstatic -e _start -u __vectors}

+*endfile:
+%{!qrtems: %(old_endfile)} %{qrtems: crtend.o%s ecrtn.o%s}
+
--- a/c/src/lib/libbsp/powerpc/psim/clock/Makefile.am
+++ b/c/src/lib/libbsp/powerpc/psim/clock/Makefile.am
@@ -3,9 +3,9 @@
 ##


-PGM = $(ARCH)/clock.rel
+VPATH = @srcdir@:@srcdir@/../../shared/clock

-C_FILES = clock.c
+C_FILES = p_clock.c
 C_O_FILES = $(C_FILES:%.c=$(ARCH)/%.$(OBJEXT))

 OBJS = $(C_O_FILES)
@@ -17,15 +17,8 @@ include $(top_srcdir)/../../../../../../automake/lib.am
 # (OPTIONAL) Add local stuff here using +=
 #

-$(PGM): $(OBJS)
-	$(make-rel)
-
 # the .rel file built here will be put into libbsp.a by ../wrapup/Makefile

-all-local: $(ARCH) $(OBJS) $(PGM)
-
-.PRECIOUS: $(PGM)
-
-EXTRA_DIST = clock.c
+all-local: $(ARCH) $(OBJS)

 include $(top_srcdir)/../../../../../../automake/local.am
--- a/c/src/lib/libbsp/powerpc/psim/clock/clock.c
+++ b/c/src/lib/libbsp/powerpc/psim/clock/clock.c
@@ -1,51 +0,0 @@
-/*
- *  Instantiate the clock driver shell for psim based
- *  on the decrementer register.
- *
- *  $Id$
- */
-
-#include <rtems.h>
-
-/*
- *  If defined, speed up the clock ticks while the idle task is running so
- *  time spent in the idle task is minimized.  This significantly reduces
- *  the wall time required to execute the RTEMS test suites.
- */
-
-/* #define CLOCK_DRIVER_USE_FAST_IDLE */
-
-#define CLOCK_VECTOR PPC_IRQ_DECREMENTER
-
-/*  On psim, each click of the decrementer register corresponds
- *  to 1 instruction.  By setting this to 100, we are indicating
- *  that we are assuming it can execute 100 instructions per
- *  microsecond.  This corresponds to sustaining 1 instruction
- *  per cycle at 100 Mhz.  Whether this is a good guess or not
- *  is anyone's guess.
- */
-
-extern int PSIM_INSTRUCTIONS_PER_MICROSECOND;
-
-unsigned int PPC_DECREMENTER_CLICKS;
-
-#define Clock_driver_support_install_isr( _new, _old ) \
-  do { \
-    _old = (rtems_isr_entry) set_vector( _new, CLOCK_VECTOR, 1 ); \
-    PPC_DECREMENTER_CLICKS = (unsigned int)&PSIM_INSTRUCTIONS_PER_MICROSECOND; \
-    PPC_DECREMENTER_CLICKS *= rtems_configuration_get_microseconds_per_tick(); \
-    /* PPC_DECREMENTER_CLICKS = 5000; */ \
-  } while(0)
-
-#define Clock_driver_support_initialize_hardware() \
-  do { \
-    unsigned int _clicks = PPC_DECREMENTER_CLICKS; \
-    PPC_Set_decrementer( _clicks ); \
-  } while (0)
-
-#define Clock_driver_support_at_tick() \
-  Clock_driver_support_initialize_hardware()
-
-#define Clock_driver_support_shutdown_hardware()
-
-#include "../../../shared/clockdrv_shell.c"
--- a/c/src/lib/libbsp/powerpc/psim/configure.ac
+++ b/c/src/lib/libbsp/powerpc/psim/configure.ac
@@ -38,6 +38,7 @@ AC_CONFIG_FILES([Makefile
 clock/Makefile
 console/Makefile
 include/Makefile
+irq/Makefile
 shmsupp/Makefile
 start/Makefile
 startup/Makefile
@@ -45,6 +46,6 @@ timer/Makefile
 vectors/Makefile
 wrapup/Makefile])

-RTEMS_PPC_EXCEPTIONS([old])
+RTEMS_PPC_EXCEPTIONS([new])

 AC_OUTPUT
--- a/c/src/lib/libbsp/powerpc/psim/include/bsp.h
+++ b/c/src/lib/libbsp/powerpc/psim/include/bsp.h
@@ -54,30 +54,39 @@ extern "C" {
 #else
 #include <rtems.h>
 #include <console.h>
+#include <libcpu/io.h>
 #include <clockdrv.h>
-#include <console.h>
 #include <iosupp.h>
-
-/*
- *  Define the time limits for RTEMS Test Suite test durations.
- *  Long test and short test duration limits are provided.  These
- *  values are in seconds and need to be converted to ticks for the
- *  application.
- *
- */
-
-#define MAX_LONG_TEST_DURATION       300 /* 5 minutes = 300 seconds */
-#define MAX_SHORT_TEST_DURATION      3   /* 3 seconds */
-
+#include <bsp/vectors.h>

 /*
 *  Stuff for Time Test 27
 */
+#if defined(RTEMS_TM27)
+
+#include <bsp/irq.h>

 #define MUST_WAIT_FOR_INTERRUPT 1

-#define Install_tm27_vector( _handler ) \
-  set_vector( (_handler), PPC_IRQ_DECREMENTER, 1 )
+/* #define Install_tm27_vector( _handler ) \
+   set_vector( (_handler), PPC_IRQ_DECREMENTER, 1 ) */
+
+void nullFunc() {}
+static rtems_irq_connect_data clockIrqData = {BSP_DECREMENTER,
+                                              0,
+                                              (rtems_irq_enable)nullFunc,
+                                              (rtems_irq_disable)nullFunc,
+                                              (rtems_irq_is_enabled) nullFunc};
+
+void Install_tm27_vector(void (*_handler)())
+{
+  clockIrqData.hdl = _handler;
+  if (!BSP_install_rtems_irq_handler (&clockIrqData)) {
+        printk("Error installing clock interrupt handler!\n");
+        rtems_fatal_error_occurred(1);
+  }
+}
+

 #define Cause_tm27_intr()  \
  do { \
@@ -100,6 +109,7 @@ extern "C" {
    _msr |=  0x8002; \
    asm volatile( "mtmsr %0 ;" : "=r" (_msr) : "r" (_msr) ); \
  } while (0)
+#endif

 /* Constants */

@@ -120,42 +130,29 @@ extern "C" {
 *  Information placed in the linkcmds file.
 */

-extern int   RAM_START;
 extern int   RAM_END;
-extern int   RAM_SIZE;
-
-extern int   PROM_START;
-extern int   PROM_END;
-extern int   PROM_SIZE;
-
-extern int   CLOCK_SPEED;
-
 extern int   end;        /* last address in the program */

+
+#define BSP_Convert_decrementer( _value ) ( (unsigned long long) _value ) 
+
+/* macros */
+#define Processor_Synchronize() \
+  asm(" eieio ")
+
 /* functions */

-void bsp_start( void );
-
-void bsp_cleanup( void );
-
 rtems_isr_entry set_vector(                    /* returns old vector */
  rtems_isr_entry     handler,                  /* isr routine        */
  rtems_vector_number vector,                   /* vector number      */
  int                 type                      /* RTEMS or RAW intr  */
 );

-void DEBUG_puts( char *string );
-
-void BSP_fatal_return( void );
-
-void bsp_spurious_initialize( void );
+void bsp_cleanup( void );

 extern rtems_configuration_table BSP_Configuration;     /* owned by BSP */
-
 extern rtems_cpu_table           Cpu_table;             /* owned by BSP */

-extern rtems_unsigned32          bsp_isr_level;
-
 #endif /* ASM */

 #ifdef __cplusplus
--- a/c/src/lib/libbsp/powerpc/psim/irq/.cvsignore
+++ b/c/src/lib/libbsp/powerpc/psim/irq/.cvsignore
@@ -0,0 +1 @@
+Makefile.in
--- a/c/src/lib/libbsp/powerpc/psim/irq/Makefile.am
+++ b/c/src/lib/libbsp/powerpc/psim/irq/Makefile.am
@@ -0,0 +1,41 @@
+##
+## Makefile.am,v 1.5 2002/12/17 13:37:41 ralf Exp
+##
+
+
+include_bspdir = $(includedir)/bsp
+
+C_FILES = irq.c irq_init.c
+OBJS = $(C_FILES:%.c=$(ARCH)/%.$(OBJEXT))
+
+include_bsp_HEADERS = irq.h
+
+S_FILES = irq_asm.S
+OBJS += $(S_FILES:%.S=$(ARCH)/%.$(OBJEXT))
+
+include $(top_srcdir)/../../../../../../automake/compile.am
+include $(top_srcdir)/../../../../../../automake/lib.am
+
+$(PROJECT_INCLUDE)/bsp:
+	$(mkinstalldirs) $@
+
+$(PROJECT_INCLUDE)/bsp/%.h: %.h
+	$(INSTALL_DATA) $< $@
+
+PREINSTALL_FILES = $(PROJECT_INCLUDE)/bsp \
+    $(include_bsp_HEADERS:%=$(PROJECT_INCLUDE)/bsp/%)
+
+#
+# (OPTIONAL) Add local stuff here using +=
+#
+
+$(PGM): $(OBJS)
+	$(make-rel)
+
+# the .rel file built here will be put into libbsp.a by ../wrapup/Makefile
+
+all-local: $(PREINSTALL_FILES) $(ARCH) $(OBJS) $(PGM)
+
+EXTRA_DIST = irq.c irq.h irq_asm.S irq_init.c
+
+include $(top_srcdir)/../../../../../../automake/local.am
--- a/c/src/lib/libbsp/powerpc/psim/irq/irq.c
+++ b/c/src/lib/libbsp/powerpc/psim/irq/irq.c
@@ -0,0 +1,361 @@
+/*
+ *
+ *  This file contains the implementation of the function described in irq.h
+ *
+ *  Copyright (C) 1998, 1999 valette@crf.canon.fr
+ *
+ *  The license and distribution terms for this file may be
+ *  found in found in the file LICENSE in this distribution or at
+ *  http://www.rtems.com/license/LICENSE.
+ *
+ *  irq.c,v 1.4.2.8 2003/09/04 18:45:20 joel Exp
+ */
+  
+#include <rtems/system.h>
+#include <bsp.h>
+#include <bsp/irq.h>
+#if 0
+#include <bsp/VME.h>
+#include <bsp/openpic.h>
+#endif
+#include <stdlib.h>
+
+#include <rtems/score/thread.h>
+#include <rtems/score/apiext.h>
+#include <libcpu/raw_exception.h>
+#include <libcpu/io.h>
+#include <bsp/vectors.h>
+
+#include <rtems/bspIo.h> /* for printk */
+#define RAVEN_INTR_ACK_REG 0xfeff0030
+
+/*
+ * pointer to the mask representing the additionnal irq vectors
+ * that must be disabled when a particular entry is activated.
+ * They will be dynamically computed from teh prioruty table given
+ * in BSP_rtems_irq_mngt_set();
+ * CAUTION : this table is accessed directly by interrupt routine
+ * 	     prologue.
+ */
+rtems_i8259_masks 	irq_mask_or_tbl[BSP_IRQ_NUMBER];
+/*
+ * default handler connected on each irq after bsp initialization
+ */
+static rtems_irq_connect_data	default_rtems_entry;
+
+/*
+ * location used to store initial tables used for interrupt
+ * management.
+ */
+static rtems_irq_global_settings* 	internal_config;
+static rtems_irq_connect_data*		rtems_hdl_tbl;
+
+/*
+ * Check if IRQ is an ISA IRQ
+ */
+static inline int is_isa_irq(const rtems_irq_symbolic_name irqLine)
+{
+  return (((int) irqLine <= BSP_ISA_IRQ_MAX_OFFSET) &
+	  ((int) irqLine >= BSP_ISA_IRQ_LOWEST_OFFSET)
+	 );
+}
+
+/*
+ * Check if IRQ is an OPENPIC IRQ
+ */
+static inline int is_pci_irq(const rtems_irq_symbolic_name irqLine)
+{
+  return (((int) irqLine <= BSP_PCI_IRQ_MAX_OFFSET) &
+	  ((int) irqLine >= BSP_PCI_IRQ_LOWEST_OFFSET)
+	 );
+}
+
+/*
+ * Check if IRQ is a Porcessor IRQ
+ */
+static inline int is_processor_irq(const rtems_irq_symbolic_name irqLine)
+{
+  return (((int) irqLine <= BSP_PROCESSOR_IRQ_MAX_OFFSET) &
+	  ((int) irqLine >= BSP_PROCESSOR_IRQ_LOWEST_OFFSET)
+	 );
+}
+
+
+/*
+ * ------------------------ RTEMS Irq helper functions ----------------
+ */
+ 
+/*
+ * Caution : this function assumes the variable "internal_config"
+ * is already set and that the tables it contains are still valid
+ * and accessible.
+ */
+static void compute_i8259_masks_from_prio ()
+{
+  int i;
+  int j;
+  /*
+   * Always mask at least current interrupt to prevent re-entrance
+   */
+  for (i=BSP_ISA_IRQ_LOWEST_OFFSET; i < BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER; i++) {
+    * ((unsigned short*) &irq_mask_or_tbl[i]) = (1 << i);
+    for (j = BSP_ISA_IRQ_LOWEST_OFFSET; j < BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER; j++) {
+      /*
+       * Mask interrupts at i8259 level that have a lower priority
+       */
+      if (internal_config->irqPrioTbl [i] > internal_config->irqPrioTbl [j]) {
+	* ((unsigned short*) &irq_mask_or_tbl[i]) |= (1 << j);
+      }
+    }
+  }
+}
+
+/*
+ * This function check that the value given for the irq line
+ * is valid.
+ */
+
+static int isValidInterrupt(int irq)
+{
+  if ( (irq < BSP_LOWEST_OFFSET) || (irq > BSP_MAX_OFFSET))
+    return 0;
+  return 1;
+}
+
+
+/*
+ * ------------------------ RTEMS Shared Irq Handler Mngt Routines ----------------
+ */
+int BSP_install_rtems_shared_irq_handler  (const rtems_irq_connect_data* irq)
+{
+  printk("BSP_insall_rtems_shared_irq_handler Not supported in psim\n");
+  return 0;
+}
+
+
+/*
+ * ------------------------ RTEMS Single Irq Handler Mngt Routines ----------------
+ */
+
+int BSP_install_rtems_irq_handler  (const rtems_irq_connect_data* irq)
+{
+    unsigned int level;
+  
+    if (!isValidInterrupt(irq->name)) {
+      printk("Invalid interrupt vector %d\n",irq->name);
+      return 0;
+    }
+    /*
+     * Check if default handler is actually connected. If not issue an error.
+     * You must first get the current handler via i386_get_current_idt_entry
+     * and then disconnect it using i386_delete_idt_entry.
+     * RATIONALE : to always have the same transition by forcing the user
+     * to get the previous handler before accepting to disconnect.
+     */
+    _CPU_ISR_Disable(level);
+    if (rtems_hdl_tbl[irq->name].hdl != default_rtems_entry.hdl) {
+      _CPU_ISR_Enable(level);
+      printk("IRQ vector %d already connected\n",irq->name);
+      return 0;
+    }
+
+    /*
+     * store the data provided by user
+     */
+    rtems_hdl_tbl[irq->name] = *irq;
+    rtems_hdl_tbl[irq->name].next_handler = (void *)-1;
+    
+    if (is_isa_irq(irq->name)) {
+      printk("What's a isa_irq on psim?");
+    }
+
+    if (is_processor_irq(irq->name)) {
+      /*
+       * Enable exception at processor level
+       */
+    }
+    /*
+     * Enable interrupt on device
+     */
+    irq->on(irq);
+    
+    _CPU_ISR_Enable(level);
+
+    return 1;
+}
+
+
+int BSP_get_current_rtems_irq_handler	(rtems_irq_connect_data* irq)
+{
+     unsigned int level;
+
+     if (!isValidInterrupt(irq->name)) {
+      return 0;
+     }
+     _CPU_ISR_Disable(level);
+     *irq = rtems_hdl_tbl[irq->name];
+     _CPU_ISR_Enable(level);
+     return 1;
+}
+
+int BSP_remove_rtems_irq_handler  (const rtems_irq_connect_data* irq)
+{
+   rtems_irq_connect_data *pchain= NULL, *vchain = NULL;
+    unsigned int level;
+  
+    if (!isValidInterrupt(irq->name)) {
+      return 0;
+    }
+    /*
+     * Check if default handler is actually connected. If not issue an error.
+     * You must first get the current handler via i386_get_current_idt_entry
+     * and then disconnect it using i386_delete_idt_entry.
+     * RATIONALE : to always have the same transition by forcing the user
+     * to get the previous handler before accepting to disconnect.
+     */
+    _CPU_ISR_Disable(level);
+    if (rtems_hdl_tbl[irq->name].hdl != irq->hdl) {
+      _CPU_ISR_Enable(level);
+      return 0;
+    }
+
+    if( (int)rtems_hdl_tbl[irq->name].next_handler != -1 )
+    {
+       int found = 0;
+
+       for( (pchain= NULL, vchain = &rtems_hdl_tbl[irq->name]);
+            (vchain->hdl != default_rtems_entry.hdl);
+            (pchain= vchain, vchain = (rtems_irq_connect_data*)vchain->next_handler) )
+       {
+          if( vchain->hdl == irq->hdl )
+          {
+             found= -1; break;
+          }
+       }
+
+       if( !found )
+       {
+          _CPU_ISR_Enable(level);
+          return 0;
+       }
+    }
+    else
+    {
+       if (rtems_hdl_tbl[irq->name].hdl != irq->hdl) 
+       {
+          _CPU_ISR_Enable(level);
+         return 0;
+       }
+    }
+
+    if (is_isa_irq(irq->name)) {
+      printk("isa irq on psim?");
+    }
+    if (is_processor_irq(irq->name)) {
+      /*
+       * disable exception at processor level
+       */
+    }    
+
+    /*
+     * Disable interrupt on device
+     */
+    irq->off(irq);
+
+    /*
+     * restore the default irq value
+     */
+    if( !vchain )
+    {
+       /* single handler vector... */
+       rtems_hdl_tbl[irq->name] = default_rtems_entry;
+    }
+    else
+    {
+       if( pchain )
+       {
+          /* non-first handler being removed */
+          pchain->next_handler = vchain->next_handler;
+       }
+       else
+       {
+          /* first handler isn't malloc'ed, so just overwrite it.  Since
+          the contents of vchain are being struct copied, vchain itself
+          goes away */
+          rtems_hdl_tbl[irq->name]= *vchain;
+       }
+       free(vchain);
+    }
+
+    _CPU_ISR_Enable(level);
+
+    return 1;
+}
+
+/*
+ * ------------------------ RTEMS Global Irq Handler Mngt Routines ----------------
+ */
+
+int BSP_rtems_irq_mngt_set(rtems_irq_global_settings* config)
+{
+   /*
+    * Store various code accelerators
+    */
+    internal_config 		= config;
+    default_rtems_entry 	= config->defaultEntry;
+    rtems_hdl_tbl 		= config->irqHdlTbl;
+    
+    return 1;
+}
+
+int BSP_rtems_irq_mngt_get(rtems_irq_global_settings** config)
+{
+    *config = internal_config;
+    return 0;
+}    
+
+int _BSP_vme_bridge_irq = -1;
+ 
+unsigned BSP_spuriousIntr = 0;
+
+/*
+ * High level IRQ handler called from shared_raw_irq_code_entry
+ */
+void C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum)
+{
+  register unsigned msr;
+  register unsigned new_msr;
+
+  if (excNum == ASM_DEC_VECTOR) {
+    _CPU_MSR_GET(msr);
+    new_msr = msr | MSR_EE;
+    _CPU_MSR_SET(new_msr);
+    
+    rtems_hdl_tbl[BSP_DECREMENTER].hdl();
+
+    _CPU_MSR_SET(msr);
+    return;
+    
+  }
+}
+    
+    
+  
+void _ThreadProcessSignalsFromIrq (BSP_Exception_frame* ctx)
+{
+  /*
+   * Process pending signals that have not already been
+   * processed by _Thread_Displatch. This happens quite
+   * unfrequently : the ISR must have posted an action
+   * to the current running thread.
+   */
+  if ( _Thread_Do_post_task_switch_extension ||
+       _Thread_Executing->do_post_task_switch_extension ) {
+    _Thread_Executing->do_post_task_switch_extension = FALSE;
+    _API_extensions_Run_postswitch();
+  }
+  /*
+   * I plan to process other thread related events here.
+   * This will include DEBUG session requested from keyboard...
+   */
+}
--- a/c/src/lib/libbsp/powerpc/psim/irq/irq.h
+++ b/c/src/lib/libbsp/powerpc/psim/irq/irq.h
@@ -0,0 +1,333 @@
+/* irq.h
+ *
+ *  This include file describe the data structure and the functions implemented
+ *  by rtems to write interrupt handlers.
+ *
+ *  CopyRight (C) 1999 valette@crf.canon.fr
+ *
+ *  This code is heavilly inspired by the public specification of STREAM V2
+ *  that can be found at :
+ *
+ *      <http://www.chorus.com/Documentation/index.html> by following
+ *  the STREAM API Specification Document link.
+ *
+ *  The license and distribution terms for this file may be
+ *  found in found in the file LICENSE in this distribution or at
+ *  http://www.rtems.com/license/LICENSE.
+ *
+ *  irq.h,v 1.2.4.2 2003/09/04 18:45:20 joel Exp
+ */
+
+#ifndef LIBBSP_POWERPC_MCP750_IRQ_IRQ_H
+#define LIBBSP_POWERPC_MCP750_IRQ_IRQ_H
+
+
+/*
+ * 8259 edge/level control definitions at VIA
+ */
+#define ISA8259_M_ELCR 		0x4d0
+#define ISA8259_S_ELCR 		0x4d1
+
+#define ELCRS_INT15_LVL         0x80
+#define ELCRS_INT14_LVL         0x40
+#define ELCRS_INT13_LVL         0x20
+#define ELCRS_INT12_LVL         0x10
+#define ELCRS_INT11_LVL         0x08
+#define ELCRS_INT10_LVL         0x04
+#define ELCRS_INT9_LVL          0x02
+#define ELCRS_INT8_LVL          0x01
+#define ELCRM_INT7_LVL          0x80
+#define ELCRM_INT6_LVL          0x40
+#define ELCRM_INT5_LVL          0x20
+#define ELCRM_INT4_LVL          0x10
+#define ELCRM_INT3_LVL          0x8
+#define ELCRM_INT2_LVL          0x4
+#define ELCRM_INT1_LVL          0x2
+#define ELCRM_INT0_LVL          0x1
+
+#define BSP_ASM_IRQ_VECTOR_BASE 0x0
+    /* PIC's command and mask registers */
+#define PIC_MASTER_COMMAND_IO_PORT		0x20	/* Master PIC command register */
+#define PIC_SLAVE_COMMAND_IO_PORT		0xa0	/* Slave PIC command register */
+#define PIC_MASTER_IMR_IO_PORT			0x21	/* Master PIC Interrupt Mask Register */
+#define PIC_SLAVE_IMR_IO_PORT		 	0xa1	/* Slave PIC Interrupt Mask Register */
+
+    /* Command for specific EOI (End Of Interrupt): Interrupt acknowledge */
+#define PIC_EOSI	0x60	/* End of Specific Interrupt (EOSI) */
+#define	SLAVE_PIC_EOSI  0x62	/* End of Specific Interrupt (EOSI) for cascade */
+#define PIC_EOI		0x20	/* Generic End of Interrupt (EOI) */
+
+#ifndef ASM
+
+
+/*
+ * Symblolic IRQ names and related definitions.
+ */
+
+typedef enum {
+  /* Base vector for our ISA IRQ handlers. */
+  BSP_ISA_IRQ_VECTOR_BASE	=	BSP_ASM_IRQ_VECTOR_BASE,
+  /*
+   * ISA IRQ handler related definitions
+   */
+  BSP_ISA_IRQ_NUMBER    	= 	16,
+  BSP_ISA_IRQ_LOWEST_OFFSET	= 	0,
+  BSP_ISA_IRQ_MAX_OFFSET	= 	BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER - 1,
+  /*
+   * PCI IRQ handlers related definitions
+   * CAUTION : BSP_PCI_IRQ_LOWEST_OFFSET should be equal to OPENPIC_VEC_SOURCE
+   */
+  BSP_PCI_IRQ_NUMBER		=	16,
+  BSP_PCI_IRQ_LOWEST_OFFSET	=	BSP_ISA_IRQ_NUMBER,
+  BSP_PCI_IRQ_MAX_OFFSET	= 	BSP_PCI_IRQ_LOWEST_OFFSET + BSP_PCI_IRQ_NUMBER - 1,
+  /*
+   * PowerPc exceptions handled as interrupt where a rtems managed interrupt
+   * handler might be connected
+   */
+  BSP_PROCESSOR_IRQ_NUMBER	=	1,
+  BSP_PROCESSOR_IRQ_LOWEST_OFFSET = 	BSP_PCI_IRQ_MAX_OFFSET + 1,
+  BSP_PROCESSOR_IRQ_MAX_OFFSET	=	BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER - 1,
+  /* Misc vectors for OPENPIC irqs (IPI, timers)
+   */
+  BSP_MISC_IRQ_NUMBER		=	8,
+  BSP_MISC_IRQ_LOWEST_OFFSET	=	BSP_PROCESSOR_IRQ_MAX_OFFSET + 1,
+  BSP_MISC_IRQ_MAX_OFFSET	=	BSP_MISC_IRQ_LOWEST_OFFSET + BSP_MISC_IRQ_NUMBER - 1,
+  /*
+   * Summary
+   */
+  BSP_IRQ_NUMBER		= 	BSP_MISC_IRQ_MAX_OFFSET + 1,
+  BSP_LOWEST_OFFSET		=	BSP_ISA_IRQ_LOWEST_OFFSET,
+  BSP_MAX_OFFSET		=	BSP_MISC_IRQ_MAX_OFFSET,
+    /*
+     * Some ISA IRQ symbolic name definition
+     */	       
+  BSP_ISA_PERIODIC_TIMER      	= 	0,
+
+  BSP_ISA_KEYBOARD          	= 	1,
+
+  BSP_ISA_UART_COM2_IRQ		=	3,
+
+  BSP_ISA_UART_COM1_IRQ		=	4,
+
+  BSP_ISA_RT_TIMER1	      	= 	8,
+  
+  BSP_ISA_RT_TIMER3		= 	10,
+    /*
+     * Some PCI IRQ symbolic name definition
+     */
+  BSP_PCI_IRQ0			=	BSP_PCI_IRQ_LOWEST_OFFSET,
+  BSP_PCI_ISA_BRIDGE_IRQ	=	BSP_PCI_IRQ0,
+    /*
+     * Some Processor execption handled as rtems IRQ symbolic name definition
+     */
+  BSP_DECREMENTER		=	BSP_PROCESSOR_IRQ_LOWEST_OFFSET
+  
+}rtems_irq_symbolic_name;
+
+    
+
+
+/*
+ * Type definition for RTEMS managed interrupts
+ */
+typedef unsigned char  rtems_irq_prio;
+typedef unsigned short rtems_i8259_masks;
+
+extern  volatile rtems_i8259_masks i8259s_cache;
+
+struct 	__rtems_irq_connect_data__;	/* forward declaratiuon */
+
+typedef void (*rtems_irq_hdl)		(void);
+typedef void (*rtems_irq_enable)	(const struct __rtems_irq_connect_data__*);
+typedef void (*rtems_irq_disable)	(const struct __rtems_irq_connect_data__*);
+typedef int  (*rtems_irq_is_enabled)	(const struct __rtems_irq_connect_data__*);
+
+typedef struct __rtems_irq_connect_data__ {
+      /*
+       * IRQ line
+       */
+      rtems_irq_symbolic_name 	name;
+      /*
+       * handler. See comment on handler properties below in function prototype.
+       */
+      rtems_irq_hdl	   		hdl;
+      /*
+       * function for enabling interrupts at device level (ONLY!).
+       * The BSP code will automatically enable it at i8259s level and openpic level.
+       * RATIONALE : anyway such code has to exist in current driver code.
+       * It is usually called immediately AFTER connecting the interrupt handler.
+       * RTEMS may well need such a function when restoring normal interrupt
+       * processing after a debug session.
+       * 
+       */
+      rtems_irq_enable		on;	
+      /*
+       * function for disabling interrupts at device level (ONLY!).
+       * The code will disable it at i8259s level. RATIONALE : anyway
+       * such code has to exist for clean shutdown. It is usually called
+       * BEFORE disconnecting the interrupt. RTEMS may well need such
+       * a function when disabling normal interrupt processing for
+       * a debug session. May well be a NOP function.
+       */
+      rtems_irq_disable		off;
+      /*
+       * function enabling to know what interrupt may currently occur
+       * if someone manipulates the i8259s interrupt mask without care...
+       */
+      rtems_irq_is_enabled	isOn;
+      /*
+       *  Set to -1 for vectors forced to have only 1 handler
+       */
+      void *next_handler;
+
+}rtems_irq_connect_data;
+
+typedef struct {
+  /*
+   * size of all the table fields (*Tbl) described below.
+   */
+  unsigned int	 		irqNb;
+  /*
+   * Default handler used when disconnecting interrupts.
+   */
+  rtems_irq_connect_data	defaultEntry;
+  /*
+   * Table containing initials/current value.
+   */
+  rtems_irq_connect_data*	irqHdlTbl;
+  /*
+   * actual value of BSP_ISA_IRQ_VECTOR_BASE...
+   */
+  rtems_irq_symbolic_name	irqBase;
+  /*
+   * software priorities associated with interrupts.
+   * if irqPrio  [i]  >  intrPrio  [j]  it  means  that  
+   * interrupt handler hdl connected for interrupt name i
+   * will  not be interrupted by the handler connected for interrupt j
+   * The interrupt source  will be physically masked at i8259 level.
+   */
+    rtems_irq_prio*		irqPrioTbl;
+}rtems_irq_global_settings;
+
+
+
+
+/*-------------------------------------------------------------------------+
+| Function Prototypes.
+--------------------------------------------------------------------------*/
+/*
+ * ------------------------ Intel 8259 (or emulation) Mngt Routines -------
+ */
+
+/*
+ * function to disable a particular irq at 8259 level. After calling
+ * this function, even if the device asserts the interrupt line it will
+ * not be propagated further to the processor
+ */
+int BSP_irq_disable_at_i8259s        (const rtems_irq_symbolic_name irqLine);
+/*
+ * function to enable a particular irq at 8259 level. After calling
+ * this function, if the device asserts the interrupt line it will
+ * be propagated further to the processor
+ */
+int BSP_irq_enable_at_i8259s		(const rtems_irq_symbolic_name irqLine);
+/*
+ * function to acknoledge a particular irq at 8259 level. After calling
+ * this function, if a device asserts an enabled interrupt line it will
+ * be propagated further to the processor. Mainly usefull for people
+ * writting raw handlers as this is automagically done for rtems managed
+ * handlers.
+ */
+int BSP_irq_ack_at_i8259s           	(const rtems_irq_symbolic_name irqLine);
+/*
+ * function to check if a particular irq is enabled at 8259 level. After calling
+ */
+int BSP_irq_enabled_at_i8259s        	(const rtems_irq_symbolic_name irqLine);
+/*
+ * ------------------------ RTEMS Single Irq Handler Mngt Routines ----------------
+ */
+/*
+ * function to connect a particular irq handler. This hanlder will NOT be called
+ * directly as the result of the corresponding interrupt. Instead, a RTEMS
+ * irq prologue will be called that will :
+ *
+ *	1) save the C scratch registers,
+ *	2) switch to a interrupt stack if the interrupt is not nested,
+ *	3) store the current i8259s' interrupt masks
+ *	4) modify them to disable the current interrupt at 8259 level (and may
+ *	be others depending on software priorities)
+ *	5) aknowledge the i8259s',
+ *	6) demask the processor,
+ *	7) call the application handler
+ *
+ * As a result the hdl function provided
+ *
+ *	a) can perfectly be written is C,
+ * 	b) may also well directly call the part of the RTEMS API that can be used
+ *	from interrupt level,
+ *	c) It only responsible for handling the jobs that need to be done at
+ *	the device level including (aknowledging/re-enabling the interrupt at device,
+ *	level, getting the data,...)
+ *
+ *	When returning from the function, the following will be performed by
+ *	the RTEMS irq epilogue :
+ *
+ *	1) masks the interrupts again,
+ *	2) restore the original i8259s' interrupt masks
+ *	3) switch back on the orinal stack if needed,
+ *	4) perform rescheduling when necessary,
+ *	5) restore the C scratch registers...
+ *	6) restore initial execution flow
+ * 
+ */
+int BSP_install_rtems_irq_handler   	(const rtems_irq_connect_data*);
+int BSP_install_rtems_shared_irq_handler  (const rtems_irq_connect_data*);
+
+#define BSP_SHARED_HANDLER_SUPPORT      1
+
+/*
+ * function to get the current RTEMS irq handler for ptr->name. It enables to
+ * define hanlder chain...
+ */
+int BSP_get_current_rtems_irq_handler	(rtems_irq_connect_data* ptr);
+/*
+ * function to get disconnect the RTEMS irq handler for ptr->name.
+ * This function checks that the value given is the current one for safety reason.
+ * The user can use the previous function to get it.
+ */
+int BSP_remove_rtems_irq_handler    	(const rtems_irq_connect_data*);
+
+/*
+ * ------------------------ RTEMS Global Irq Handler Mngt Routines ----------------
+ */
+/*
+ * (Re) Initialize the RTEMS interrupt management.
+ *
+ * The result of calling this function will be the same as if each individual
+ * handler (config->irqHdlTbl[i].hdl)  different from "config->defaultEntry.hdl"
+ * has been individualy connected via
+ *	BSP_install_rtems_irq_handler(&config->irqHdlTbl[i])
+ * And each handler currently equal to config->defaultEntry.hdl
+ * has been previously disconnected via
+ * 	 BSP_remove_rtems_irq_handler (&config->irqHdlTbl[i])
+ *
+ * This is to say that all information given will be used and not just
+ * only the space.
+ *
+ * CAUTION : the various table address contained in config will be used
+ *	     directly by the interrupt mangement code in order to save
+ *	     data size so they must stay valid after the call => they should
+ *	     not be modified or declared on a stack.
+ */
+
+int BSP_rtems_irq_mngt_set(rtems_irq_global_settings* config);
+/*
+ * (Re) get info on current RTEMS interrupt management.
+ */
+int BSP_rtems_irq_mngt_get(rtems_irq_global_settings**);
+  
+extern void BSP_rtems_irq_mng_init(unsigned cpuId);
+extern void BSP_i8259s_init(void);
+#endif
+
+#endif
--- a/c/src/lib/libbsp/powerpc/psim/irq/irq_asm.S
+++ b/c/src/lib/libbsp/powerpc/psim/irq/irq_asm.S
@@ -0,0 +1,357 @@
+/*
+ *  This file contains the assembly code for the PowerPC 
+ *  IRQ veneers for RTEMS.
+ *
+ *  The license and distribution terms for this file may be
+ *  found in found in the file LICENSE in this distribution or at
+ *  http://www.rtems.com/license/LICENSE.
+ *
+ *  Modified to support the MCP750.
+ *  Modifications Copyright (C) 1999 Eric Valette. valette@crf.canon.fr
+ *
+ *  Till Straumann <strauman@slac.stanford.edu>, 2003/7:
+ *    - store isr nesting level in _ISR_Nest_level rather than
+ *      SPRG0 - RTEMS relies on that variable.
+ *
+ * irq_asm.S,v 1.5.4.3 2003/09/04 18:45:20 joel Exp
+ */
+  	
+#include <asm.h>
+#include <rtems/score/cpu.h>
+#include <bsp/vectors.h>
+#include <libcpu/raw_exception.h>
+	
+
+#define SYNC \
+	sync; \
+	isync
+	
+	.text
+	.p2align 5	
+		
+	PUBLIC_VAR(decrementer_exception_vector_prolog_code)
+	
+SYM (decrementer_exception_vector_prolog_code):
+	/*
+	 * let room for exception frame
+	 */
+	stwu    r1, - (EXCEPTION_FRAME_END)(r1)
+	stw	r4, GPR4_OFFSET(r1)
+	li	r4, ASM_DEC_VECTOR
+	ba	shared_raw_irq_code_entry
+
+	PUBLIC_VAR (decrementer_exception_vector_prolog_code_size)
+	
+	decrementer_exception_vector_prolog_code_size = . - decrementer_exception_vector_prolog_code
+
+	PUBLIC_VAR(external_exception_vector_prolog_code)
+	
+SYM (external_exception_vector_prolog_code):
+	/*
+	 * let room for exception frame
+	 */
+	stwu    r1, - (EXCEPTION_FRAME_END)(r1)
+	stw	r4, GPR4_OFFSET(r1)
+	li	r4, ASM_EXT_VECTOR
+	ba	shared_raw_irq_code_entry
+
+	PUBLIC_VAR (external_exception_vector_prolog_code_size)
+	
+	external_exception_vector_prolog_code_size = . - external_exception_vector_prolog_code
+
+	PUBLIC_VAR(shared_raw_irq_code_entry)
+	PUBLIC_VAR(C_dispatch_irq_handler)
+	
+	.p2align 5
+SYM (shared_raw_irq_code_entry):
+	/*
+	 * Entry conditions :
+	 *	Registers already saved : R1, R4
+	 *	R1  :	points to a location with enough room for the
+	 *	        interrupt frame
+	 *	R4  :	vector number
+	 */
+	/*
+	 * Save SRR0/SRR1 As soon As possible as it is the minimal needed 
+	 * to reenable exception processing
+	 */
+	stw	r0, GPR0_OFFSET(r1)
+	/* PPC EABI: R2 is reserved (pointer to short data .sdata2) - we won't touch it
+	 * but we still save/restore it, just in case...
+	 */
+	stw	r2, GPR2_OFFSET(r1)
+	stw	r3, GPR3_OFFSET(r1)
+	
+	mfsrr0  r0
+	mfsrr1  r3
+	
+	stw	r0, SRR0_FRAME_OFFSET(r1)
+	stw	r3, SRR1_FRAME_OFFSET(r1)
+
+	mfmsr	r3
+	/*
+	 * Enable data and instruction address translation, exception recovery
+     *
+     * also, on CPUs with FP, enable FP so that FP context can be
+     * saved and restored (using FP instructions)
+	 */
+#if (PPC_HAS_FPU == 0)
+	ori     r3, r3, MSR_RI | MSR_IR | MSR_DR
+#else
+	ori     r3, r3, MSR_RI | MSR_FP  /* MSR_IR | MSR_DR */
+#endif
+	mtmsr   r3
+	SYNC
+	/*
+	 * Push C scratch registers on the current stack. It may
+	 * actually be the thread stack or the interrupt stack.
+	 * Anyway we have to make it in order to be able to call C/C++
+	 * functions. Depending on the nesting interrupt level, we will
+	 * switch to the right stack later.
+	 */
+	stw	r5, GPR5_OFFSET(r1)
+	stw	r6, GPR6_OFFSET(r1)
+	stw	r7, GPR7_OFFSET(r1)
+	stw	r8, GPR8_OFFSET(r1)
+	stw	r9, GPR9_OFFSET(r1)
+	stw	r10, GPR10_OFFSET(r1)
+	stw	r11, GPR11_OFFSET(r1)
+	stw	r12, GPR12_OFFSET(r1)
+	stw	r13, GPR13_OFFSET(r1)
+
+	mfcr	r5
+	mfctr	r6
+	mfxer	r7
+	mflr	r8
+	
+	stw	r5,  EXC_CR_OFFSET(r1)
+	stw	r6,  EXC_CTR_OFFSET(r1)
+	stw	r7,  EXC_XER_OFFSET(r1)
+	stw	r8,  EXC_LR_OFFSET(r1)
+
+	/*
+	 * Add some non volatile registers to store information
+	 * that will be used when returning from C handler
+	 */
+	stw	r14, GPR14_OFFSET(r1)
+	stw	r15, GPR15_OFFSET(r1)
+	/*
+	 * save current stack pointer location in R14
+	 */
+	addi	r14, r1, 0
+	/*
+	 * store part of _Thread_Dispatch_disable_level address in R15
+	 */
+	addis r15,0, _Thread_Dispatch_disable_level@ha
+#if BROKEN_ISR_NEST_LEVEL
+	/*
+	 * Get current nesting level in R3
+	 */
+	mfspr	r3, SPRG0
+#else
+	/*
+	 * Retrieve current nesting level from _ISR_Nest_level
+	 */
+	lis		r7, _ISR_Nest_level@ha
+	lwz		r3, _ISR_Nest_level@l(r7)
+#endif
+	/*
+	 * Check if stack switch is necessary
+	 */
+	cmpwi	r3,0
+	bne	nested
+	mfspr	r1, SPRG1
+	
+nested:	
+	/* 
+	 * Start Incrementing nesting level in R3
+	 */
+	addi	r3,r3,1
+	/*
+	 * Start Incrementing _Thread_Dispatch_disable_level R4 = _Thread_Dispatch_disable_level
+	 */
+	lwz	r6,_Thread_Dispatch_disable_level@l(r15)
+#if BROKEN_ISR_NEST_LEVEL
+	/*
+	 * Store new nesting level in SPRG0
+	 */
+	mtspr	SPRG0, r3
+#else
+	/* store new nesting level in _ISR_Nest_level */
+	stw		r3, _ISR_Nest_level@l(r7)
+#endif
+	
+	addi	r6, r6, 1
+	mfmsr	r5
+	/*
+	 * store new _Thread_Dispatch_disable_level value
+	 */
+	stw	r6, _Thread_Dispatch_disable_level@l(r15)
+	/*
+	 * We are now running on the interrupt stack. External and decrementer
+	 * exceptions are still disabled. I see no purpose trying to optimize
+	 * further assembler code. 
+	 */
+	/*
+	 * Call C exception handler for decrementer Interrupt frame is passed just
+	 * in case...
+	 */
+	addi	r3, r14, 0x8
+	bl	C_dispatch_irq_handler /* C_dispatch_irq_handler(cpu_interrupt_frame* r3, vector r4) */
+	/*
+	 * start decrementing nesting level. Note : do not test result against 0 
+	 * value as an easy exit condition because if interrupt nesting level > 1
+	 * then _Thread_Dispatch_disable_level > 1
+	 */
+#if BROKEN_ISR_NEST_LEVEL
+	mfspr	r4, SPRG0
+#else
+	lis		r7, _ISR_Nest_level@ha
+	lwz		r4, _ISR_Nest_level@l(r7)
+#endif
+	/*
+	 * start decrementing _Thread_Dispatch_disable_level
+	 */
+	lwz	r3,_Thread_Dispatch_disable_level@l(r15)
+	addi	r4, r4, -1	/* Continue decrementing nesting level */
+	addi	r3, r3, -1	/* Continue decrementing _Thread_Dispatch_disable_level */
+#if BROKEN_ISR_NEST_LEVEL
+	mtspr	SPRG0, r4	/* End decrementing nesting level */
+#else
+	stw		r4, _ISR_Nest_level@l(r7) /* End decrementing nesting level */
+#endif
+	stw	r3,_Thread_Dispatch_disable_level@l(r15) /* End decrementing _Thread_Dispatch_disable_level */
+	cmpwi	r3, 0
+	/*
+	 * switch back to original stack (done here just optimize registers 
+	 * contention. Could have been done before...)
+	 */
+	addi	r1, r14, 0
+	bne	easy_exit /* if (_Thread_Dispatch_disable_level != 0) goto easy_exit */
+	/*
+	 * Here we are running again on the thread system stack.
+	 * We have interrupt nesting level = _Thread_Dispatch_disable_level = 0.
+	 * Interrupt are still disabled. Time to check if scheduler request to 
+	 * do something with the current thread...
+	 */
+	addis	r4, 0, _Context_Switch_necessary@ha
+	lwz	r5, _Context_Switch_necessary@l(r4)
+	cmpwi	r5, 0
+	bne	switch
+	
+	addis	r6, 0, _ISR_Signals_to_thread_executing@ha
+	lwz	r7, _ISR_Signals_to_thread_executing@l(r6)
+	cmpwi	r7, 0
+	li	r8, 0
+	beq	easy_exit
+	stw	r8, _ISR_Signals_to_thread_executing@l(r6)
+	/*
+	 * going to call _ThreadProcessSignalsFromIrq
+	 * Push a complete exception like frame...
+	 */
+	stmw	r16, GPR16_OFFSET(r1)
+	addi	r3, r1, 0x8
+	/*
+	 * compute SP at exception entry
+	 */
+	addi    r4, r1, EXCEPTION_FRAME_END
+	/*
+	 * store it at the right place
+	 */
+	stw     r4, GPR1_OFFSET(r1)
+	/*
+	 * Call High Level signal handling code
+	 */
+	bl	_ThreadProcessSignalsFromIrq
+	/*
+	 * start restoring exception like frame
+	 */
+	lwz	r31,  EXC_CTR_OFFSET(r1)
+	lwz	r30,  EXC_XER_OFFSET(r1)
+	lwz	r29,  EXC_CR_OFFSET(r1)
+	lwz	r28,  EXC_LR_OFFSET(r1)
+	
+	mtctr	r31
+	mtxer	r30
+	mtcr	r29
+	mtlr	r28
+	
+	lmw	r4, GPR4_OFFSET(r1)
+	lwz	r2, GPR2_OFFSET(r1)
+	lwz	r0, GPR0_OFFSET(r1)
+
+	/*
+	 * Disable data and instruction translation. Make path non recoverable...
+	 */
+	mfmsr	r3
+	xori	r3, r3, MSR_RI /* | MSR_IR | MSR_DR */
+	mtmsr   r3
+	SYNC
+	/*
+	 * Restore rfi related settings
+	 */
+		 
+	lwz	r3, SRR1_FRAME_OFFSET(r1)
+	mtsrr1	r3
+	lwz	r3, SRR0_FRAME_OFFSET(r1)
+	mtsrr0	r3
+	
+	lwz	r3, GPR3_OFFSET(r1)
+	addi 	r1,r1, EXCEPTION_FRAME_END
+	SYNC
+	rfi
+	
+switch:
+	bl	SYM (_Thread_Dispatch)
+	
+easy_exit:	
+	/*
+	 * start restoring interrupt frame
+	 */
+	lwz	r3,  EXC_CTR_OFFSET(r1)
+	lwz	r4,  EXC_XER_OFFSET(r1)
+	lwz	r5,  EXC_CR_OFFSET(r1)
+	lwz	r6,  EXC_LR_OFFSET(r1)
+	
+	mtctr	r3
+	mtxer	r4
+	mtcr	r5
+	mtlr	r6
+
+	lwz	r15, GPR15_OFFSET(r1)
+	lwz	r14, GPR14_OFFSET(r1)
+	lwz	r13, GPR13_OFFSET(r1)
+	lwz	r12, GPR12_OFFSET(r1)
+	lwz	r11, GPR11_OFFSET(r1)
+	lwz	r10, GPR10_OFFSET(r1)
+	lwz	r9, GPR9_OFFSET(r1)
+	lwz	r8, GPR8_OFFSET(r1)
+	lwz	r7, GPR7_OFFSET(r1)
+	lwz	r6, GPR6_OFFSET(r1)
+	lwz	r5, GPR5_OFFSET(r1)
+
+	/*
+	 * Disable nested exception processing, data and instruction
+	 * translation.
+	 */
+	mfmsr	r3
+	xori	r3, r3, MSR_RI /* | MSR_IR | MSR_DR */
+	mtmsr   r3
+	SYNC
+	/*
+	 * Restore rfi related settings
+	 */
+		 
+	lwz	r4, SRR1_FRAME_OFFSET(r1)
+	lwz	r3, SRR0_FRAME_OFFSET(r1)
+	lwz	r2, GPR2_OFFSET(r1)
+	lwz	r0, GPR0_OFFSET(r1)
+
+	mtsrr1	r4
+	mtsrr0	r3
+	lwz	r4, GPR4_OFFSET(r1)
+	lwz	r3, GPR3_OFFSET(r1)
+	addi 	r1,r1, EXCEPTION_FRAME_END
+	SYNC
+	rfi
+
--- a/c/src/lib/libbsp/powerpc/psim/irq/irq_init.c
+++ b/c/src/lib/libbsp/powerpc/psim/irq/irq_init.c
@@ -0,0 +1,168 @@
+/* irq_init.c
+ *
+ *  This file contains the implementation of rtems initialization
+ *  related to interrupt handling.
+ *
+ *  CopyRight (C) 1999 valette@crf.canon.fr
+ *
+ * Enhanced by Jay Kulpinski <jskulpin@eng01.gdds.com>
+ * to make it valid for MVME2300 Motorola boards.
+ *
+ * Till Straumann <strauman@slac.stanford.edu>, 12/20/2001:
+ * Use the new interface to openpic_init
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.com/license/LICENSE.
+ *
+ *  irq_init.c,v 1.6.2.5 2003/09/04 18:45:20 joel Exp
+ */
+
+#include <libcpu/io.h>
+#include <libcpu/spr.h>
+#include <bsp/irq.h>
+#include <bsp.h>
+#include <libcpu/raw_exception.h>
+#include <rtems/bspIo.h>
+#if 0
+#include <bsp/pci.h>
+#include <bsp/residual.h>
+#include <bsp/openpic.h>
+#include <bsp/motorola.h>
+#endif
+
+
+/*
+#define SHOW_ISA_PCI_BRIDGE_SETTINGS
+*/
+
+typedef struct {
+  unsigned char bus;	/* few chance the PCI/ISA bridge is not on first bus but ... */
+  unsigned char device;
+  unsigned char function;
+} pci_isa_bridge_device;
+
+pci_isa_bridge_device* via_82c586 = 0;
+
+extern unsigned int external_exception_vector_prolog_code_size[];
+extern void external_exception_vector_prolog_code();
+extern unsigned int decrementer_exception_vector_prolog_code_size[];
+extern void decrementer_exception_vector_prolog_code();
+
+/*
+ * default on/off function
+ */
+static void nop_func(){}
+/*
+ * default isOn function
+ */
+static int not_connected() {return 0;}
+/*
+ * default possible isOn function
+ */
+static int connected() {return 1;}
+
+static rtems_irq_connect_data     	rtemsIrq[BSP_IRQ_NUMBER];
+static rtems_irq_global_settings     	initial_config;
+static rtems_irq_connect_data     	defaultIrq = {
+  /* vectorIdex,	 hdl		, on		, off		, isOn */
+  0, 			 nop_func	, nop_func	, nop_func	, not_connected
+};
+static rtems_irq_prio irqPrioTable[BSP_IRQ_NUMBER]={
+  /*
+   * actual rpiorities for interrupt :
+   *	0   means that only current interrupt is masked
+   *	255 means all other interrupts are masked
+   */
+  /*
+   * ISA interrupts.
+   * The second entry has a priority of 255 because
+   * it is the slave pic entry and is should always remain
+   * unmasked.
+   */
+  0,0,
+  255,
+  0, 0, 0, 0,  0,  0,  0,  0,  0,  0,  0,  0,  0,
+  /*
+   * PCI Interrupts
+   */
+  8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, /* for raven prio 0 means unactive... */
+  /*
+   * Processor exceptions handled as interrupts
+   */
+  0
+};
+
+void VIA_isa_bridge_interrupts_setup(void)
+{
+  printk("VIA_isa_bridge_interrupts_setup - Shouldn't get here!\n");
+  return;
+}
+
+  /*
+   * This code assumes the exceptions management setup has already
+   * been done. We just need to replace the exceptions that will
+   * be handled like interrupt. On mcp750/mpc750 and many PPC processors
+   * this means the decrementer exception and the external exception.
+   */
+void BSP_rtems_irq_mng_init(unsigned cpuId)
+{
+  rtems_raw_except_connect_data vectorDesc;
+  int i;
+  
+  /*
+   * First initialize the Interrupt management hardware
+   */
+
+  /*
+   * Initialize Rtems management interrupt table
+   */
+    /*
+     * re-init the rtemsIrq table
+     */
+    for (i = 0; i < BSP_IRQ_NUMBER; i++) {
+      rtemsIrq[i]      = defaultIrq;
+      rtemsIrq[i].name = i;
+    }
+    /*
+     * Init initial Interrupt management config
+     */
+    initial_config.irqNb 	= BSP_IRQ_NUMBER;
+    initial_config.defaultEntry = defaultIrq;
+    initial_config.irqHdlTbl	= rtemsIrq;
+    initial_config.irqBase	= BSP_ASM_IRQ_VECTOR_BASE;
+    initial_config.irqPrioTbl	= irqPrioTable;
+
+    if (!BSP_rtems_irq_mngt_set(&initial_config)) {
+      /*
+       * put something here that will show the failure...
+       */
+      BSP_panic("Unable to initialize RTEMS interrupt Management!!! System locked\n");
+    }
+  
+  /*
+   * We must connect the raw irq handler for the two
+   * expected interrupt sources : decrementer and external interrupts.
+   */
+    vectorDesc.exceptIndex 	=	ASM_DEC_VECTOR;
+    vectorDesc.hdl.vector	=	ASM_DEC_VECTOR;
+    vectorDesc.hdl.raw_hdl	=	decrementer_exception_vector_prolog_code;
+    vectorDesc.hdl.raw_hdl_size	=	(unsigned) decrementer_exception_vector_prolog_code_size;
+    vectorDesc.on		=	nop_func;
+    vectorDesc.off		=	nop_func;
+    vectorDesc.isOn		=	connected;
+    if (!mpc60x_set_exception (&vectorDesc)) {
+      BSP_panic("Unable to initialize RTEMS decrementer raw exception\n");
+    }
+    vectorDesc.exceptIndex	=	ASM_EXT_VECTOR;
+    vectorDesc.hdl.vector	=	ASM_EXT_VECTOR;
+    vectorDesc.hdl.raw_hdl	=	external_exception_vector_prolog_code;
+    vectorDesc.hdl.raw_hdl_size	=	(unsigned) external_exception_vector_prolog_code_size;
+    if (!mpc60x_set_exception (&vectorDesc)) {
+      BSP_panic("Unable to initialize RTEMS external raw exception\n");
+    }
+#ifdef TRACE_IRQ_INIT  
+    printk("RTEMS IRQ management is now operationnal\n");
+#endif
+}
+
--- a/c/src/lib/libbsp/powerpc/psim/start/Makefile.am
+++ b/c/src/lib/libbsp/powerpc/psim/start/Makefile.am
@@ -2,7 +2,9 @@
 ## $Id$
 ##

-S_FILES = start.S
+VPATH = @srcdir@:@srcdir@/../../shared/start
+
+S_FILES = start.S rtems_crti.S
 S_O_FILES = $(S_FILES:%.S=$(ARCH)/%.$(OBJEXT))

 OBJS = $(S_O_FILES)
@@ -13,20 +15,22 @@ include $(top_srcdir)/../../../../../../automake/lib.am
 #
 # (OPTIONAL) Add local stuff here using +=
 #
-
-install-data-local: $(PROJECT_RELEASE)/lib/start$(LIB_VARIANT).$(OBJEXT)
-	@$(mkinstalldirs) $(DESTDIR)$(bsplibdir)
-	$(INSTALL_DATA) $< $(DESTDIR)$(bsplibdir)
+bsplib_DATA =  $(PROJECT_RELEASE)/lib/start$(LIB_VARIANT).$(OBJEXT)
+bsplib_DATA += $(PROJECT_RELEASE)/lib/rtems_crti.$(OBJEXT)

 $(PROJECT_RELEASE)/lib/start$(LIB_VARIANT).$(OBJEXT): $(ARCH)/start.$(OBJEXT)
 	$(INSTALL_DATA) $< $@

+$(PROJECT_RELEASE)/lib/rtems_crti.$(OBJEXT): $(ARCH)/rtems_crti.$(OBJEXT)
+	$(INSTALL_DATA) $< $@
+
 TMPINSTALL_FILES += $(PROJECT_RELEASE)/lib/start$(LIB_VARIANT).$(OBJEXT)
+TMPINSTALL_FILES += $(PROJECT_RELEASE)/lib/rtems_crti.$(OBJEXT)

-all-local: $(ARCH) $(OBJS) $(ARCH)/start.$(OBJEXT) $(TMPINSTALL_FILES)
+all-local: $(ARCH) $(OBJS) $(ARCH)/start.$(OBJEXT) $(ARCH)/rtems_crti.$(OBJEXT) $(TMPINSTALL_FILES)

-.PRECIOUS: $(ARCH)/start.$(OBJEXT)
+$(OBJS): $(ARCH)

-EXTRA_DIST = start.S
+.PRECIOUS: $(ARCH)/start.$(OBJEXT) $(ARCH)/rtems_crti.$(OBJEXT)

 include $(top_srcdir)/../../../../../../automake/local.am
--- a/c/src/lib/libbsp/powerpc/psim/start/start.S
+++ b/c/src/lib/libbsp/powerpc/psim/start/start.S
@@ -17,6 +17,9 @@
 *  $Id$
 */

+#include <asm.h>
+#include <rtems/score/cpu.h>
+#include <libcpu/io.h>
 #include "ppc-asm.h"

 	.file	"startsim.s"
@@ -53,9 +56,14 @@ FUNC_NAME(__atexit):			/* tell C's eabi-ctor's we have an atexit function */
 .Lptr:
 	.long .LCTOC1-.Laddr

+	.globl	__rtems_entry_point
+	.type	__rtems_entry_point,@function
+__rtems_entry_point:
+#if 1
 	.globl	_start
 	.type	_start,@function
 _start:
+#endif
 	bl	.Laddr			/* get current address */
 .Laddr:
 	mflr	r4			/* real address of .Laddr */
@@ -64,6 +72,7 @@ _start:
 	lwz	r4,.Ltable(r5)		/* get linker's idea of where .Laddr is */
 	subf	r4,r4,r5		/* calculate difference between where linked and current */

+	bl      __eabi	/* setup EABI and SYSV environment */
 	/* clear bss */
 	lwz	r6,.Lbss_start(r5)	/* calculate beginning of the BSS */
 	lwz	r7,.Lend(r5)		/* calculate end of the BSS */
@@ -100,6 +109,7 @@ _start:
        la	r5,environ@l(r5)	/* environp */
 	li	r4, 0			/* argv */
 	li	r3, 0			/* argc */
+
 	/* Let her rip */
 	bl	FUNC_NAME(boot_card)

--- a/c/src/lib/libbsp/powerpc/psim/startup/Makefile.am
+++ b/c/src/lib/libbsp/powerpc/psim/startup/Makefile.am
@@ -8,7 +8,7 @@ VPATH = @srcdir@:@srcdir@/../../../shared
 PGM = $(ARCH)/startup.rel

 C_FILES = bspclean.c bsplibc.c bsppost.c bspstart.c bootcard.c main.c sbrk.c \
-    setvec.c gnatinstallhandler.c
+    gnatinstallhandler.c
 C_O_FILES = $(C_FILES:%.c=$(ARCH)/%.$(OBJEXT))

 OBJS = $(C_O_FILES)
@@ -38,6 +38,6 @@ all-local: $(ARCH) $(OBJS) $(PGM) $(TMPINSTALL_FILES)

 .PRECIOUS: $(PGM)

-EXTRA_DIST = bspclean.c bspstart.c device-tree linkcmds setvec.c
+EXTRA_DIST = bspclean.c bspstart.c device-tree linkcmds 

 include $(top_srcdir)/../../../../../../automake/local.am
--- a/c/src/lib/libbsp/powerpc/psim/startup/bspstart.c
+++ b/c/src/lib/libbsp/powerpc/psim/startup/bspstart.c
@@ -16,37 +16,85 @@

 #include <string.h>
 #include <fcntl.h>
-
 #include <bsp.h>
+#include <bsp/irq.h>
 #include <rtems/libio.h>
 #include <rtems/libcsupport.h>
 #include <rtems/bspIo.h>
+#include <libcpu/cpuIdent.h>
+#include <libcpu/spr.h>
+
+SPR_RW(SPRG0)
+SPR_RW(SPRG1)
+
+
+extern unsigned long __rtems_end[];
+
+void  initialize_exceptions(void);
+
+/*  On psim, each click of the decrementer register corresponds
+ *  to 1 instruction.  By setting this to 100, we are indicating
+ *  that we are assuming it can execute 100 instructions per
+ *  microsecond.  This corresponds to sustaining 1 instruction
+ *  per cycle at 100 Mhz.  Whether this is a good guess or not
+ *  is anyone's guess.
+ */
+
+extern int PSIM_INSTRUCTIONS_PER_MICROSECOND;

 /*
 *  The original table from the application and our copy of it with
 *  some changes.
 */
- 
+
 extern rtems_configuration_table  Configuration;
 rtems_configuration_table         BSP_Configuration;
-
 rtems_cpu_table   Cpu_table;
-rtems_unsigned32  bsp_isr_level;

 /*
 *  Tells us where to put the workspace in case remote debugger is present.
 */

 #if 0
-extern rtems_unsigned32  rdb_start;
+extern uint32_t          rdb_start;
 #endif

+/*
+ * PCI Bus Frequency
+ */
+ unsigned int BSP_bus_frequency;
+ /*
+  *  * Time base divisior (how many tick for 1 second).
+  *   */
+ unsigned int BSP_time_base_divisor;
+
+
+
 /*
 *  Use the shared implementations of the following routines
 */
- 
+
 void bsp_postdriver_hook(void);
-void bsp_libc_init( void *, unsigned32, int );
+void bsp_libc_init( void *, uint32_t, int );
+
+/*
+ * system init stack and soft ir stack size
+ */
+#define INIT_STACK_SIZE 0x1000
+#define INTR_STACK_SIZE CONFIGURE_INTERRUPT_STACK_MEMORY
+
+
+void BSP_panic(char *s)
+{
+    printk("%s PANIC %s\n",_RTEMS_version, s);
+      __asm__ __volatile ("sc");
+}
+
+void _BSP_Fatal_error(unsigned int v)
+{
+    printk("%s PANIC ERROR %x\n",_RTEMS_version, v);
+      __asm__ __volatile ("sc");
+}

 /*
 *  bsp_pretasking_hook
@@ -58,10 +106,10 @@ void bsp_libc_init( void *, unsigned32, int );
 void bsp_pretasking_hook(void)
 {
  extern int end;
-  rtems_unsigned32 heap_start;
-  rtems_unsigned32 heap_size;
+  uint32_t         heap_start;
+  uint32_t         heap_size;

-  heap_start = (rtems_unsigned32) &end;
+  heap_start = (uint32_t) &end;
  if (heap_start & (CPU_ALIGNMENT-1))
    heap_start = (heap_start + CPU_ALIGNMENT) & ~(CPU_ALIGNMENT-1);

@@ -84,16 +132,14 @@ void bsp_pretasking_hook(void)

 void bsp_start( void )
 {
-  unsigned char *work_space_start;
+  unsigned char     *work_space_start;
+  register uint32_t  intrStack;
+  register uint32_t *intrStackPtr;

-#if 0
-  /* 
-   * Set MSR to show vectors at 0 XXX
+  /*
+   * Note we can not get CPU identification dynamically, so force current_ppc_cpu.
   */
-  _CPU_MSR_Value( msr_value );
-  msr_value &= ~PPC_MSR_EP;
-  _CPU_MSR_SET( msr_value );
-#endif
+  current_ppc_cpu = PPC_PSIM;

  /*
   * Set up our hooks
@@ -118,15 +164,18 @@ void bsp_start( void )

  Cpu_table.interrupt_stack_size = CONFIGURE_INTERRUPT_STACK_MEMORY;

+  BSP_bus_frequency        = (unsigned int)&PSIM_INSTRUCTIONS_PER_MICROSECOND;
+  BSP_time_base_divisor    = 1;
+
  /*
-   *  The monitor likes the exception table to be at 0x0.
+   *  The simulator likes the exception table to be at 0xfff00000.
   */

-  Cpu_table.exceptions_in_RAM = TRUE;
+  Cpu_table.exceptions_in_RAM = FALSE;

  BSP_Configuration.work_space_size += 1024;

-  work_space_start = 
+  work_space_start =
    (unsigned char *)&RAM_END - BSP_Configuration.work_space_size;

  if ( work_space_start <= (unsigned char *)&end ) {
@@ -136,4 +185,36 @@ void bsp_start( void )

  BSP_Configuration.work_space_start = work_space_start;

+  /*
+   * Initialize the interrupt related settings
+   * SPRG1 = software managed IRQ stack
+   *
+   * This could be done latter (e.g in IRQ_INIT) but it helps to understand
+   * some settings below...
+   */
+  intrStack = ((uint32_t) __rtems_end) + 
+          INIT_STACK_SIZE + INTR_STACK_SIZE - CPU_MINIMUM_STACK_FRAME_SIZE;
+
+  /* make sure it's properly aligned */
+  intrStack &= ~(CPU_STACK_ALIGNMENT-1);
+
+  /* tag the bottom (T. Straumann 6/36/2001 <strauman@slac.stanford.edu>) */
+  intrStackPtr = (uint32_t*) intrStack;
+  *intrStackPtr = 0;
+
+  _write_SPRG1(intrStack);
+
+  /* signal them that we have fixed PR288 - eventually, this should go away */
+  _write_SPRG0(PPC_BSP_HAS_FIXED_PR288);
+
+  /*
+   * Initialize default raw exception hanlders. See vectors/vectors_init.c
+   */
+  initialize_exceptions();
+
+  /*
+   * Initalize RTEMS IRQ system
+   */
+  BSP_rtems_irq_mng_init(0);
+
 }
--- a/c/src/lib/libbsp/powerpc/psim/startup/linkcmds
+++ b/c/src/lib/libbsp/powerpc/psim/startup/linkcmds
@@ -16,7 +16,7 @@ OUTPUT_ARCH(powerpc)
 ENTRY(_start)
 /* Do we need any of these for elf?
   __DYNAMIC = 0;    */
-PROVIDE (PSIM_INSTRUCTIONS_PER_MICROSECOND = 100);
+PROVIDE (PSIM_INSTRUCTIONS_PER_MICROSECOND = 10000);   /* 100); */
 PROVIDE (CPU_PPC_CLICKS_PER_MS = 16667);
 MEMORY
  {
@@ -26,10 +26,10 @@ MEMORY

 SECTIONS
 {
-  .vectors 0xFFF00100 :
+  .entry_point_section :
  {
-    *(.vectors)
-  } >EPROM
+	*(.entry_point_section)
+  } > EPROM

  /* Read-only sections, merged into text segment: */
  /* . = 0x40000 + SIZEOF_HEADERS; */
@@ -74,8 +74,15 @@ SECTIONS
    /* .gnu.warning sections are handled specially by elf32.em.  */
    *(.gnu.warning)
  } >RAM
-  .init		  : { _init = .; __init = .; *(.init)		} >RAM
-  .fini		  : { _fini = .; __fini = .; *(.fini)		} >RAM
+  .init           :
+  {
+    KEEP (*(.init))
+  } >RAM =0
+  .fini           :
+  {
+    _fini = .;
+    KEEP (*(.fini))
+  } >RAM =0
  .rodata  	  : { *(.rodata*) *(.gnu.linkonce.r*) } >RAM
  .rodata1	  : { *(.rodata1) 	} >RAM
  .eh_frame	  : { *.(eh_frame)		} >RAM
@@ -143,6 +150,8 @@ SECTIONS
  PROVIDE (_GOT_END_ = .);
  PROVIDE (__GOT_END__ = .);

+  .jcr            : { KEEP (*(.jcr)) } > RAM
+
  /* We want the small data sections together, so single-instruction offsets
     can access them all, and initialized data all before uninitialized, so
     we can shorten the on-disk segment size.  */
@@ -170,6 +179,7 @@ SECTIONS
   *(COMMON)
  } >RAM
  . =  ALIGN(8) + 0x8000;
+  __rtems_end = . ;
  PROVIDE(__stack = .);
  PROVIDE(_end = .);
  PROVIDE(end = .);
--- a/c/src/lib/libbsp/powerpc/psim/vectors/Makefile.am
+++ b/c/src/lib/libbsp/powerpc/psim/vectors/Makefile.am
@@ -3,12 +3,17 @@
 ##


-PGM = $(ARCH)/vectors.rel
+VPATH = @srcdir@:@srcdir@/../console:@srcdir@/../../shared/vectors

-S_FILES = align_h.S vectors.S
+C_FILES = vectors_init.c
+C_O_FILES = $(C_FILES:%.c=$(ARCH)/%.$(OBJEXT))
+
+H_FILES = ../../shared/vectors/vectors.h
+
+S_FILES = vectors.S
 S_O_FILES = $(S_FILES:%.S=$(ARCH)/%.$(OBJEXT))

-OBJS = $(S_O_FILES)
+OBJS = $(S_O_FILES) $(C_O_FILES)

 include $(top_srcdir)/../../../../../../automake/compile.am
 include $(top_srcdir)/../../../../../../automake/lib.am
@@ -20,12 +25,20 @@ include $(top_srcdir)/../../../../../../automake/lib.am
 $(PGM): $(OBJS)
 	$(make-rel)

-# the .rel file built here will be put into libbsp.a by ../wrapup/Makefile
+include_bspdir = $(includedir)/bsp
+include_bsp_HEADERS = ../../shared/vectors/vectors.h

-all-local: $(ARCH) $(OBJS) $(PGM)
+$(PROJECT_INCLUDE)/bsp:
+	$(mkinstalldirs) $@

-.PRECIOUS: $(PGM)
+$(PROJECT_INCLUDE)/bsp/vectors.h: ../../shared/vectors/vectors.h
+	$(INSTALL_DATA) $< $@

-EXTRA_DIST = README align_h.S vectors.S
+TMPINSTALL_FILES += $(PROJECT_INCLUDE)
+TMPINSTALL_FILES += $(PROJECT_INCLUDE)/bsp
+TMPINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/vectors.h

+all-local: $(ARCH) $(TMPINSTALL_FILES) $(OBJS)
+
+include $(top_srcdir)/../../../../../../automake/force-preinstall.am
 include $(top_srcdir)/../../../../../../automake/local.am
--- a/c/src/lib/libbsp/powerpc/psim/vectors/vectors.S
+++ b/c/src/lib/libbsp/powerpc/psim/vectors/vectors.S
@@ -1,123 +1,160 @@
-/*  vectors.s	1.1 - 95/12/04
+/*
+ * (c) 1999, Eric Valette valette@crf.canon.fr
+ *
 *
 *  This file contains the assembly code for the PowerPC 
- *  interrupt vectors for RTEMS.
+ *  exception veneers for RTEMS.
 *
- *  COPYRIGHT (c) 1989-1999.
- *  On-Line Applications Research Corporation (OAR).
- *
- *  The license and distribution terms for this file may be
- *  found in found in the file LICENSE in this distribution or at
- *  http://www.rtems.com/license/LICENSE.
- *
- *  $Id$
+ * vectors.S,v 1.3.4.1 2003/02/20 21:48:25 joel Exp
 */
+	

+
+#include <asm.h>
+#include <rtems/score/cpu.h>
+#include <bsp/vectors.h>
+	
+
+#define SYNC \
+	sync; \
+	isync
+	
+	PUBLIC_VAR (__rtems_start)
+	.section .entry_point_section,"awx",@progbits
 /*
- *  The issue with this file is getting it loaded at the right place.
- *  The first vector MUST be at address 0x????0100.
- *  How this is achieved is dependant on the tool chain.
- *
- *  However the basic mechanism for ELF assemblers is to create a
- *  section called ".vectors", which will be loaded to an address
- *  between 0x????0000 and 0x????0100 (inclusive) via a link script.
- *
- *  The basic mechanism for XCOFF assemblers is to place it in the
- *  normal text section, and arrange for this file to be located
- *  at an appropriate position on the linker command line.
- *
- *  The variable 'PPC_VECTOR_FILE_BASE' must be defined to be the
- *  offset from 0x????0000 to the first location in the file.  This
- *  will usually be 0x0000 or 0x0100.
+ * Entry point information used by bootloader code
 */
+SYM (__rtems_start):		
+	.long   __rtems_entry_point

-#include <bsp.h>
-#include "asm.h"
-
-#ifndef PPC_VECTOR_FILE_BASE
-#error "PPC_VECTOR_FILE_BASE is not defined."
-#endif
-
-	/* Where this file will be loaded */
-	.set	file_base, PPC_VECTOR_FILE_BASE
-
-	/* Offset to store reg 0 */
-
-	.set	IP_LINK, 0
-#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27)
-	.set	IP_0, (IP_LINK + 56)
-#else
-	.set	IP_0, (IP_LINK + 8)
-#endif
-	.set	IP_2, (IP_0 + 4)
-
-	.set	IP_3, (IP_2 + 4)
-	.set	IP_4, (IP_3 + 4)
-	.set	IP_5, (IP_4 + 4)
-	.set	IP_6, (IP_5 + 4)
+	/*
+	 * end of special Entry point section
+	 */	
+	.text
+	.p2align 5	
+		
+PUBLIC_VAR(default_exception_vector_code_prolog)
+SYM (default_exception_vector_code_prolog):
+	/*
+	 * let room for exception frame
+	 */
+	stwu    r1, - (EXCEPTION_FRAME_END)(r1)
+	stw	r3, GPR3_OFFSET(r1)
+	/* R2 should never change (EABI: pointer to .sdata2) - we
+     * save it nevertheless..
+	 */
+	stw	r2, GPR2_OFFSET(r1)
+	mflr	r3
+	stw	r3, EXC_LR_OFFSET(r1)
+	bl	0f
+0:	/*
+	 * r3 = exception vector entry point 
+	 * (256 * vector number) + few instructions
+	 */
+	mflr	r3
+	/*
+	 * r3 = r3 >> 8 = vector
+	 */
+	srwi	r3,r3,8
+	ba	push_normalized_frame
 	
-	.set	IP_7, (IP_6 + 4)
-	.set	IP_8, (IP_7 + 4)
-	.set	IP_9, (IP_8 + 4)
-	.set	IP_10, (IP_9 + 4)
+	PUBLIC_VAR (default_exception_vector_code_prolog_size)
 	
-	.set	IP_11, (IP_10 + 4)
-	.set	IP_12, (IP_11 + 4)
-	.set	IP_13, (IP_12 + 4)
-	.set	IP_28, (IP_13 + 4)
+	default_exception_vector_code_prolog_size= . - default_exception_vector_code_prolog
 	
-	.set	IP_29, (IP_28 + 4)
-	.set	IP_30, (IP_29 + 4)
-	.set	IP_31, (IP_30 + 4)
-	.set	IP_CR, (IP_31 + 4)
-	
-	.set	IP_CTR, (IP_CR + 4)
-	.set	IP_XER, (IP_CTR + 4)
-	.set	IP_LR, (IP_XER + 4)
-	.set	IP_PC, (IP_LR + 4)
-	
-	.set	IP_MSR, (IP_PC + 4)
-	
-	.set	IP_END, (IP_MSR + 16)
+	.p2align 5
+PUBLIC_VAR (push_normalized_frame)	
+SYM (push_normalized_frame):
+	stw	r3, EXCEPTION_NUMBER_OFFSET(r1)
+	stw	r0, GPR0_OFFSET(r1)
+	mfsrr0  r3
+	stw	r3, SRR0_FRAME_OFFSET(r1)
+	mfsrr1  r3
+	stw	r3, SRR1_FRAME_OFFSET(r1)
+	/*
+	 * Save general purpose registers
+	 * Already saved in prolog : R1, R2, R3, LR.
+	 * Saved a few line above  : R0
+	 *
+	 * Manual says that "stmw" instruction may be slower than
+	 * series of individual "stw" but who cares about performance 
+	 * for the DEFAULT exception handler?
+	 */
+	stmw	r4, GPR4_OFFSET(r1)	/* save R4->R31 */

-	/* Vector offsets			 */
-	.set    begin_vector,0xFFF00000
-	.set    crit_vector,0xFFF00100
-	.set    mach_vector,0xFFF00200
-	.set    prot_vector,0xFFF00300
-	.set    ext_vector,0xFFF00500
-	.set    align_vector,0xFFF00600
-	.set    prog_vector,0xFFF00700
-	.set    dec_vector,0xFFF00900
-	.set    sys_vector,0xFFF00C00
-	.set    pit_vector,0xFFF01000
-	.set    fit_vector,0xFFF01010
-	.set    wadt_vector,0xFFF01020
-	.set    debug_vector,0xFFF02000
-
-/* Go to the right section */
-#if PPC_ASM == PPC_ASM_ELF
-	.section .vectors,"awx",@progbits
-#elif PPC_ASM == PPC_ASM_XCOFF
-	.csect	.text[PR]
-#endif
-
-	PUBLIC_VAR (__vectors)
-SYM (__vectors):
+	mfcr	r31
+	stw	r31,  EXC_CR_OFFSET(r1)
+	mfctr	r30
+	stw	r30,  EXC_CTR_OFFSET(r1)
+	mfxer	r28
+	stw	r28,  EXC_XER_OFFSET(r1)
+	mfmsr	r28
+	stw	r28,  EXC_MSR_OFFSET(r1)
+	mfdar	r28
+	stw	r28,  EXC_DAR_OFFSET(r1)
+	/*
+	 * compute SP at exception entry
+	 */
+	addi    r3, r1, EXCEPTION_FRAME_END
+	/*
+	 * store it at the right place
+	 */
+	stw     r3, GPR1_OFFSET(r1)
+	/*
+	 * Enable data and instruction address translation, exception nesting
+	 */
+	mfmsr	r3
+	ori     r3,r3, MSR_RI /* | MSR_IR | MSR_DR */
+	mtmsr   r3
+	SYNC
 	
-/* Decrementer interrupt */
-	.org	dec_vector - file_base
-#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27)
-#if (PPC_HAS_FPU)
-	stwu	r1, -(20*4 + 18*8 + IP_END)(r1)
-#else
-	stwu	r1, -(20*4 + IP_END)(r1)
-#endif
-#else
-	stwu	r1, -(IP_END)(r1)
-#endif
-	stw	r0, IP_0(r1)
+	/*
+	 * Call C exception handler
+	 */
+	/*
+	 * store the execption frame address in r3 (first param)
+	 */
+	addi	r3, r1, 0x8
+	/*
+	 * globalExceptHdl(r3)
+	 */
+	addis	r4, 0, globalExceptHdl@ha
+	lwz	r5, globalExceptHdl@l(r4)
+	mtlr	r5
+	blrl
+	/*
+	 * Restore registers status
+	 */
+	lwz	r31,  EXC_CR_OFFSET(r1)
+	mtcr	r31
+	lwz	r30,  EXC_CTR_OFFSET(r1)
+	mtctr	r30
+	lwz	r29,  EXC_LR_OFFSET(r1)
+	mtlr	r29
+	lwz	r28,  EXC_XER_OFFSET(r1)
+	mtxer	r28

-	li      r0, PPC_IRQ_DECREMENTER
-	b       PROC (_ISR_Handler)
+	lmw	r4, GPR4_OFFSET(r1)
+	lwz	r2, GPR2_OFFSET(r1)
+	lwz	r0, GPR0_OFFSET(r1)

+	/*
+	 * Disable data and instruction translation. Make path non recoverable...
+	 */
+	mfmsr	r3
+	xori	r3, r3, MSR_RI | MSR_IR | MSR_DR
+	mtmsr   r3
+	SYNC
+	/*
+	 * Restore rfi related settings
+	 */
+		 
+	lwz	r3, SRR1_FRAME_OFFSET(r1)
+	mtsrr1	r3
+	lwz	r3, SRR0_FRAME_OFFSET(r1)
+	mtsrr0	r3
+	
+	lwz	r3, GPR3_OFFSET(r1)
+	addi 	r1,r1, EXCEPTION_FRAME_END
+	SYNC
+	rfi
--- a/c/src/lib/libbsp/powerpc/psim/wrapup/Makefile.am
+++ b/c/src/lib/libbsp/powerpc/psim/wrapup/Makefile.am
@@ -2,25 +2,28 @@
 ## $Id$
 ##

-include $(top_srcdir)/../../../../../../automake/compile.am
-include $(top_srcdir)/../../../../../../automake/lib.am
+if HAS_MP
+BSP_MP_O_FILES = shmsupp
+endif
+BSP_PIECES = startup clock console irq vectors $(BSP_MP_O_FILES)

 if HAS_MP
-GENERIC_MP_REL_PIECES = shmdr
+GENERIC_MP_REL_FILES = shmdr
 endif
-GENERIC_PIECES = $(GENERIC_MP_REL_PIECES)
-
-if HAS_MP
-BSP_MP_O_PIECES = shmsupp
-endif
-BSP_PIECES = startup clock console timer vectors $(BSP_MP_O_PIECES)
+GENERIC_FILES = $(GENERIC_MP_REL_FILES)

 # bummer; have to use $foreach since % pattern subst rules only replace 1x
-OBJS = $(foreach piece, $(BSP_PIECES), $(wildcard ../$(piece)/$(ARCH)/*.$(OBJEXT))) \
+OBJS = $(foreach piece, $(BSP_PIECES), ../$(piece)/$(ARCH)/*.$(OBJEXT)) \
+    $(foreach piece, $(GENERIC_FILES), ../../../$(piece)/$(ARCH)/$(piece).rel) \
+    $(wildcard ../../../../libcpu/$(RTEMS_CPU)/shared/*/$(ARCH)/*.$(OBJEXT)) \
+    $(wildcard ../../../../libcpu/$(RTEMS_CPU)/mpc6xx/*/$(ARCH)/*.$(OBJEXT)) \
    ../@exceptions@/$(ARCH)/rtems-cpu.rel \
-    $(foreach piece, $(GENERIC_PIECES), ../../../$(piece)/$(ARCH)/$(piece).rel)
+    $(wildcard ../../../../libcpu/$(RTEMS_CPU)/$(RTEMS_CPU_MODEL)/*/$(ARCH)/*.$(OBJEXT))
 LIB = $(ARCH)/libbsp.a

+include $(top_srcdir)/../../../../../../automake/compile.am
+include $(top_srcdir)/../../../../../../automake/lib.am
+
 #
 # (OPTIONAL) Add local stuff here using +=
 #
--- a/c/src/lib/libbsp/powerpc/score603e/ChangeLog
+++ b/c/src/lib/libbsp/powerpc/score603e/ChangeLog
@@ -1,3 +1,10 @@
+2005-04-11	Jennifer Averett<jennifer.averett@oarcorp.com>
+
+	PR 778/bsps
+	* include/bsp.h, include/gen2.h, startup/FPGA.c, startup/Hwr_init.c,
+	startup/bspstart.c, tod/tod.c:
+        modify SCORE_.. to BSP_.. for externally used define's.
+
 2003-09-04	Joel Sherrill <joel@OARcorp.com>

 	* PCI_bus/PCI.h, clock/clock.c, console/85c30.c, console/85c30.h,
--- a/c/src/lib/libbsp/powerpc/score603e/include/bsp.h
+++ b/c/src/lib/libbsp/powerpc/score603e/include/bsp.h
@@ -69,7 +69,10 @@ extern "C" {

 #define Initialize_Board_ctrl_register()                         \
  *SCORE603E_BOARD_CTRL_REG = (*SCORE603E_BOARD_CTRL_REG |       \
-                               SCORE603E_BRD_FLASH_DISABLE_MASK) \
+                               SCORE603E_BRD_FLASH_DISABLE_MASK)
+ 
+#define Processor_Synchronize() \
+  asm(" eieio ")

 /*
 *  Define the time limits for RTEMS Test Suite test durations.
@@ -249,6 +252,9 @@ unsigned int SCORE603e_FLASH_Enable_writes(
  rtems_unsigned32               area        /* Unused  */
 );

+#define BSP_FLASH_ENABLE_WRITES( _area) SCORE603e_FLASH_Enable_writes( _area )
+#define BSP_FLASH_DISABLE_WRITES(_area) SCORE603e_FLASH_Disable( _area )
+
 #define Convert_Endian_32( _data ) \
  ( ((_data&0x000000ff)<<24) | ((_data&0x0000ff00)<<8) |  \
    ((_data&0x00ff0000)>>8)  | ((_data&0xff000000)>>24) )
--- a/c/src/lib/libbsp/powerpc/score603e/include/gen2.h
+++ b/c/src/lib/libbsp/powerpc/score603e/include/gen2.h
@@ -25,7 +25,7 @@ extern "C" {
 * ISA/PCI I/O space.
 */
 #define SCORE603E_VME_JUMPER_ADDR      0x00e20000       
-#define SCORE603E_FLASH_BASE_ADDR      0x04000000
+#define BSP_FLASH_BASE                 0x04000000
 #define SCORE603E_ISA_PCI_IO_BASE      0x80000000
 #define SCORE603E_TIMER_PORT_C         0xfd000000       
 #define SCORE603E_TIMER_INT_ACK        0xfd000000       
@@ -47,62 +47,61 @@ extern "C" {
 /*
 * PSC8 - PMC Card 
 */
-#define SCORE603E_PCI_CONFIGURATION_BASE   0x80800000
-#define SCORE603E_PMC_BASE                 SCORE603E_PCI_CONFIGURATION_BASE
-#define SCORE603E_PCI_PMC_DEVICE_BASE      0x80808000
+#define BSP_PCI_CONFIGURATION_BASE   0x80800000
+#define BSP_PMC_BASE                 BSP_PCI_CONFIGURATION_BASE
+#define BSP_PCI_PMC_DEVICE_BASE      0x80808000

-#define SCORE603E_PCI_REGISTER_BASE        0xfc000000
+#define BSP_PCI_REGISTER_BASE        0xfc000000

-#define SCORE603E_PCI_DEVICE_ADDRESS( _offset) \
-         ((volatile rtems_unsigned32 *)( SCORE603E_PCI_PMC_DEVICE_BASE + _offset ))
-  
+#define BSP_PCI_DEVICE_ADDRESS( _offset) \
+         ((volatile rtems_unsigned32 *)( BSP_PCI_PMC_DEVICE_BASE + _offset ))

-#define SCORE603E_PMC_SERIAL_ADDRESS( _offset )    \
-        ((volatile rtems_unsigned8 *)(SCORE603E_PCI_REGISTER_BASE + _offset))
+
+#define BSP_PMC_SERIAL_ADDRESS( _offset )    \
+        ((volatile rtems_unsigned8 *)(BSP_PCI_REGISTER_BASE + _offset))

 /*
 * PMC serial channels - (4-7: 232 and 8-11: 422)
 */
-#define SCORE603E_85C30_CTRL_4        SCORE603E_PMC_SERIAL_ADDRESS(0x200020) 
-#define SCORE603E_85C30_DATA_4        SCORE603E_PMC_SERIAL_ADDRESS(0x200024) 
-#define SCORE603E_85C30_CTRL_5        SCORE603E_PMC_SERIAL_ADDRESS(0x200028) 
-#define SCORE603E_85C30_DATA_5        SCORE603E_PMC_SERIAL_ADDRESS(0x20002c) 
-#define SCORE603E_85C30_CTRL_6        SCORE603E_PMC_SERIAL_ADDRESS(0x200030) 
-#define SCORE603E_85C30_DATA_6        SCORE603E_PMC_SERIAL_ADDRESS(0x200034) 
-#define SCORE603E_85C30_CTRL_7        SCORE603E_PMC_SERIAL_ADDRESS(0x200038) 
-#define SCORE603E_85C30_DATA_7        SCORE603E_PMC_SERIAL_ADDRESS(0x20003c) 
-#define SCORE603E_85C30_CTRL_8        SCORE603E_PMC_SERIAL_ADDRESS(0x200000) 
-#define SCORE603E_85C30_DATA_8        SCORE603E_PMC_SERIAL_ADDRESS(0x200004) 
-#define SCORE603E_85C30_CTRL_9        SCORE603E_PMC_SERIAL_ADDRESS(0x200008) 
-#define SCORE603E_85C30_DATA_9        SCORE603E_PMC_SERIAL_ADDRESS(0x20000c) 
-#define SCORE603E_85C30_CTRL_10       SCORE603E_PMC_SERIAL_ADDRESS(0x200010) 
-#define SCORE603E_85C30_DATA_10       SCORE603E_PMC_SERIAL_ADDRESS(0x200014) 
-#define SCORE603E_85C30_CTRL_11       SCORE603E_PMC_SERIAL_ADDRESS(0x200018) 
-#define SCORE603E_85C30_DATA_11       SCORE603E_PMC_SERIAL_ADDRESS(0x20001c) 
+#define SCORE603E_85C30_CTRL_4        BSP_PMC_SERIAL_ADDRESS(0x200020)
+#define SCORE603E_85C30_DATA_4        BSP_PMC_SERIAL_ADDRESS(0x200024)
+#define SCORE603E_85C30_CTRL_5        BSP_PMC_SERIAL_ADDRESS(0x200028)
+#define SCORE603E_85C30_DATA_5        BSP_PMC_SERIAL_ADDRESS(0x20002c)
+#define SCORE603E_85C30_CTRL_6        BSP_PMC_SERIAL_ADDRESS(0x200030)
+#define SCORE603E_85C30_DATA_6        BSP_PMC_SERIAL_ADDRESS(0x200034)
+#define SCORE603E_85C30_CTRL_7        BSP_PMC_SERIAL_ADDRESS(0x200038)
+#define SCORE603E_85C30_DATA_7        BSP_PMC_SERIAL_ADDRESS(0x20003c)
+#define SCORE603E_85C30_CTRL_8        BSP_PMC_SERIAL_ADDRESS(0x200000)
+#define SCORE603E_85C30_DATA_8        BSP_PMC_SERIAL_ADDRESS(0x200004)
+#define SCORE603E_85C30_CTRL_9        BSP_PMC_SERIAL_ADDRESS(0x200008)
+#define SCORE603E_85C30_DATA_9        BSP_PMC_SERIAL_ADDRESS(0x20000c)
+#define SCORE603E_85C30_CTRL_10       BSP_PMC_SERIAL_ADDRESS(0x200010)
+#define SCORE603E_85C30_DATA_10       BSP_PMC_SERIAL_ADDRESS(0x200014)
+#define SCORE603E_85C30_CTRL_11       BSP_PMC_SERIAL_ADDRESS(0x200018)
+#define SCORE603E_85C30_DATA_11       BSP_PMC_SERIAL_ADDRESS(0x20001c)

 #define SCORE603E_PCI_IO_CFG_ADDR      0x80000cf8
 #define SCORE603E_PCI_IO_CFG_DATA      0x80000cfc

 #define SCORE603E_UNIVERSE_BASE        0x80030000
 #define SCORE603E_IO_VME_UNIVERSE_BASE 0x80007000
-#define SCORE603E_PCI_MEM_BASE         0xc0000000       
-#define SCORE603E_NVRAM_BASE           0xfd100000
-#define SCORE603E_RTC_ADDRESS          ((volatile unsigned char *)0xfd180000)
+#define BSP_PCI_MEM_BASE         0xc0000000
+#define BSP_NVRAM_BASE           0xfd100000
+#define BSP_RTC_ADDRESS          ((volatile unsigned char *)0xfd180000)
 #define SCORE603E_JP1_JP2_PROM_BASE    0xfff00000
 #define SCORE603E_NOT_JP1_2_FLASH_BASE 0xff800000

-
 #if (SCORE603E_USE_SDS) | (SCORE603E_USE_OPEN_FIRMWARE) | (SCORE603E_USE_NONE)
 #define SCORE603E_VME_A16_OFFSET       0x04000000
 #elif (SCORE603E_USE_DINK)
 #define SCORE603E_VME_A16_OFFSET       0x11000000
 #define SCORE603E_VME_A24_OFFSET       0x10000000
-#define SCORE603E_VME_A24_BASE         (SCORE603E_PCI_MEM_BASE+SCORE603E_VME_A24_OFFSET)
+#define BSP_VME_A24_BASE               (BSP_PCI_MEM_BASE+SCORE603E_VME_A24_OFFSET)
 #else
 #error "SCORE603E gen2.h -- what ROM monitor are you using"
 #endif

-#define SCORE603E_VME_A16_BASE         (SCORE603E_PCI_MEM_BASE+SCORE603E_VME_A16_OFFSET)
+#define BSP_VME_A16_BASE               (BSP_PCI_MEM_BASE+SCORE603E_VME_A16_OFFSET)

 /*
 *  Definations for the ICM 1770 RTC chip
@@ -115,7 +114,7 @@ extern "C" {
 #define ICM1770_CRYSTAL_FREQ_2M       0x02
 #define ICM1770_CRYSTAL_FREQ_4M       0x03

-#define SCORE_RTC_FREQUENCY           ICM1770_CRYSTAL_FREQ_32K 
+#define BSP_RTC_FREQUENCY             ICM1770_CRYSTAL_FREQ_32K 

 /*
 *  Z85C30 Definations for the 423 interface.
@@ -158,13 +157,13 @@ extern "C" {
 /*
 * The PMC status word is at the PMC base address 
 */
-#define SCORE603E_PMC_STATUS_ADDRESS  (SCORE603E_PMC_SERIAL_ADDRESS (0))
+#define BSP_PMC_STATUS_ADDRESS  (BSP_PMC_SERIAL_ADDRESS (0))
 #define Is_PMC_85C30_4_IRQ( _status ) (_status & 0x80)    /* SCC 422-1 */
 #define Is_PMC_85C30_2_IRQ( _status ) (_status & 0x40)    /* SCC 232-1 */
 #define Is_PMC_85C30_5_IRQ( _status ) (_status & 0x20)    /* SCC 422-2 */
 #define Is_PMC_85C30_3_IRQ( _status ) (_status & 0x08)    /* SCC 232-2 */

-#define SCORE603E_PMC_CONTROL_ADDRESS    SCORE603E_PMC_SERIAL_ADDRESS(0x100000)
+#define SCORE603E_PMC_CONTROL_ADDRESS    BSP_PMC_SERIAL_ADDRESS(0x100000)
 #define SCORE603E_PMC_SCC_232_LOOPBACK (_word) (_word|0x20)

 #define PMC_SET_232_LOOPBACK(_word)   (_word | 0x02)   
--- a/c/src/lib/libbsp/powerpc/score603e/startup/FPGA.c
+++ b/c/src/lib/libbsp/powerpc/score603e/startup/FPGA.c
@@ -115,7 +115,7 @@ rtems_unsigned16 read_and_clear_PMC_irq(
 {
  rtems_unsigned16    status_word = irq;

-  status_word = (*SCORE603E_PMC_STATUS_ADDRESS);
+  status_word = (*BSP_PMC_STATUS_ADDRESS);

  return status_word;
 }
--- a/c/src/lib/libbsp/powerpc/score603e/startup/Hwr_init.c
+++ b/c/src/lib/libbsp/powerpc/score603e/startup/Hwr_init.c
@@ -76,7 +76,7 @@ void init_RTC()
 {
  volatile Harris_RTC *the_RTC;
  
-  the_RTC = (volatile Harris_RTC *)SCORE603E_RTC_ADDRESS;
+  the_RTC = (volatile Harris_RTC *)BSP_RTC_ADDRESS;

  the_RTC->command_register = 0x0;
 }
--- a/c/src/lib/libbsp/powerpc/score603e/startup/bspstart.c
+++ b/c/src/lib/libbsp/powerpc/score603e/startup/bspstart.c
@@ -116,20 +116,20 @@ void initialize_PMC() {
  /*
   * set PMC base address.
   */
-  PMC_addr  = SCORE603E_PCI_DEVICE_ADDRESS( 0x14 );
-  *PMC_addr = (SCORE603E_PCI_REGISTER_BASE >> 24) & 0x3f;
+  PMC_addr  = BSP_PCI_DEVICE_ADDRESS( 0x14 );
+  *PMC_addr = (BSP_PCI_REGISTER_BASE >> 24) & 0x3f;

  /*
   * Clear status, enable SERR and memory space only.
   */
-  PMC_addr = SCORE603E_PCI_DEVICE_ADDRESS( 0x4 );
+  PMC_addr = BSP_PCI_DEVICE_ADDRESS( 0x4 );
  *PMC_addr = 0x0201ff37;

  /*
   * Bit 0 and 1 HI cause Medium Loopback to occur.
   */
  PMC_addr = (volatile rtems_unsigned32 *)
-        SCORE603E_PMC_SERIAL_ADDRESS( 0x100000 );
+        BSP_PMC_SERIAL_ADDRESS( 0x100000 );
  data = *PMC_addr;
  /*   *PMC_addr = data | 0x3;  */
  *PMC_addr = data & 0xfc;
@@ -142,17 +142,17 @@ void initialize_PMC() {
  /*
   * Clear status, enable SERR and memory space only.
   */
-  PMC_addr = SCORE603E_PCI_DEVICE_ADDRESS( 0x4 );
+  PMC_addr = BSP_PCI_DEVICE_ADDRESS( 0x4 );
  *PMC_addr = 0x020080cc;

  /*
   * set PMC base address.
   */
-  PMC_addr  = SCORE603E_PCI_DEVICE_ADDRESS( 0x14 );
-  *PMC_addr = (SCORE603E_PCI_REGISTER_BASE >> 24) & 0x3f;
+  PMC_addr  = BSP_PCI_DEVICE_ADDRESS( 0x14 );
+  *PMC_addr = (BSP_PCI_REGISTER_BASE >> 24) & 0x3f;

  PMC_addr = (volatile rtems_unsigned32 *)
-      SCORE603E_PMC_SERIAL_ADDRESS( 0x100000 );
+      BSP_PMC_SERIAL_ADDRESS( 0x100000 );
  data = *PMC_addr;
  *PMC_addr = data & 0xfc;

--- a/c/src/lib/libbsp/powerpc/score603e/tod/tod.c
+++ b/c/src/lib/libbsp/powerpc/score603e/tod/tod.c
@@ -43,7 +43,7 @@ void setRealTimeToRTEMS()
 {
  rtems_time_of_day rtc_tod;

-  ICM7170_GetTOD( SCORE603E_RTC_ADDRESS, SCORE_RTC_FREQUENCY, &rtc_tod );
+  ICM7170_GetTOD( BSP_RTC_ADDRESS, BSP_RTC_FREQUENCY, &rtc_tod );
  rtems_clock_set( &rtc_tod );
 }

@@ -52,7 +52,7 @@ void setRealTimeFromRTEMS()
  rtems_time_of_day rtems_tod;

  rtems_clock_get( RTEMS_CLOCK_GET_TOD, &rtems_tod );
-  ICM7170_SetTOD( SCORE603E_RTC_ADDRESS, SCORE_RTC_FREQUENCY, &rtems_tod );
+  ICM7170_SetTOD( BSP_RTC_ADDRESS, BSP_RTC_FREQUENCY, &rtems_tod );
 }

 int checkRealTime()
@@ -60,7 +60,7 @@ int checkRealTime()
  rtems_time_of_day rtems_tod;
  rtems_time_of_day rtc_tod;

-  ICM7170_GetTOD( SCORE603E_RTC_ADDRESS, SCORE_RTC_FREQUENCY, &rtc_tod );
+  ICM7170_GetTOD( BSP_RTC_ADDRESS, BSP_RTC_FREQUENCY, &rtc_tod );
  rtems_clock_get( RTEMS_CLOCK_GET_TOD, &rtems_tod );

  if( rtems_tod.year == rtc_tod.year &&
--- a/c/src/lib/libbsp/powerpc/shared/ChangeLog
+++ b/c/src/lib/libbsp/powerpc/shared/ChangeLog
@@ -1,3 +1,40 @@
+2005-09-01	Joel Sherrill <joel@OARcorp.com>
+
+	* include/bsp.h: This file is only to be used by BSPs with the new
+	interrupt API so checking for USE_ENHANCED_INTR_API is not needed.
+
+2004-11-23	Richard Campbell <richard.campbell@oarcorp.com>
+
+	* startup/bspstart.c: Removed mpc824x conditionals around call to 
+	L1_caches_enables, conditionals are now in mmuAsm.S.
+ 	* vme/VMEConfig.h: Set up VME A16, A24 and A32 windows at different 
+	locations for mvme2100.
+	* vme/vmeconfig.c: Fixed spelling.
+
+2004-11-10	Richard Campbell <richard.campbell@oarcorp.com>
+
+	* ChangeLog, Makefile.am, bootloader/misc.c, bootloader/pci.c,
+	bootloader/pci.h, console/console.c, console/inch.c,
+	console/reboot.c, console/uart.c, console/uart.h, include/bsp.h,
+	irq/irq.c, irq/irq.h, irq/irq_init.c, motorola/motorola.c,
+	motorola/motorola.h, openpic/openpic.c, openpic/openpic.h,
+	pci/detect_raven_bridge.c, pci/pci.c, pci/pci.h, start/start.S,
+	startup/bspstart.c, vectors/vectors_init.c, vme/vmeconfig.c: Add
+	MVME2100 BSP and MPC8240 support. There was also a significant amount
+	of spelling and whitespace cleanup.
+	* tod/.cvsignore, tod/Makefile.am, tod/todcfg.c: New files.
+
+2004-11-10	Richard Campbell <richard.campbell@oarcorp.com>
+
+	* Makefile.am, bootloader/misc.c, bootloader/pci.c, bootloader/pci.h,
+	console/console.c, console/inch.c, console/reboot.c, console/uart.c,
+	console/uart.h, include/bsp.h, irq/irq.c, irq/irq.h, irq/irq_init.c,
+	motorola/motorola.c, motorola/motorola.h, openpic/openpic.c,
+	openpic/openpic.h, pci/detect_raven_bridge.c, pci/pci.c, pci/pci.h,
+	start/start.S, startup/bspstart.c, vectors/vectors_init.c,
+	vme/vmeconfig.c: Add MVME2100 BSP and MPC8240 support.
+	* tod/.cvsignore, tod/Makefile.am, tod/todcfg.c: New files.
+
 2004-09-27      Greg Menke <gregory.menke@gsfc.nasa.gov>

 	PR 606/bsps
--- a/c/src/lib/libbsp/powerpc/shared/Makefile.am
+++ b/c/src/lib/libbsp/powerpc/shared/Makefile.am
@@ -5,7 +5,7 @@

 if need_shared
 SUBDIRS = clock console include pci residual openpic irq vectors start \
-    startup motorola bootloader vme
+    startup motorola bootloader vme tod
 endif

 include $(top_srcdir)/../../../../../automake/subdirs.am
--- a/c/src/lib/libbsp/powerpc/shared/bootloader/misc.c
+++ b/c/src/lib/libbsp/powerpc/shared/bootloader/misc.c
@@ -24,6 +24,7 @@
 #include <libcpu/page.h>
 #include <libcpu/byteorder.h>
 #include <rtems/bspIo.h>
+#include <bsp.h>

 SPR_RW(DEC)
 SPR_RO(PVR)
@@ -280,8 +281,13 @@ setup_hw(void)
 	/* We check that the keyboard is present and immediately 
 	 * select the serial console if not.
 	 */
+#if defined(BSP_KBD_IOBASE)
 	err = kbdreset();
-	if (err) select_console(CONSOLE_SERIAL);
+        if (err) select_console(CONSOLE_SERIAL);
+#else
+	err = 1;
+	select_console(CONSOLE_SERIAL);
+#endif

 	printk("\nModel: %s\nSerial: %s\n"
 	       "Processor/Bus frequencies (Hz): %ld/%ld\n"
@@ -293,8 +299,6 @@ setup_hw(void)
               vpd.ProcessorBusHz,
 	       (vpd.TimeBaseDivisor ? vpd.TimeBaseDivisor : 4000),
 	       res->TotalMemory);
-	printk("Original MSR: %lx\nOriginal HID0: %lx\nOriginal R31: %lx\n",
-	       bd->o_msr, bd->o_hid0, bd->o_r31); 

 	/* This reconfigures all the PCI subsystem */
        pci_init();
--- a/c/src/lib/libbsp/powerpc/shared/bootloader/pci.c
+++ b/c/src/lib/libbsp/powerpc/shared/bootloader/pci.c
@@ -24,6 +24,7 @@
 #include <libcpu/io.h>
 #include <libcpu/page.h>
 #include <bsp/consoleIo.h>
+#include <string.h>

 typedef unsigned int u32;

--- a/c/src/lib/libbsp/powerpc/shared/bootloader/pci.h
+++ b/c/src/lib/libbsp/powerpc/shared/bootloader/pci.h
@@ -497,6 +497,7 @@
 #define PCI_VENDOR_ID_MOTOROLA		0x1057
 #define PCI_DEVICE_ID_MOTOROLA_MPC105	0x0001
 #define PCI_DEVICE_ID_MOTOROLA_MPC106	0x0002
+#define PCI_DEVICE_ID_MOTOROLA_MPC8240	0x0003
 #define PCI_DEVICE_ID_MOTOROLA_RAVEN	0x4801

 #define PCI_VENDOR_ID_PROMISE		0x105a
--- a/c/src/lib/libbsp/powerpc/shared/console/console.c
+++ b/c/src/lib/libbsp/powerpc/shared/console/console.c
@@ -75,7 +75,6 @@ static TtySTblRec ttyS[]={
 		},
 };

-
 /*-------------------------------------------------------------------------+
 | Console device driver INITIALIZE entry point.
 +--------------------------------------------------------------------------+
@@ -135,6 +134,7 @@ console_initialize(rtems_device_major_number major,
 		}

  }
+
  return RTEMS_SUCCESSFUL;
 } /* console_initialize */

@@ -174,22 +174,35 @@ console_open(rtems_device_major_number major,
 {
  rtems_status_code              status;
  static rtems_termios_callbacks cb = 
+#if defined(USE_POLLED_IO)
+  {
+    NULL,				/* firstOpen */
+    NULL,				/* lastClose */
+    NULL,				/* pollRead */
+    BSP_uart_termios_write_polled,	/* write */
+    conSetAttr,				/* setAttributes */
+    NULL,				/* stopRemoteTx */
+    NULL,				/* startRemoteTx */
+    0					/* outputUsesInterrupts */
+  };
+#else
  {
    console_first_open,			/* firstOpen */
    console_last_close,			/* lastClose */
-    NULL,						/* pollRead */
-    BSP_uart_termios_write_com,	/* write */
-    conSetAttr,					/* setAttributes */
-    NULL,						/* stopRemoteTx */
-    NULL,						/* startRemoteTx */
-    1							/* outputUsesInterrupts */
+    NULL,				/* pollRead */
+    BSP_uart_termios_write_com,		/* write */
+    conSetAttr,				/* setAttributes */
+    NULL,				/* stopRemoteTx */
+    NULL,				/* startRemoteTx */
+    1					/* outputUsesInterrupts */
  };
+#endif

  status = rtems_termios_open (major, minor, arg, &cb);

  if(status != RTEMS_SUCCESSFUL)
    {
-      printk("Error openning console device\n");
+      printk("Error opening console device\n");
      return status;
    }

--- a/c/src/lib/libbsp/powerpc/shared/console/inch.c
+++ b/c/src/lib/libbsp/powerpc/shared/console/inch.c
@@ -20,6 +20,7 @@
 */

 #include <bsp.h>
+#if defined(BSP_KBD_IOBASE)
 #include <bsp/irq.h>

 #include "console.inl"
@@ -299,9 +300,4 @@ _IBMPC_inch_sleep(void)
 	
    return c;
 } /* _IBMPC_inch */
-
-
-
-
-
-
+#endif
--- a/c/src/lib/libbsp/powerpc/shared/console/reboot.c
+++ b/c/src/lib/libbsp/powerpc/shared/console/reboot.c
@@ -16,5 +16,7 @@ void rtemsReboot(void)
  printk("Printing a stack trace for your convenience :-)\n");
  CPU_print_stack();
  /* shutdown and reboot */
+#if defined(BSP_KBD_IOBASE)
  kbd_outb(0x4, 0xFE);      /* use keyboard controler to do the job... */
+#endif
 } /* rtemsReboot */
--- a/c/src/lib/libbsp/powerpc/shared/console/uart.c
+++ b/c/src/lib/libbsp/powerpc/shared/console/uart.c
@@ -132,7 +132,7 @@ void
 BSP_uart_init(int uart, int baud, int hwFlow)
 {
  unsigned char tmp;
-  
+ 
  /* Sanity check */
  SANITY_CHECK(uart);
  
@@ -156,10 +156,10 @@ BSP_uart_init(int uart, int baud, int hwFlow)
      assert(0);
      return;
    }
-  
+
  /* Set DLAB bit to 1 */
  uwrite(uart, LCR, DLAB);
-  
+
  /* Set baud rate */
  uwrite(uart, DLL,  (BSPBaseBaud/baud) & 0xff); 
  uwrite(uart, DLM,  ((BSPBaseBaud/baud) >> 8) & 0xff); 
@@ -185,6 +185,7 @@ BSP_uart_init(int uart, int baud, int hwFlow)
  /* Remember state */
  uart_data[uart].hwFlow     = hwFlow;
  uart_data[uart].baud       = baud;
+
  return;
 }

@@ -201,7 +202,7 @@ BSP_uart_set_baud(int uart, int baud)
  
  /* 
   * This function may be called whenever TERMIOS parameters
-   * are changed, so we have to make sire that baud change is 
+   * are changed, so we have to make sure that baud change is 
   * indeed required
   */

@@ -460,8 +461,14 @@ uart_noop(const rtems_irq_connect_data *unused)
 static int
 uart_isr_is_on(const rtems_irq_connect_data *irq)
 {
-int uart = (irq->name == BSP_ISA_UART_COM1_IRQ) ?
+  int uart;
+
+#if defined(mvme2100)
+  uart = BSP_UART_COM1;
+#else
+  uart = (irq->name == BSP_ISA_UART_COM1_IRQ) ?
 			BSP_UART_COM1 : BSP_UART_COM2;
+#endif
  return uread(uart,IER);
 }

@@ -469,8 +476,12 @@ static int
 doit(int uart, rtems_irq_hdl handler, int (*p)(const rtems_irq_connect_data*))
 {
 	rtems_irq_connect_data d={0};
+#if defined(mvme2100)
+        d.name = BSP_UART_COM1_IRQ;
+#else
 	d.name = (uart == BSP_UART_COM1) ? 
 			BSP_ISA_UART_COM1_IRQ : BSP_ISA_UART_COM2_IRQ;
+#endif
 	d.off  = d.on = uart_noop;
 	d.isOn = uart_isr_is_on;
 	d.hdl  = handler;
@@ -525,6 +536,21 @@ BSP_uart_termios_set(int uart, void *ttyp)
  return;
 }

+int
+BSP_uart_termios_write_polled(int minor, const char *buf, int len)
+{
+  int uart=minor;	/* could differ, theoretically */
+  int nwrite;
+  const char *b = buf;
+
+  assert(buf != NULL);
+
+  for (nwrite=0 ; nwrite < len ; nwrite++) {
+    BSP_uart_polled_write(uart, *b++);
+  }
+  return nwrite;
+}
+
 int
 BSP_uart_termios_write_com(int minor, const char *buf, int len)
 {
@@ -536,7 +562,7 @@ BSP_uart_termios_write_com(int minor, const char *buf, int len)
      return 0;
    }

-  /* If there TX buffer is busy - something is royally screwed up */
+  /* If the TX buffer is busy - something is royally screwed up */
  /*   assert((uread(BSP_UART_COM1, LSR) & THRE) != 0); */
       

--- a/c/src/lib/libbsp/powerpc/shared/console/uart.h
+++ b/c/src/lib/libbsp/powerpc/shared/console/uart.h
@@ -16,7 +16,7 @@
 #include <rtems/libio.h>

 void BSP_uart_init(int uart, int baud, int hwFlow);
-void BSP_uart_set_baud(int aurt, int baud);
+void BSP_uart_set_baud(int uart, int baud);
 void BSP_uart_intr_ctrl(int uart, int cmd);
 void BSP_uart_throttle(int uart);
 void BSP_uart_unthrottle(int uart);
@@ -31,6 +31,7 @@ void BSP_uart_dbgisr_com1(void);
 void BSP_uart_dbgisr_com2(void);
 int  BSP_uart_install_isr(int uart, rtems_irq_hdl handler);
 int  BSP_uart_remove_isr(int uart, rtems_irq_hdl handler);
+int  BSP_uart_termios_write_polled(int minor, const char *buf, int len);
 int  BSP_uart_get_break_cb(int uart, rtems_libio_ioctl_args_t *arg);
 int  BSP_uart_set_break_cb(int uart, rtems_libio_ioctl_args_t *arg);

--- a/c/src/lib/libbsp/powerpc/shared/include/bsp.h
+++ b/c/src/lib/libbsp/powerpc/shared/include/bsp.h
@@ -26,28 +26,69 @@
 *   - Interrupt stack space is not minimum if defined.
 */

+#if defined(mvme2100)
+#define CONFIGURE_NUMBER_OF_TERMIOS_PORTS 1
+#else
 #define CONFIGURE_NUMBER_OF_TERMIOS_PORTS 2
+#endif
+
 #define CONFIGURE_INTERRUPT_STACK_MEMORY  (16 * 1024)

-/* fundamental addresses for this BSP (PREPxxx are from libcpu/io.h) */
-#define	_IO_BASE			PREP_ISA_IO_BASE
+/* fundamental addresses for BSP (CHRPxxx and PREPxxx are from libcpu/io.h) */
+#if defined(mvme2100)
+#define	_IO_BASE		CHRP_ISA_IO_BASE
+#define	_ISA_MEM_BASE		CHRP_ISA_MEM_BASE
+/* address of our ram on the PCI bus   */
+#define	PCI_DRAM_OFFSET		CHRP_PCI_DRAM_OFFSET
+#define PCI_MEM_BASE		0x80000000 
+#define PCI_MEM_BASE_ADJUSTMENT	0
+
+#else
+#define	_IO_BASE		PREP_ISA_IO_BASE
 #define	_ISA_MEM_BASE		PREP_ISA_MEM_BASE
 /* address of our ram on the PCI bus   */
 #define	PCI_DRAM_OFFSET		PREP_PCI_DRAM_OFFSET
 /* offset of pci memory as seen from the CPU */
 #define PCI_MEM_BASE		PREP_ISA_MEM_BASE
+#define PCI_MEM_BASE_ADJUSTMENT	PREP_ISA_MEM_BASE
+#endif

 /*
- *  base address definitions for several devices
+ *  Base address definitions for several devices
 *
+ *  MVME2100 is very similar but has fewer devices and uses on-CPU EPIC
+ *  implementation of OpenPIC controller.  It also cannot be probed to
+ *  find out what it is which is VERY different from other Motorola boards.
 */
+
+#if defined(mvme2100)
+#define BSP_UART_IOBASE_COM1 ((_IO_BASE)+0x01e10000)
+/* #define BSP_UART_IOBASE_COM1     (0xffe10000) */
+#define BSP_OPEN_PIC_BASE_OFFSET 0x40000
+
+#define MVME_HAS_DEC21140
+#else
 #define BSP_UART_IOBASE_COM1 ((_IO_BASE)+0x3f8)
 #define BSP_UART_IOBASE_COM2 ((_IO_BASE)+0x2f8)
+
 #define BSP_KBD_IOBASE       ((_IO_BASE)+0x60)
 #define BSP_VGA_IOBASE       ((_IO_BASE)+0x3c0)

-#define BSP_CONSOLE_PORT	BSP_UART_COM1
+#if defined(mvme2300)
+#define MVME_HAS_DEC21140
+#endif
+#endif
+
 #define BSP_UART_BAUD_BASE	115200
+#define BSP_CONSOLE_PORT	BSP_UART_COM1
+
+#if defined(MVME_HAS_DEC21140)
+struct rtems_bsdnet_ifconfig;
+int rtems_dec21140_driver_attach (struct rtems_bsdnet_ifconfig *, int);
+                                                                                
+#define RTEMS_BSP_NETWORK_DRIVER_NAME "dc1"
+#define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_dec21140_driver_attach
+#endif
  
 #include <bsp/openpic.h>
 #define BSP_PIC_DO_EOI openpic_eoi(0)
@@ -110,7 +151,7 @@ extern unsigned long _BSP_clear_hostbridge_errors(int enableMCP, int quiet);
 *  TM27 stuff
 */

-#if defined(USE_ENHANCED_INTR_API) && defined(RTEMS_TM27)
+#if defined(RTEMS_TM27)

 #include <bsp/irq.h>

--- a/c/src/lib/libbsp/powerpc/shared/irq/irq.c
+++ b/c/src/lib/libbsp/powerpc/shared/irq/irq.c
@@ -21,6 +21,7 @@
 #include <libcpu/raw_exception.h>
 #include <libcpu/io.h>
 #include <bsp/vectors.h>
+#include <stdlib.h>

 #include <rtems/bspIo.h> /* for printk */
 #define RAVEN_INTR_ACK_REG 0xfeff0030
@@ -28,7 +29,7 @@
 /*
 * pointer to the mask representing the additionnal irq vectors
 * that must be disabled when a particular entry is activated.
- * They will be dynamically computed from teh prioruty table given
+ * They will be dynamically computed from the priority table given
 * in BSP_rtems_irq_mngt_set();
 * CAUTION : this table is accessed directly by interrupt routine
 * 	     prologue.
@@ -67,7 +68,7 @@ static inline int is_pci_irq(const rtems_irq_symbolic_name irqLine)
 }

 /*
- * Check if IRQ is a Porcessor IRQ
+ * Check if IRQ is a Processor IRQ
 */
 static inline int is_processor_irq(const rtems_irq_symbolic_name irqLine)
 {
@@ -126,7 +127,7 @@ int BSP_install_rtems_shared_irq_handler  (const rtems_irq_connect_data* irq)
 {
    unsigned int level;
    rtems_irq_connect_data* vchain;
-  
+ 
    if (!isValidInterrupt(irq->name)) {
      printk("Invalid interrupt vector %d\n",irq->name);
      return 0;
@@ -191,7 +192,7 @@ int BSP_install_rtems_shared_irq_handler  (const rtems_irq_connect_data* irq)
 int BSP_install_rtems_irq_handler  (const rtems_irq_connect_data* irq)
 {
    unsigned int level;
-  
+ 
    if (!isValidInterrupt(irq->name)) {
      printk("Invalid interrupt vector %d\n",irq->name);
      return 0;
@@ -363,7 +364,7 @@ int BSP_remove_rtems_irq_handler  (const rtems_irq_connect_data* irq)
 }

 /*
- * ------------------------ RTEMS Global Irq Handler Mngt Routines ----------------
+ * RTEMS Global Interrupt Handler Management Routines 
 */

 int BSP_rtems_irq_mngt_set(rtems_irq_global_settings* config)
@@ -517,7 +518,6 @@ void C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum)
  register unsigned msr;
  register unsigned new_msr;

-
  if (excNum == ASM_DEC_VECTOR) {
    _CPU_MSR_GET(msr);
    new_msr = msr | MSR_EE;
@@ -527,8 +527,8 @@ void C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum)

    _CPU_MSR_SET(msr);
    return;
-    
  }
+
  irq = openpic_irq(0);
  if (irq == OPENPIC_VEC_SPURIOUS) {
    ++BSP_spuriousIntr;
--- a/c/src/lib/libbsp/powerpc/shared/irq/irq.h
+++ b/c/src/lib/libbsp/powerpc/shared/irq/irq.h
@@ -1,9 +1,9 @@
 /* irq.h
 *
 *  This include file describe the data structure and the functions implemented
- *  by rtems to write interrupt handlers.
+ *  by RTEMS to write interrupt handlers.
 *
- *  CopyRight (C) 1999 valette@crf.canon.fr
+ *  Copyright (C) 1999 valette@crf.canon.fr
 *
 *  This code is heavilly inspired by the public specification of STREAM V2
 *  that can be found at :
@@ -21,7 +21,6 @@
 #ifndef LIBBSP_POWERPC_MCP750_IRQ_IRQ_H
 #define LIBBSP_POWERPC_MCP750_IRQ_IRQ_H

-
 /*
 * 8259 edge/level control definitions at VIA
 */
@@ -65,71 +64,79 @@ extern "C" {


 /*
- * Symblolic IRQ names and related definitions.
+ * Symbolic IRQ names and related definitions.
 */

 typedef enum {
  /* Base vector for our ISA IRQ handlers. */
-  BSP_ISA_IRQ_VECTOR_BASE	=	BSP_ASM_IRQ_VECTOR_BASE,
+  BSP_ISA_IRQ_VECTOR_BASE	= BSP_ASM_IRQ_VECTOR_BASE,
  /*
   * ISA IRQ handler related definitions
   */
-  BSP_ISA_IRQ_NUMBER    	= 	16,
-  BSP_ISA_IRQ_LOWEST_OFFSET	= 	0,
-  BSP_ISA_IRQ_MAX_OFFSET	= 	BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER - 1,
+  BSP_ISA_IRQ_NUMBER    	= 16,
+  BSP_ISA_IRQ_LOWEST_OFFSET	= 0,
+  BSP_ISA_IRQ_MAX_OFFSET	= BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER - 1,
  /*
   * PCI IRQ handlers related definitions
   * CAUTION : BSP_PCI_IRQ_LOWEST_OFFSET should be equal to OPENPIC_VEC_SOURCE
   */
-  BSP_PCI_IRQ_NUMBER		=	16,
-  BSP_PCI_IRQ_LOWEST_OFFSET	=	BSP_ISA_IRQ_NUMBER,
-  BSP_PCI_IRQ_MAX_OFFSET	= 	BSP_PCI_IRQ_LOWEST_OFFSET + BSP_PCI_IRQ_NUMBER - 1,
+  BSP_PCI_IRQ_NUMBER		= 16,
+  BSP_PCI_IRQ_LOWEST_OFFSET	= BSP_ISA_IRQ_NUMBER,
+  BSP_PCI_IRQ_MAX_OFFSET	= BSP_PCI_IRQ_LOWEST_OFFSET + BSP_PCI_IRQ_NUMBER - 1,
  /*
-   * PowerPc exceptions handled as interrupt where a rtems managed interrupt
+   * PowerPC exceptions handled as interrupt where an RTEMS managed interrupt
   * handler might be connected
   */
-  BSP_PROCESSOR_IRQ_NUMBER	=	1,
-  BSP_PROCESSOR_IRQ_LOWEST_OFFSET = 	BSP_PCI_IRQ_MAX_OFFSET + 1,
-  BSP_PROCESSOR_IRQ_MAX_OFFSET	=	BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER - 1,
+  BSP_PROCESSOR_IRQ_NUMBER	= 1,
+  BSP_PROCESSOR_IRQ_LOWEST_OFFSET = BSP_PCI_IRQ_MAX_OFFSET + 1,
+  BSP_PROCESSOR_IRQ_MAX_OFFSET	= BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER - 1,
  /* Misc vectors for OPENPIC irqs (IPI, timers)
   */
-  BSP_MISC_IRQ_NUMBER		=	8,
-  BSP_MISC_IRQ_LOWEST_OFFSET	=	BSP_PROCESSOR_IRQ_MAX_OFFSET + 1,
-  BSP_MISC_IRQ_MAX_OFFSET	=	BSP_MISC_IRQ_LOWEST_OFFSET + BSP_MISC_IRQ_NUMBER - 1,
+  BSP_MISC_IRQ_NUMBER		= 8,
+  BSP_MISC_IRQ_LOWEST_OFFSET	= BSP_PROCESSOR_IRQ_MAX_OFFSET + 1,
+  BSP_MISC_IRQ_MAX_OFFSET	= BSP_MISC_IRQ_LOWEST_OFFSET + BSP_MISC_IRQ_NUMBER - 1,
  /*
   * Summary
   */
-  BSP_IRQ_NUMBER		= 	BSP_MISC_IRQ_MAX_OFFSET + 1,
-  BSP_LOWEST_OFFSET		=	BSP_ISA_IRQ_LOWEST_OFFSET,
-  BSP_MAX_OFFSET		=	BSP_MISC_IRQ_MAX_OFFSET,
+  BSP_IRQ_NUMBER		= BSP_MISC_IRQ_MAX_OFFSET + 1,
+  BSP_LOWEST_OFFSET		= BSP_ISA_IRQ_LOWEST_OFFSET,
+  BSP_MAX_OFFSET		= BSP_MISC_IRQ_MAX_OFFSET,
    /*
     * Some ISA IRQ symbolic name definition
-     */	       
-  BSP_ISA_PERIODIC_TIMER      	= 	0,
-
-  BSP_ISA_KEYBOARD          	= 	1,
-
-  BSP_ISA_UART_COM2_IRQ		=	3,
-
-  BSP_ISA_UART_COM1_IRQ		=	4,
-
-  BSP_ISA_RT_TIMER1	      	= 	8,
-  
-  BSP_ISA_RT_TIMER3		= 	10,
+     */	
+  BSP_ISA_PERIODIC_TIMER      	=  0,
+  BSP_ISA_KEYBOARD          	=  1,
+  BSP_ISA_UART_COM2_IRQ		=  3,
+  BSP_ISA_UART_COM1_IRQ		=  4,
+  BSP_ISA_RT_TIMER1	      	=  8,
+  BSP_ISA_RT_TIMER3		= 10,
    /*
     * Some PCI IRQ symbolic name definition
     */
-  BSP_PCI_IRQ0			=	BSP_PCI_IRQ_LOWEST_OFFSET,
-  BSP_PCI_ISA_BRIDGE_IRQ	=	BSP_PCI_IRQ0,
+  BSP_PCI_IRQ0			= BSP_PCI_IRQ_LOWEST_OFFSET,
+  BSP_PCI_ISA_BRIDGE_IRQ	= BSP_PCI_IRQ0,
+
+#if defined(mvme2100)
+  BSP_DEC21143_IRQ                = BSP_PCI_IRQ_LOWEST_OFFSET + 1,
+  BSP_PMC_PCMIP_TYPE1_SLOT0_IRQ   = BSP_PCI_IRQ_LOWEST_OFFSET + 2,
+  BSP_PCMIP_TYPE1_SLOT1_IRQ       = BSP_PCI_IRQ_LOWEST_OFFSET + 3,
+  BSP_PCMIP_TYPE2_SLOT0_IRQ       = BSP_PCI_IRQ_LOWEST_OFFSET + 4,
+  BSP_PCMIP_TYPE2_SLOT1_IRQ       = BSP_PCI_IRQ_LOWEST_OFFSET + 5,
+  BSP_PCI_INTA_UNIVERSE_LINT0_IRQ = BSP_PCI_IRQ_LOWEST_OFFSET + 7,
+  BSP_PCI_INTB_UNIVERSE_LINT1_IRQ = BSP_PCI_IRQ_LOWEST_OFFSET + 8,
+  BSP_PCI_INTC_UNIVERSE_LINT2_IRQ = BSP_PCI_IRQ_LOWEST_OFFSET + 9,
+  BSP_PCI_INTD_UNIVERSE_LINT3_IRQ = BSP_PCI_IRQ_LOWEST_OFFSET + 10,
+  BSP_UART_COM1_IRQ               = BSP_PCI_IRQ_LOWEST_OFFSET + 13,
+  BSP_FRONT_PANEL_ABORT_IRQ       = BSP_PCI_IRQ_LOWEST_OFFSET + 14,
+  BSP_RTC_IRQ                     = BSP_PCI_IRQ_LOWEST_OFFSET + 15,
+#endif
+
    /*
-     * Some Processor execption handled as rtems IRQ symbolic name definition
+     * Some Processor exception handled as RTEMS IRQ symbolic name definition
     */
-  BSP_DECREMENTER		=	BSP_PROCESSOR_IRQ_LOWEST_OFFSET
-  
-}rtems_irq_symbolic_name;
-
-    
+  BSP_DECREMENTER		= BSP_PROCESSOR_IRQ_LOWEST_OFFSET

+} rtems_irq_symbolic_name;

 /*
 * Type definition for RTEMS managed interrupts
@@ -162,7 +169,6 @@ typedef struct __rtems_irq_connect_data__ {
       * It is usually called immediately AFTER connecting the interrupt handler.
       * RTEMS may well need such a function when restoring normal interrupt
       * processing after a debug session.
-       * 
       */
      rtems_irq_enable		on;	
      /*
@@ -205,7 +211,7 @@ typedef struct {
  rtems_irq_symbolic_name	irqBase;
  /*
   * software priorities associated with interrupts.
-   * if irqPrio  [i]  >  intrPrio  [j]  it  means  that  
+   * if irqPrio  [i]  >  intrPrio  [j]  it  means  that
   * interrupt handler hdl connected for interrupt name i
   * will  not be interrupted by the handler connected for interrupt j
   * The interrupt source  will be physically masked at i8259 level.
@@ -236,10 +242,10 @@ int BSP_irq_disable_at_i8259s        (const rtems_irq_symbolic_name irqLine);
 */
 int BSP_irq_enable_at_i8259s		(const rtems_irq_symbolic_name irqLine);
 /*
- * function to acknoledge a particular irq at 8259 level. After calling
+ * function to acknowledge a particular irq at 8259 level. After calling
 * this function, if a device asserts an enabled interrupt line it will
- * be propagated further to the processor. Mainly usefull for people
- * writting raw handlers as this is automagically done for rtems managed
+ * be propagated further to the processor. Mainly useful for people
+ * writing raw handlers as this is automagically done for RTEMS managed
 * handlers.
 */
 int BSP_irq_ack_at_i8259s           	(const rtems_irq_symbolic_name irqLine);
@@ -260,18 +266,18 @@ int BSP_irq_enabled_at_i8259s        	(const rtems_irq_symbolic_name irqLine);
 *	3) store the current i8259s' interrupt masks
 *	4) modify them to disable the current interrupt at 8259 level (and may
 *	be others depending on software priorities)
- *	5) aknowledge the i8259s',
+ *	5) acknowledge the i8259s',
 *	6) demask the processor,
 *	7) call the application handler
 *
 * As a result the hdl function provided
 *
 *	a) can perfectly be written is C,
- * 	b) may also well directly call the part of the RTEMS API that can be used
- *	from interrupt level,
- *	c) It only responsible for handling the jobs that need to be done at
- *	the device level including (aknowledging/re-enabling the interrupt at device,
- *	level, getting the data,...)
+ * 	b) may also well directly call the part of the RTEMS API that can be
+ *         used from interrupt level,
+ *	c) It is only responsible for handling the jobs that need to be done at
+ *	   the device level including (acknowledging/re-enabling the interrupt
+ *         at the device level, getting the data,...)
 *
 *	When returning from the function, the following will be performed by
 *	the RTEMS irq epilogue :
@@ -282,7 +288,6 @@ int BSP_irq_enabled_at_i8259s        	(const rtems_irq_symbolic_name irqLine);
 *	4) perform rescheduling when necessary,
 *	5) restore the C scratch registers...
 *	6) restore initial execution flow
- * 
 */
 int BSP_install_rtems_irq_handler   	(const rtems_irq_connect_data*);
 int BSP_install_rtems_shared_irq_handler  (const rtems_irq_connect_data*);
@@ -296,7 +301,8 @@ int BSP_install_rtems_shared_irq_handler  (const rtems_irq_connect_data*);
 int BSP_get_current_rtems_irq_handler	(rtems_irq_connect_data* ptr);
 /*
 * function to get disconnect the RTEMS irq handler for ptr->name.
- * This function checks that the value given is the current one for safety reason.
+ * This function checks that the value given is the current one for safety
+ * reasons.
 * The user can use the previous function to get it.
 */
 int BSP_remove_rtems_irq_handler    	(const rtems_irq_connect_data*);
@@ -329,7 +335,7 @@ int BSP_rtems_irq_mngt_set(rtems_irq_global_settings* config);
 * (Re) get info on current RTEMS interrupt management.
 */
 int BSP_rtems_irq_mngt_get(rtems_irq_global_settings**);
-  
+
 extern void BSP_rtems_irq_mng_init(unsigned cpuId);
 extern void BSP_i8259s_init(void);

--- a/c/src/lib/libbsp/powerpc/shared/irq/irq_init.c
+++ b/c/src/lib/libbsp/powerpc/shared/irq/irq_init.c
@@ -29,10 +29,6 @@
 #include <bsp/motorola.h>
 #include <rtems/bspIo.h>

-/*
-#define SHOW_ISA_PCI_BRIDGE_SETTINGS
-*/
-
 typedef struct {
  unsigned char bus;	/* few chance the PCI/ISA bridge is not on first bus but ... */
  unsigned char device;
@@ -68,14 +64,14 @@ static rtems_irq_connect_data     	defaultIrq = {
 };
 static rtems_irq_prio irqPrioTable[BSP_IRQ_NUMBER]={
  /*
-   * actual rpiorities for interrupt :
+   * actual priorities for interrupt :
   *	0   means that only current interrupt is masked
   *	255 means all other interrupts are masked
   */
  /*
   * ISA interrupts.
   * The second entry has a priority of 255 because
-   * it is the slave pic entry and is should always remain
+   * it is the slave pic entry and should always remain
   * unmasked.
   */
  0,0,
@@ -91,6 +87,45 @@ static rtems_irq_prio irqPrioTable[BSP_IRQ_NUMBER]={
  0
 };

+#if defined(mvme2100)
+static unsigned char mvme2100_openpic_initpolarities[16] = {
+    0,  /* Not used - should be disabled */
+    0,	/* DEC21143 Controller */
+    0,  /* PMC/PC-MIP Type I Slot 0 */
+    0,  /* PC-MIP Type I Slot 1 */
+    0,  /* PC-MIP Type II Slot 0 */
+    0,  /* PC-MIP Type II Slot 1 */
+    0,  /* Not used - should be disabled */
+    0,  /* PCI Expansion Interrupt A/Universe II (LINT0) */
+    0,  /* PCI Expansion Interrupt B/Universe II (LINT1) */
+    0,  /* PCI Expansion Interrupt C/Universe II (LINT2) */
+    0,  /* PCI Expansion Interrupt D/Universe II (LINT3) */
+    0,  /* Not used - should be disabled */
+    0,  /* Not used - should be disabled */
+    1,  /* 16550 UART */
+    0,  /* Front panel Abort Switch */
+    0,  /* RTC IRQ */
+};
+
+static unsigned char mvme2100_openpic_initsenses[] = {
+    0,  /* Not used - should be disabled */
+    1,	/* DEC21143 Controller */
+    1,  /* PMC/PC-MIP Type I Slot 0 */
+    1,  /* PC-MIP Type I Slot 1 */
+    1,  /* PC-MIP Type II Slot 0 */
+    1,  /* PC-MIP Type II Slot 1 */
+    0,  /* Not used - should be disabled */
+    1,  /* PCI Expansion Interrupt A/Universe II (LINT0) */
+    1,  /* PCI Expansion Interrupt B/Universe II (LINT1) */
+    1,  /* PCI Expansion Interrupt C/Universe II (LINT2) */
+    1,  /* PCI Expansion Interrupt D/Universe II (LINT3) */
+    0,  /* Not used - should be disabled */
+    0,  /* Not used - should be disabled */
+    1,  /* 16550 UART */
+    0,  /* Front panel Abort Switch */
+    1,  /* RTC IRQ */
+};
+#else
 static unsigned char mcp750_openpic_initpolarities[16] = {
    1,  /* 8259 cascade */
    0,	/* all the rest of them */
@@ -114,6 +149,7 @@ static unsigned char mcp750_openpic_initsenses[] = {
    1,	/* MCP750_INT_PCI_BUS2_INTC */
    1,	/* MCP750_INT_PCI_BUS2_INTD */
 };
+#endif

 void VIA_isa_bridge_interrupts_setup(void)
 {
@@ -226,17 +262,28 @@ loop_exit:
   */
 void BSP_rtems_irq_mng_init(unsigned cpuId)
 {
-  rtems_raw_except_connect_data vectorDesc;
+#if !defined(mvme2100)
  int known_cpi_isa_bridge = 0;
+#endif
+  rtems_raw_except_connect_data vectorDesc;
  int i;
  
  /*
   * First initialize the Interrupt management hardware
   */
-#ifdef TRACE_IRQ_INIT  
+#if defined(mvme2100)
+#ifdef TRACE_IRQ_INIT 
+  printk("Going to initialize EPIC interrupt controller (openpic compliant)\n");
+#endif
+  openpic_init(1, mvme2100_openpic_initpolarities, mvme2100_openpic_initsenses);
+#else
+#ifdef TRACE_IRQ_INIT 
  printk("Going to initialize raven interrupt controller (openpic compliant)\n");
-#endif       
+#endif
  openpic_init(1, mcp750_openpic_initpolarities, mcp750_openpic_initsenses);
+#endif       
+
+#if !defined(mvme2100)
 #ifdef TRACE_IRQ_INIT  
  printk("Going to initialize the PCI/ISA bridge IRQ related setting (VIA 82C586)\n");
 #endif
@@ -261,9 +308,12 @@ void BSP_rtems_irq_mng_init(unsigned cpuId)
 #ifdef TRACE_IRQ_INIT  
  printk("Going to initialize the ISA PC legacy IRQ management hardware\n");
 #endif       
+
  BSP_i8259s_init();
+#endif
+
  /*
-   * Initialize Rtems management interrupt table
+   * Initialize RTEMS management interrupt table
   */
    /*
     * re-init the rtemsIrq table
@@ -309,8 +359,8 @@ void BSP_rtems_irq_mng_init(unsigned cpuId)
    if (!mpc60x_set_exception (&vectorDesc)) {
      BSP_panic("Unable to initialize RTEMS external raw exception\n");
    }
-#ifdef TRACE_IRQ_INIT  
-    printk("RTEMS IRQ management is now operationnal\n");
+#ifdef TRACE_IRQ_INIT
+    printk("RTEMS IRQ management is now operational\n");
 #endif
 }

--- a/c/src/lib/libbsp/powerpc/shared/motorola/motorola.c
+++ b/c/src/lib/libbsp/powerpc/shared/motorola/motorola.c
@@ -12,7 +12,7 @@
 *  $Id$
 */

-
+#include <bsp.h>
 #include <bsp/motorola.h>
 #include <rtems/bspIo.h>
 #include <libcpu/io.h>
@@ -20,8 +20,8 @@


 /*
-** Board-specific table that maps interrupt names to onboard pci
-** peripherals as well as local pci busses.  This table is used at
+** Board-specific table that maps interrupt names to onboard PCI
+** peripherals as well as local PCI busses.  This table is used at
 ** bspstart() to configure the interrupt name & pin for all devices that
 ** do not have it already specified.  If the device is already
 ** configured, we leave it alone but sanity check & print a warning if
@@ -116,12 +116,18 @@ static struct _int_map mtx603_intmap[] = {

   NULL_INTMAP };

+static struct _int_map mvme2100_intmap[] = {
+   {0, 0, 0, {{1, {16,-1,-1,-1}}, /* something shows up in slot 0 and OpenPIC */
+                                  /* 0 is unused.  This hushes the init code. */
+               NULL_PINMAP}},

+   {0, 13, 0, {{1, {23,24,25,26}},  /* PCI INT[A-D]/Universe Lint[0-3] */
+               NULL_PINMAP}},

+   {0, 14, 0, {{1, {17,-1,-1,-1}},  /* onboard ethernet */
+               NULL_PINMAP}},

-
-
-
+   NULL_INTMAP };

 /*
 * This table represents the standard PCI swizzle defined in the
@@ -141,14 +147,6 @@ static int prep_pci_swizzle(int slot, int pin)
   return prep_pci_intpins[ slot % 4 ][ pin-1 ];
 }

-
-
-
-
-
-
-
-
 typedef struct {
  /*
   * 0x100 mask assumes for Raven and Hawk boards
@@ -163,7 +161,6 @@ typedef struct {
      int               (*swizzler)(int, int);
 } mot_info_t;

-
 static const mot_info_t mot_boards[] = {
  {0x300, 0x00, "MVME 2400", NULL, NULL},
  {0x010, 0x00, "Genesis", NULL, NULL},
@@ -185,13 +182,13 @@ static const mot_info_t mot_boards[] = {
  {0x1E0, 0xFD, "MVME 3600 with MVME712M", NULL, NULL},
  {0x1E0, 0xFE, "MVME 3600 with MVME761", NULL, NULL},
  {0x1E0, 0xFF, "MVME 1600-001 or 1600-011", NULL, NULL},
-  {0x000, 0x00, ""}
+  {0x000, 0x00, ""},   /* end of probeable values for automatic scan */
+  {0x000, 0x00, "MVME 2100", mvme2100_intmap, prep_pci_swizzle},
 };

-
-
 prep_t currentPrepType;
-motorolaBoard		currentBoard;
+motorolaBoard currentBoard;
+
 prep_t checkPrepBoardType(RESIDUAL *res)
 {
  prep_t PREP_type;
@@ -213,13 +210,22 @@ prep_t checkPrepBoardType(RESIDUAL *res)
  return PREP_type;
 }

-motorolaBoard	getMotorolaBoard()
+motorolaBoard getMotorolaBoard()
 {
+/*
+ *  At least the MVME2100 does not have the CPU Type and Base Type Registers,
+ *  so it cannot be probed.
+ *
+ *  NOTE: Every path must set currentBoard.
+ */
+#if defined(mvme2100)
+  currentBoard = (motorolaBoard) MVME_2100;
+#else
  unsigned char  cpu_type;
  unsigned char  base_mod;
  int	       	 entry;
  int	       	 mot_entry = -1;
-
+  
  cpu_type = inb(MOTOROLA_CPUTYPE_REG) & 0xF0;
  base_mod = inb(MOTOROLA_BASETYPE_REG);

@@ -234,7 +240,7 @@ motorolaBoard	getMotorolaBoard()
      
    if (mot_boards[entry].base_type != base_mod)
      continue;
-    else{
+    else {
      mot_entry = entry;
      break;
    }
@@ -247,6 +253,7 @@ motorolaBoard	getMotorolaBoard()
    return currentBoard;
  }
  currentBoard = (motorolaBoard) mot_entry;
+#endif
  return currentBoard;
 }

@@ -261,6 +268,7 @@ const char* motorolaBoardToString(motorolaBoard board)
 const struct _int_map *motorolaIntMap(motorolaBoard board)
 {
  if (board == MOTOROLA_UNKNOWN) return NULL;
+  /* printk( "IntMap board %d 0x%08x\n", board, mot_boards[board].intmap ); */
  return mot_boards[board].intmap;
 }

--- a/c/src/lib/libbsp/powerpc/shared/motorola/motorola.h
+++ b/c/src/lib/libbsp/powerpc/shared/motorola/motorola.h
@@ -52,6 +52,8 @@ typedef enum {
  MVME_3600_W_MVME712M		= 17,
  MVME_3600_W_MVME761		= 18,
  MVME_1600			= 19,
+  /* In the table, slot 20 is the marker for end of automatic probe and scan */
+  MVME_2100			= 21,
  MOTOROLA_UNKNOWN		= 255
 } motorolaBoard;

@@ -59,7 +61,7 @@ typedef enum {
  HOST_BRIDGE_RAVEN	= 0,
  HOST_BRIDGE_HAWK	= 1,
  HOST_BRIDGE_UNKNOWN	= 255
-}motorolaHostBridge;
+} motorolaHostBridge;
  
 #define MOTOROLA_CPUTYPE_REG	0x800
 #define MOTOROLA_BASETYPE_REG	0x803  
--- a/c/src/lib/libbsp/powerpc/shared/openpic/openpic.c
+++ b/c/src/lib/libbsp/powerpc/shared/openpic/openpic.c
@@ -20,12 +20,12 @@
 */

 #include <rtems.h>
+#include <bsp.h>
 #include <rtems/bspIo.h>
 #include <bsp/openpic.h>
 #include <bsp/pci.h>
 #include <libcpu/io.h>
 #include <libcpu/byteorder.h>
-#include <bsp.h>
 #include <rtems/bspIo.h>

 #ifndef NULL
@@ -198,7 +198,9 @@ void openpic_init(int main_pic, unsigned char *polarities, unsigned char *senses
 	       OPENPIC_VENDOR_ID_STEPPING_SHIFT;

    /* Kludge for the Raven */
+/*
    pci_read_config_dword(0, 0, 0, 0, &t);
+*/
    if (t == PCI_VENDOR_ID_MOTOROLA + (PCI_DEVICE_ID_MOTOROLA_RAVEN<<16)) {
    	vendor = "Motorola";
 	device = "Raven";
@@ -479,6 +481,11 @@ unsigned long flags;

 void openpic_initirq(unsigned int irq, unsigned int pri, unsigned int vec, int pol, int sense)
 {
+#if 0
+  printk("openpic_initirq: irq=%d pri=%d vec=%d pol=%d sense=%d\n",
+    irq, pri, vec, pol, sense);
+#endif
+
    check_arg_irq(irq);
    check_arg_pri(pri);
    check_arg_vec(vec);
--- a/c/src/lib/libbsp/powerpc/shared/openpic/openpic.h
+++ b/c/src/lib/libbsp/powerpc/shared/openpic/openpic.h
@@ -37,12 +37,15 @@
 #ifndef _RTEMS_OPENPIC_H
 #define _RTEMS_OPENPIC_H

-
    /*
     *  OpenPIC supports up to 2048 interrupt sources and up to 32 processors
     */

+#if defined(mpc8240) || defined(mpc8245)
+#define OPENPIC_MAX_SOURCES	(2048 - 16)
+#else
 #define OPENPIC_MAX_SOURCES	2048
+#endif
 #define OPENPIC_MAX_PROCESSORS	32

 #define OPENPIC_NUM_TIMERS	4
@@ -157,6 +160,9 @@ typedef struct _OpenPIC_Global {
    OpenPIC_Reg _Timer_Frequency;		/* Read/Write */
    OpenPIC_Timer Timer[OPENPIC_NUM_TIMERS];
    char Pad1[0xee00];
+#if defined(mpc8240) || defined(mpc8245)
+    char Pad2[0x0200];
+#endif
 } OpenPIC_Global;


--- a/c/src/lib/libbsp/powerpc/shared/pci/detect_raven_bridge.c
+++ b/c/src/lib/libbsp/powerpc/shared/pci/detect_raven_bridge.c
@@ -12,20 +12,22 @@
 #include <bsp/openpic.h>

 #include <rtems/bspIo.h>
+#include <libcpu/cpuIdent.h>

-#define RAVEN_MPIC_IOSPACE_ENABLE	0x1
-#define RAVEN_MPIC_MEMSPACE_ENABLE	0x2
-#define RAVEN_MASTER_ENABLE		0x4
-#define RAVEN_PARITY_CHECK_ENABLE	0x40
-#define RAVEN_SYSTEM_ERROR_ENABLE	0x100
-#define RAVEN_CLEAR_EVENTS_MASK		0xf9000000
+#define RAVEN_MPIC_IOSPACE_ENABLE  0x0001
+#define RAVEN_MPIC_MEMSPACE_ENABLE 0x0002
+#define RAVEN_MASTER_ENABLE        0x0004
+#define RAVEN_PARITY_CHECK_ENABLE  0x0040
+#define RAVEN_SYSTEM_ERROR_ENABLE  0x0100
+#define RAVEN_CLEAR_EVENTS_MASK    0xf9000000

-#define RAVEN_MPIC_MEREN		((volatile unsigned *)0xfeff0020)
-#define RAVEN_MPIC_MERST		((volatile unsigned *)0xfeff0024)
+#define RAVEN_MPIC_MEREN    ((volatile unsigned *)0xfeff0020)
+#define RAVEN_MPIC_MERST    ((volatile unsigned *)0xfeff0024)
 /* enable machine check on all conditions */
-#define MEREN_VAL				0x2f00
+#define MEREN_VAL           0x2f00

 #define pci BSP_pci_configuration
+extern unsigned int EUMBBAR;

 extern const pci_config_access_functions pci_direct_functions;
 extern const pci_config_access_functions pci_indirect_functions;
@@ -35,48 +37,63 @@ _BSP_clear_hostbridge_errors(int enableMCP, int quiet)
 {
 unsigned merst;

-		merst = in_be32(RAVEN_MPIC_MERST);
-		/* write back value to clear status */
-		out_be32(RAVEN_MPIC_MERST, merst);
+    merst = in_be32(RAVEN_MPIC_MERST);
+    /* write back value to clear status */
+    out_be32(RAVEN_MPIC_MERST, merst);

-		if (enableMCP) {
-			if (!quiet)
-				printk("Enabling MCP generation on hostbridge errors\n");
-			out_be32(RAVEN_MPIC_MEREN, MEREN_VAL);
-		} else {
-			out_be32(RAVEN_MPIC_MEREN, 0);
-			if ( !quiet && enableMCP ) {
-				printk("leaving MCP interrupt disabled\n");
-			}
-		}
-		return (merst & 0xffff);
+    if (enableMCP) {
+      if (!quiet)
+        printk("Enabling MCP generation on hostbridge errors\n");
+      out_be32(RAVEN_MPIC_MEREN, MEREN_VAL);
+    } else {
+      out_be32(RAVEN_MPIC_MEREN, 0);
+      if ( !quiet && enableMCP ) {
+        printk("leaving MCP interrupt disabled\n");
+      }
+    }
+    return (merst & 0xffff);
 }

 void detect_host_bridge()
 {
+#if (defined(mpc8240) || defined(mpc8245))
+  /*
+   * If the processor is an 8240 or an 8245 then the PIC is built
+   * in instead of being on the PCI bus. The MVME2100 is using Processor
+   * Address Map B (CHRP) although the Programmer's Reference Guide says
+   * it defaults to Map A.
+   */
+  /* We have an EPIC Interrupt Controller  */
+  OpenPIC = (volatile struct OpenPIC *) (EUMBBAR + BSP_OPEN_PIC_BASE_OFFSET);
+  pci.pci_functions = &pci_indirect_functions;
+  pci.pci_config_addr = (volatile unsigned char *) 0xfec00000;
+  pci.pci_config_data = (volatile unsigned char *) 0xfee00000;
+#else
+
  PPC_DEVICE *hostbridge;
  unsigned int id0;
  unsigned int tmp;
-  
+
  /*
   * This code assumes that the host bridge is located at
   * bus 0, dev 0, func 0 AND that the old pre PCI 2.1
   * standart devices detection mecahnism that was used on PC
   * (still used in BSD source code) works.
   */
-  hostbridge=residual_find_device(&residualCopy, PROCESSORDEVICE, NULL, 
-				  BridgeController,
-				  PCIBridge, -1, 0);
+  hostbridge=residual_find_device(&residualCopy, PROCESSORDEVICE, NULL,
+            BridgeController,
+            PCIBridge, -1, 0);
+
  if (hostbridge) {
    if (hostbridge->DeviceId.Interface==PCIBridgeIndirect) {
      pci.pci_functions=&pci_indirect_functions;
-      /* Should be extracted from residual data, 
+      /* Should be extracted from residual data,
       * indeed MPC106 in CHRP mode is different,
       * but we should not use residual data in
-       * this case anyway. 
+       * this case anyway.
       */
-      pci.pci_config_addr = ((volatile unsigned char *) 
-			      (ptr_mem_map->io_base+0xcf8));
+      pci.pci_config_addr = ((volatile unsigned char *)
+             (ptr_mem_map->io_base+0xcf8));
      pci.pci_config_data = ptr_mem_map->io_base+0xcfc;
    } else if(hostbridge->DeviceId.Interface==PCIBridgeDirect) {
      pci.pci_functions=&pci_direct_functions;
@@ -87,14 +104,15 @@ void detect_host_bridge()
    /* Let us try by experimentation at our own risk! */
    pci.pci_functions = &pci_direct_functions;
    /* On all direct bridges I know the host bridge itself
-     * appears as device 0 function 0. 
-		 */
+     * appears as device 0 function 0.
+     */
    pci_read_config_dword(0, 0, 0, PCI_VENDOR_ID, &id0);
    if (id0==~0U) {
      pci.pci_functions = &pci_indirect_functions;
-      pci.pci_config_addr = ((volatile unsigned char*)
-			      (ptr_mem_map->io_base+0xcf8));
-      pci.pci_config_data = ((volatile unsigned char*)ptr_mem_map->io_base+0xcfc);
+      pci.pci_config_addr = (volatile unsigned char*)
+              (ptr_mem_map->io_base+0xcf8);
+      pci.pci_config_data = (volatile unsigned char*)
+                              (ptr_mem_map->io_base+0xcfc);
    }
    /* Here we should check that the host bridge is actually
     * present, but if it not, we are in such a desperate
@@ -102,40 +120,42 @@ void detect_host_bridge()
     */
  }
  pci_read_config_dword(0, 0, 0, 0, &id0);
+
  if(id0 == PCI_VENDOR_ID_MOTOROLA +
     (PCI_DEVICE_ID_MOTOROLA_RAVEN<<16)) {
    /*
     * We have a Raven bridge. We will get information about its settings
     */
    pci_read_config_dword(0, 0, 0, PCI_COMMAND, &id0);
-#ifdef SHOW_RAVEN_SETTING    
+#ifdef SHOW_RAVEN_SETTING
    printk("RAVEN PCI command register = %x\n",id0);
-#endif    
+#endif
    id0 |= RAVEN_CLEAR_EVENTS_MASK;
    pci_write_config_dword(0, 0, 0, PCI_COMMAND, id0);
    pci_read_config_dword(0, 0, 0, PCI_COMMAND, &id0);
-#ifdef SHOW_RAVEN_SETTING    
+#ifdef SHOW_RAVEN_SETTING
    printk("After error clearing RAVEN PCI command register = %x\n",id0);
-#endif    
-    
+#endif
+
    if (id0 & RAVEN_MPIC_IOSPACE_ENABLE) {
      pci_read_config_dword(0, 0, 0,PCI_BASE_ADDRESS_0, &tmp);
-#ifdef SHOW_RAVEN_SETTING    
-      printk("Raven MPIC is accessed via IO Space Access at address : %x\n",(tmp & ~0x1));
-#endif    
+#ifdef SHOW_RAVEN_SETTING
+      printk("Raven MPIC is accessed via IO Space Access at address : %x\n",
+          (tmp & ~0x1));
+#endif
    }
    if (id0 & RAVEN_MPIC_MEMSPACE_ENABLE) {
      pci_read_config_dword(0, 0, 0,PCI_BASE_ADDRESS_1, &tmp);
-#ifdef SHOW_RAVEN_SETTING    
-      printk("Raven MPIC is accessed via memory Space Access at address : %x\n", tmp);
-#endif    
+#ifdef SHOW_RAVEN_SETTING
+      printk("Raven MPIC is accessed via memory Space Access"
+             "at address : %x\n", tmp)
+#endif
      OpenPIC=(volatile struct OpenPIC *) (tmp + PREP_ISA_MEM_BASE);
-      printk("OpenPIC found at %x.\n",
-	     OpenPIC);
+      printk("OpenPIC found at %x.\n", OpenPIC);
    }
  }
+#endif
  if (OpenPIC == (volatile struct OpenPIC *)0) {
    BSP_panic("OpenPic Not found\n");
  }
-
 }
--- a/c/src/lib/libbsp/powerpc/shared/pci/pci.c
+++ b/c/src/lib/libbsp/powerpc/shared/pci/pci.c
@@ -1,9 +1,9 @@
 /*
 * pci.c :  this file contains basic PCI Io functions.
 *
- *  CopyRight (C) 1999 valette@crf.canon.fr
+ *  Copyright (C) 1999 valette@crf.canon.fr
 *
- *  This code is heavilly inspired by the public specification of STREAM V2
+ *  This code is heavily inspired by the public specification of STREAM V2
 *  that can be found at :
 *
 *      <http://www.chorus.com/Documentation/index.html> by following
@@ -217,17 +217,6 @@ const pci_config_access_functions pci_direct_functions = {
 };


-
-
-
-
-
-
-
-
-
-
-
 #define PRINT_MSG() \
             printk("pci : Device %d:%02x routed to interrupt_line %d\n", pbus, pslot, int_name )

@@ -236,9 +225,15 @@ const pci_config_access_functions pci_direct_functions = {
 ** Validate a test interrupt name and print a warning if its not one of
 ** the names defined in the routing record.
 */
-static int test_intname( struct _int_map *row, int pbus, int pslot, int int_pin, int int_name )
+static int test_intname(
+  const struct _int_map *row,
+  int pbus,
+  int pslot,
+  int int_pin,
+  int int_name
+)
 {
-   int j,k;
+   int j, k;
   int _nopin= -1, _noname= -1;

   for(j=0; row->pin_route[j].pin > -1; j++)
@@ -333,7 +328,7 @@ static int FindPCIbridge( int mybus, struct pcibridge *pb )



-void FixupPCI( struct _int_map *bspmap, int (*swizzler)(int,int) )
+void FixupPCI( const struct _int_map *bspmap, int (*swizzler)(int,int) )
 {
   unsigned char        cvalue;
   unsigned16           devid;
--- a/c/src/lib/libbsp/powerpc/shared/pci/pci.h
+++ b/c/src/lib/libbsp/powerpc/shared/pci/pci.h
@@ -1164,7 +1164,7 @@ struct _int_map
      struct _pin_routes pin_route[5];
 };

-void FixupPCI( struct _int_map *, int (*swizzler)(int,int) );
+void FixupPCI( const struct _int_map *, int (*swizzler)(int,int) );


 /* scan for a specific device */
--- a/c/src/lib/libbsp/powerpc/shared/start/start.S
+++ b/c/src/lib/libbsp/powerpc/shared/start/start.S
@@ -14,6 +14,7 @@
 #include <asm.h>
 #include <rtems/score/cpu.h>
 #include <libcpu/io.h>
+#include <bspopts.h>

 #define SYNC \
 	sync; \
@@ -28,7 +29,6 @@
 	li	r10,0x63	;	\
 	sc

-		
 	.text
 	.globl	__rtems_entry_point
 	.type	__rtems_entry_point,@function
@@ -67,13 +67,24 @@ __rtems_entry_point:
 * of RAM to KERNELBASE. 
 */
 	lis	r11,KERNELBASE@h
-	ori	r11,r11,0x1ffe		/* set up BAT registers for 604 */
+/* set up BAT registers for 604 */
+	ori	r11,r11,0x1ffe		
 	li	r8,2			/* R/W access */
 	isync
+#if defined(mvme2100)
+        /* BSP_vme_config() wants to use BAT0, this board will use the
+         * available BAT1 to map RAM.
+         */
+	mtspr	DBAT1L,r8		/* N.B. 6xx (not 601) have valid */
+	mtspr	DBAT1U,r11		/* bit in upper BAT register */
+	mtspr	IBAT1L,r8
+	mtspr	IBAT1U,r11
+#else
 	mtspr	DBAT0L,r8		/* N.B. 6xx (not 601) have valid */
 	mtspr	DBAT0U,r11		/* bit in upper BAT register */
 	mtspr	IBAT0L,r8
 	mtspr	IBAT0U,r11
+#endif
 	isync

 /*
@@ -87,7 +98,7 @@ __rtems_entry_point:
 	
 enter_C_code:
 	bl	MMUon
-	bl  __eabi	/* setup EABI and SYSV environment */
+	bl      __eabi	/* setup EABI and SYSV environment */
 	bl	zero_bss
 	/*
 	 * restore prep boot params
@@ -105,7 +116,8 @@ enter_C_code:
        addi	r9,r9, __rtems_end+(4096-CPU_MINIMUM_STACK_FRAME_SIZE)@l
 	mr	r1, r9
 	/*
-	 * We are know in a environment that is totally independent from bootloader setup.
+	 * We are now in a environment that is totally independent from 
+         * bootloader setup.
 	 */
        lis	r5,environ@ha
        la	r5,environ@l(r5)	/* environp */
@@ -113,16 +125,19 @@ enter_C_code:
 	li	r3, 0			/* argc */
 	bl	boot_card
 	bl	_return_to_ppcbug
-	
+
 	.globl  MMUon
 	.type	MMUon,@function
-MMUon:	
+MMUon:
 	mfmsr	r0
-#if (PPC_HAS_FPU == 0)
 	ori	r0,r0, MSR_IP | MSR_RI | MSR_IR | MSR_DR | MSR_EE | MSR_FE0 | MSR_FE1 | MSR_FP
+#if defined(mvme2100)
+        /* Data addr translation is broken for the mvme2100, disable it here */
+	xori	r0,r0, MSR_DR
+#endif
+#if (PPC_HAS_FPU == 0)
 	xori	r0, r0, MSR_EE | MSR_IP | MSR_FP
 #else
-	ori	r0,r0, MSR_IP | MSR_RI | MSR_IR | MSR_DR | MSR_EE | MSR_FE0 | MSR_FE1 | MSR_FP
 	xori	r0, r0, MSR_EE | MSR_IP | MSR_FE0 | MSR_FE1
 #endif
 	mflr	r11
@@ -130,10 +145,10 @@ MMUon:
 	mtsrr1	r0
 	SYNC
 	rfi
-	
+
 	.globl  MMUoff
 	.type	MMUoff,@function
-MMUoff:	
+MMUoff: 
 	mfmsr	r0
 	ori	r0,r0,MSR_IR| MSR_DR | MSR_IP
 	mflr	r11
--- a/c/src/lib/libbsp/powerpc/shared/startup/bspstart.c
+++ b/c/src/lib/libbsp/powerpc/shared/startup/bspstart.c
@@ -19,6 +19,7 @@

 #include <string.h>

+#include <bsp.h>
 #include <rtems/libio.h>
 #include <rtems/libcsupport.h>
 #include <bsp/consoleIo.h>
@@ -28,7 +29,6 @@
 #include <bsp/openpic.h>
 #include <bsp/irq.h>
 #include <bsp/VME.h>
-#include <bsp.h>
 #include <libcpu/bat.h>
 #include <libcpu/pte121.h>
 #include <libcpu/cpuIdent.h>
@@ -48,6 +48,41 @@ extern void			BSP_vme_config();
 SPR_RW(SPRG0)
 SPR_RW(SPRG1)

+#if defined(DEBUG_BATS)
+void printBAT( int bat, unsigned32 upper, unsigned32 lower )
+{
+  unsigned32 lowest_addr;
+  unsigned32 size;
+
+  printk("BAT%d raw(upper=0x%08x, lower=0x%08x) ", bat, upper, lower );
+
+  lowest_addr = (upper & 0xFFFE0000);
+  size = (((upper & 0x00001FFC) >> 2) + 1) * (128 * 1024);
+  printk(" range(0x%08x, 0x%08x) %s%s %s%s%s%s %s\n",
+    lowest_addr,
+    lowest_addr + (size - 1),
+    (upper & 0x01) ? "P" : "p",
+    (upper & 0x02) ? "S" : "s",
+    (lower & 0x08) ? "G" : "g",
+    (lower & 0x10) ? "M" : "m",
+    (lower & 0x20) ? "I" : "i",
+    (lower & 0x40) ? "W" : "w",
+    (lower & 0x01) ? "Read Only" :
+      ((lower & 0x02) ? "Read/Write" : "No Access")
+  );
+}
+
+void ShowBATS(){
+  unsigned32 lower;
+  unsigned32 upper;
+
+  __MFSPR(536, upper); __MFSPR(537, lower); printBAT( 0, upper, lower );
+  __MFSPR(538, upper); __MFSPR(539, lower); printBAT( 1, upper, lower );
+  __MFSPR(540, upper); __MFSPR(541, lower); printBAT( 2, upper, lower );
+  __MFSPR(542, upper); __MFSPR(543, lower); printBAT( 3, upper, lower );
+}
+#endif
+
 /*
 * Copy of residuals passed by firmware
 */
@@ -130,28 +165,28 @@ void bsp_libc_init( void *, unsigned32, int );
 
 void bsp_pretasking_hook(void)
 {
-    rtems_unsigned32        heap_start;    
-    rtems_unsigned32        heap_size;
-    rtems_unsigned32        heap_sbrk_spared;
-	extern rtems_unsigned32 _bsp_sbrk_init(rtems_unsigned32, rtems_unsigned32*);
+  rtems_unsigned32        heap_start;    
+  rtems_unsigned32        heap_size;
+  rtems_unsigned32        heap_sbrk_spared;
+  extern rtems_unsigned32 _bsp_sbrk_init(rtems_unsigned32, rtems_unsigned32*);

-    heap_start = ((rtems_unsigned32) __rtems_end) +INIT_STACK_SIZE + INTR_STACK_SIZE;
-    if (heap_start & (CPU_ALIGNMENT-1))
-        heap_start = (heap_start + CPU_ALIGNMENT) & ~(CPU_ALIGNMENT-1);
+  heap_start = ((rtems_unsigned32) __rtems_end) +
+                INIT_STACK_SIZE + INTR_STACK_SIZE;
+  if (heap_start & (CPU_ALIGNMENT-1))
+      heap_start = (heap_start + CPU_ALIGNMENT) & ~(CPU_ALIGNMENT-1);

-    heap_size = (BSP_mem_size - heap_start) - BSP_Configuration.work_space_size;
-
-	heap_sbrk_spared=_bsp_sbrk_init(heap_start, &heap_size);
+  heap_size = (BSP_mem_size - heap_start) - BSP_Configuration.work_space_size;
+  heap_sbrk_spared=_bsp_sbrk_init(heap_start, &heap_size);

 #ifdef SHOW_MORE_INIT_SETTINGS
-   	printk(" HEAP start %x  size %x (%x bytes spared for sbrk)\n", heap_start, heap_size, heap_sbrk_spared);
+  printk( "HEAP start %x  size %x (%x bytes spared for sbrk)\n",
+             heap_start, heap_size, heap_sbrk_spared);
 #endif    

-    bsp_libc_init((void *) 0, heap_size, heap_sbrk_spared);
-
+  bsp_libc_init((void *) 0, heap_size, heap_sbrk_spared);

 #ifdef RTEMS_DEBUG
-    rtems_debug_enable( RTEMS_DEBUG_ALL_MASK );
+  rtems_debug_enable( RTEMS_DEBUG_ALL_MASK );
 #endif
 }

@@ -173,6 +208,33 @@ void save_boot_params(RESIDUAL* r3, void *r4, void* r5, char *additional_boot_op
  loaderParam[MAX_LOADER_ADD_PARM - 1] ='\0';
 }

+#if defined(mpc8240) || defined(mpc8245)
+unsigned int EUMBBAR;
+
+/* 
+ * Return the current value of the Embedded Utilities Memory Block Base Address
+ * Register (EUMBBAR) as read from the processor configuration register using
+ * Processor Address Map B (CHRP).
+ */ 
+unsigned int get_eumbbar() {
+  register int a, e;
+
+  asm volatile( "lis %0,0xfec0; ori  %0,%0,0x0000": "=r" (a) );
+  asm volatile("sync");
+                                                                
+  asm volatile("lis %0,0x8000; ori %0,%0,0x0078": "=r"(e) ); 
+  asm volatile("stwbrx  %0,0x0,%1": "=r"(e): "r"(a));  
+  asm volatile("sync");
+
+  asm volatile("lis %0,0xfee0; ori %0,%0,0x0000": "=r" (a) ); 
+  asm volatile("sync");
+                                                         
+  asm volatile("lwbrx %0,0x0,%1": "=r" (e): "r" (a));
+  asm volatile("isync");
+  return e;
+}
+#endif
+
 /*
 *  bsp_start
 *
@@ -181,7 +243,6 @@ void save_boot_params(RESIDUAL* r3, void *r4, void* r5, char *additional_boot_op

 void bsp_start( void )
 {
-  int err;
  unsigned char *stack;
  unsigned l2cr;
  register unsigned char* intrStack;
@@ -191,17 +252,29 @@ void bsp_start( void )
  prep_t boardManufacturer;
  motorolaBoard myBoard;
  Triv121PgTbl	pt=0;
+
+  select_console(CONSOLE_SERIAL);
  /*
-   * Get CPU identification dynamically. Note that the get_ppc_cpu_type() function
-   * store the result in global variables so that it can be used latter...
+   * Get CPU identification dynamically. Note that the get_ppc_cpu_type()
+   * function store the result in global variables so that it can be used 
+   * later...
   */
  myCpu 	= get_ppc_cpu_type();
  myCpuRevision = get_ppc_cpu_revision();
+
+#if defined(mvme2100)
+  EUMBBAR = get_eumbbar(); 
+
+  Cpu_table.exceptions_in_RAM 	 = TRUE;
+  { unsigned v = 0x3000 ; _CPU_MSR_SET(v); }
+#endif
+
  /*
   * enables L1 Cache. Note that the L1_caches_enables() codes checks for
   * relevant CPU type so that the reason why there is no use of myCpu...
   */
  L1_caches_enables();
+
  /*
   * Enable L2 Cache. Note that the set_L2CR(L2CR) codes checks for
   * relevant CPU type (mpc750)...
@@ -212,24 +285,27 @@ void bsp_start( void )
 #endif  
  if ( (! (l2cr & 0x80000000)) && ((int) l2cr == -1))
    set_L2CR(0xb9A14000);
+
  /*
-   * the initial stack  has aready been set to this value in start.S
+   * the initial stack has already been set to this value in start.S
   * so there is no need to set it in r1 again... It is just for info
   * so that It can be printed without accessing R1.
   */
-  stack = ((unsigned char*) __rtems_end) + INIT_STACK_SIZE - CPU_MINIMUM_STACK_FRAME_SIZE;
+  stack = ((unsigned char*) __rtems_end) +
+               INIT_STACK_SIZE - CPU_MINIMUM_STACK_FRAME_SIZE;

- /* tag the bottom (T. Straumann 6/36/2001 <strauman@slac.stanford.edu>) */
+  /* tag the bottom (T. Straumann 6/36/2001 <strauman@slac.stanford.edu>) */
  *((unsigned32 *)stack) = 0;

  /*
   * Initialize the interrupt related settings
   * SPRG1 = software managed IRQ stack
   *
-   * This could be done latter (e.g in IRQ_INIT) but it helps to understand
+   * This could be done later (e.g in IRQ_INIT) but it helps to understand
   * some settings below...
   */
-  intrStack = ((unsigned char*) __rtems_end) + INIT_STACK_SIZE + INTR_STACK_SIZE - CPU_MINIMUM_STACK_FRAME_SIZE;
+  intrStack = ((unsigned char*) __rtems_end) +
+    INIT_STACK_SIZE + INTR_STACK_SIZE - CPU_MINIMUM_STACK_FRAME_SIZE;

  /* make sure it's properly aligned */
  (unsigned32)intrStack &= ~(CPU_STACK_ALIGNMENT-1);
@@ -243,38 +319,47 @@ void bsp_start( void )
  _write_SPRG0(PPC_BSP_HAS_FIXED_PR288);

  /*
-   * Initialize default raw exception hanlders. See vectors/vectors_init.c
+   * Initialize default raw exception handlers. See vectors/vectors_init.c
   */
  initialize_exceptions();
+
  /*
-   * Init MMU block address translation to enable hardware
-   * access
+   * Init MMU block address translation to enable hardware access
   */
+#if !defined(mvme2100)
  /*
-   * PC legacy IO space used for inb/outb and all PC
-   * compatible hardware
+   * PC legacy IO space used for inb/outb and all PC compatible hardware
   */
-  setdbat(1, _IO_BASE, _IO_BASE, 0x10000000, IO_PAGE);
+   setdbat(1, _IO_BASE, _IO_BASE, 0x10000000, IO_PAGE);
+#endif
+
  /*
-   * PCI devices memory area. Needed to access OPENPIC features
-   * provided by the RAVEN
+   * PCI devices memory area. Needed to access OpenPIC features
+   * provided by the Raven
+   *
+   * T. Straumann: give more PCI address space
   */
-  /* T. Straumann: give more PCI address space */
-  setdbat(2, PCI_MEM_BASE, PCI_MEM_BASE, 0x10000000, IO_PAGE);
+   setdbat(2, PCI_MEM_BASE, PCI_MEM_BASE, 0x10000000, IO_PAGE);
+
  /*
-   * Must have acces to open pic PCI ACK registers 
-   * provided by the RAVEN
-   * 
+   * Must have access to OpenPIC PCI ACK registers provided by the Raven
   */
  setdbat(3, 0xf0000000, 0xf0000000, 0x10000000, IO_PAGE);

  select_console(CONSOLE_LOG);

-  /* We check that the keyboard is present and immediately 
+  /*
+   * We check that the keyboard is present and immediately 
   * select the serial console if not.
   */
-  err = kbdreset();
-  if (err) select_console(CONSOLE_SERIAL);
+#if defined(BSP_KBD_IOBASE)
+  { int err;
+    err = kbdreset();
+    if (err) select_console(CONSOLE_SERIAL);
+  }
+#else
+  select_console(CONSOLE_SERIAL);
+#endif

  boardManufacturer   =  checkPrepBoardType(&residualCopy);
  if (boardManufacturer != PREP_Motorola) {
@@ -284,7 +369,8 @@ void bsp_start( void )
  myBoard = getMotorolaBoard();
  
  printk("-----------------------------------------\n");
-  printk("Welcome to %s on %s\n", _RTEMS_version, motorolaBoardToString(myBoard));
+  printk("Welcome to %s on %s\n", _RTEMS_version,
+                                    motorolaBoardToString(myBoard));
  printk("-----------------------------------------\n");
 #ifdef SHOW_MORE_INIT_SETTINGS  
  printk("Residuals are located at %x\n", (unsigned) &residualCopy);
@@ -308,18 +394,17 @@ void bsp_start( void )
 #endif  
  InitializePCI();

- {
-    struct _int_map     *bspmap   = motorolaIntMap(currentBoard);
-    if( bspmap )
-    {
-       printk("pci : Configuring interrupt routing for '%s'\n", motorolaBoardToString(currentBoard));
+  {
+    const struct _int_map *bspmap = motorolaIntMap(currentBoard);
+    if( bspmap ) {
+       printk("pci : Configuring interrupt routing for '%s'\n",
+          motorolaBoardToString(currentBoard));
       FixupPCI(bspmap, motorolaIntSwizzle(currentBoard) );
    }
    else
       printk("pci : Interrupt routing not available for this bsp\n");
 }

-
 #ifdef SHOW_MORE_INIT_SETTINGS
  printk("Number of PCI buses found is : %d\n", BusCountPCI());
 #endif
@@ -330,25 +415,31 @@ void bsp_start( void )
   */
  __asm__ __volatile ("sc");
  /*
-   * Check we can still catch exceptions and returned coorectly.
+   * Check we can still catch exceptions and return correctly.
   */
  printk("Testing exception handling Part 2\n");
  __asm__ __volatile ("sc");
+
+  /*
+   *  Somehow doing the above seems to clobber SPRG0 on the mvme2100.  It
+   *  is probably a not so subtle hint that you do not want to use PPCBug
+   *  once RTEMS is up and running.  Anyway, we still needs to indicate
+   *  that we have fixed PR288.  Eventually, this should go away.
+   */
+  _write_SPRG0(PPC_BSP_HAS_FIXED_PR288);
 #endif  

-
-  BSP_mem_size 				= residualCopy.TotalMemory;
-  BSP_bus_frequency			= residualCopy.VitalProductData.ProcessorBusHz;
-  BSP_processor_frequency		= residualCopy.VitalProductData.ProcessorHz;
-  BSP_time_base_divisor			= (residualCopy.VitalProductData.TimeBaseDivisor?
-					   residualCopy.VitalProductData.TimeBaseDivisor : 4000);
+  BSP_mem_size            = residualCopy.TotalMemory;
+  BSP_bus_frequency       = residualCopy.VitalProductData.ProcessorBusHz;
+  BSP_processor_frequency = residualCopy.VitalProductData.ProcessorHz;
+  BSP_time_base_divisor   = (residualCopy.VitalProductData.TimeBaseDivisor?
+                    residualCopy.VitalProductData.TimeBaseDivisor : 4000);

  /* clear hostbridge errors but leave MCP disabled -
   * PCI config space scanning code will trip otherwise :-(
   */
  _BSP_clear_hostbridge_errors(0 /* enableMCP */, 0/*quiet*/);

-
  /* Allocate and set up the page table mappings
   * This is only available on >604 CPUs.
   *
@@ -358,18 +449,13 @@ void bsp_start( void )
   */
  pt = BSP_pgtbl_setup(&BSP_mem_size);

-  if (!pt ||
-	  TRIV121_MAP_SUCCESS != triv121PgTblMap(
-			  							pt,
-										TRIV121_121_VSID,
-										0xfeff0000,
-										1,
-										TRIV121_ATTR_IO_PAGE,
-										TRIV121_PP_RW_PAGE
-										)) {
-	printk("WARNING: unable to setup page tables VME bridge must share PCI space\n");
+  if (!pt || TRIV121_MAP_SUCCESS != triv121PgTblMap(
+            pt, TRIV121_121_VSID, 0xfeff0000, 1,
+            TRIV121_ATTR_IO_PAGE, TRIV121_PP_RW_PAGE)) {
+	printk("WARNING: unable to setup page tables VME "
+               "bridge must share PCI space\n");
  }
-  
+
  /*
   * Set up our hooks
   * Make sure libc_init is done before drivers initialized so that
@@ -384,12 +470,14 @@ void bsp_start( void )
  Cpu_table.exceptions_in_RAM 	 = TRUE;

 #ifdef SHOW_MORE_INIT_SETTINGS
-  printk("BSP_Configuration.work_space_size = %x\n", BSP_Configuration.work_space_size);
+  printk("BSP_Configuration.work_space_size = %x\n",
+          BSP_Configuration.work_space_size);
 #endif  
  work_space_start = 
    (unsigned char *)BSP_mem_size - BSP_Configuration.work_space_size;

-  if ( work_space_start <= ((unsigned char *)__rtems_end) + INIT_STACK_SIZE + INTR_STACK_SIZE) {
+  if ( work_space_start <=
+       ((unsigned char *)__rtems_end) + INIT_STACK_SIZE + INTR_STACK_SIZE) {
    printk( "bspstart: Not enough RAM!!!\n" );
    bsp_cleanup();
  }
@@ -401,7 +489,6 @@ void bsp_start( void )
   */
  BSP_rtems_irq_mng_init(0);

-  
  /* Activate the page table mappings only after
   * initializing interrupts because the irq_mng_init()
   * routine needs to modify the text
@@ -411,23 +498,27 @@ void bsp_start( void )
    printk("Page table setup finished; will activate it NOW...\n");
 #endif
    BSP_pgtbl_activate(pt);
-  	/* finally, switch off DBAT3 */
-	setdbat(3, 0, 0, 0, 0); 
+    /* finally, switch off DBAT3 */
+    setdbat(3, 0, 0, 0, 0); 
  }

  /*
-   * Initialize VME bridge - needs working PCI
-   * and IRQ subsystems...
+   * Initialize VME bridge - needs working PCI and IRQ subsystems...
   */
 #ifdef SHOW_MORE_INIT_SETTINGS
  printk("Going to initialize VME bridge\n");
 #endif
-  /* VME initialization is in a separate file so apps which don't use
-   * VME or want a different configuration may link against a customized
-   * routine.
+  /*
+   * VME initialization is in a separate file so apps which don't use VME or
+   * want a different configuration may link against a customized routine.
   */
  BSP_vme_config();

+
+#if defined(DEBUG_BATS)
+  ShowBATS();
+#endif
+
 #ifdef SHOW_MORE_INIT_SETTINGS
  printk("Exit from bspstart\n");
 #endif  
--- a/c/src/lib/libbsp/powerpc/shared/tod/.cvsignore
+++ b/c/src/lib/libbsp/powerpc/shared/tod/.cvsignore
@@ -0,0 +1,2 @@
+Makefile
+Makefile.in
--- a/c/src/lib/libbsp/powerpc/shared/tod/Makefile.am
+++ b/c/src/lib/libbsp/powerpc/shared/tod/Makefile.am
@@ -0,0 +1,12 @@
+##
+## $Id$
+##
+
+
+C_FILES = todcfg.c
+
+all-local: 
+
+EXTRA_DIST = todcfg.c
+
+include $(top_srcdir)/../../../../../automake/local.am
--- a/c/src/lib/libbsp/powerpc/shared/tod/todcfg.c
+++ b/c/src/lib/libbsp/powerpc/shared/tod/todcfg.c
@@ -0,0 +1,69 @@
+/*
+ * This file contains the RTC driver table for Motorola shared BSPs.
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ *
+ * $Id$
+ */
+
+#include <bsp.h>
+#include <libchip/rtc.h>
+#include <libchip/m48t08.h>
+
+/* Forward function declaration */
+#if !defined(mvme2100)
+unsigned32 mvmertc_get_register( unsigned32, unsigned8 );
+void mvmertc_set_register( unsigned32, unsigned8, unsigned32 );
+#endif
+
+/* The following table configures the RTC drivers used in this BSP */
+rtc_tbl RTC_Table[] = {
+    {
+        "/dev/rtc",                /* sDeviceName */
+        RTC_M48T08,                /* deviceType  -- actually M48T59 */
+        &m48t08_fns,               /* pDeviceFns */
+        rtc_probe,                 /* deviceProbe */
+        NULL,                      /* pDeviceParams */
+#if defined(mvme2100)
+        0xFFE81ff8,                /* ulCtrlPort1 */
+        0x00,                      /* ulDataPort */
+        m48t08_get_register,       /* getRegister */
+        m48t08_set_register        /* setRegister */
+#else
+        0xFFE81ff8,                /* ulCtrlPort1 */
+        0x00,                      /* ulDataPort */
+        mvmertc_get_register,      /* getRegister */
+        mvmertc_set_register       /* setRegister */
+#endif
+    }
+};
+
+/* Some information used by the RTC driver */
+
+#define NUM_RTCS (sizeof(RTC_Table)/sizeof(rtc_tbl))
+
+unsigned long RTC_Count = NUM_RTCS;
+
+rtems_device_minor_number RTC_Minor;
+
+#if !defined(mvme2100)
+#include <rtems/bspIo.h>
+void mvmertc_set_register(
+  unsigned32 base,
+  unsigned8  reg,
+  unsigned32 value
+)
+{
+  printk( "RTC SUPPORT NOT IMPLEMENTED ON THIS BOARD\n");
+}
+
+unsigned32 mvmertc_get_register(
+  unsigned32 base,
+  unsigned8  reg
+)
+{
+  printk( "RTC SUPPORT NOT IMPLEMENTED ON THIS BOARD\n");
+}
+#endif
--- a/c/src/lib/libbsp/powerpc/shared/vectors/vectors_init.c
+++ b/c/src/lib/libbsp/powerpc/shared/vectors/vectors_init.c
@@ -175,7 +175,9 @@ void initialize_exceptions()
  if (!mpc60x_init_exceptions(&exception_config)) {
    BSP_panic("Exception handling initialization failed\n");
  }
+#ifdef RTEMS_DEBUG
  else {
    printk("Exception handling initialization done\n");
  }
+#endif
 }
--- a/c/src/lib/libbsp/powerpc/shared/vme/VMEConfig.h
+++ b/c/src/lib/libbsp/powerpc/shared/vme/VMEConfig.h
@@ -11,10 +11,15 @@
 * hardcoded window lengths that match this
 * layout:
 */
-#define _VME_A32_WIN0_ON_PCI	0x10000000
-#define _VME_A24_ON_PCI			0x1f000000
-#define _VME_A16_ON_PCI			0x1fff0000
-
+#if defined(mvme2100)
+  #define _VME_A32_WIN0_ON_PCI  0x80000000
+  #define _VME_A24_ON_PCI       0x8f000000
+  #define _VME_A16_ON_PCI       0x8fff0000
+#else
+  #define _VME_A32_WIN0_ON_PCI  0x10000000
+  #define _VME_A24_ON_PCI       0x1f000000
+  #define _VME_A16_ON_PCI       0x1fff0000
+#endif
 /* start of the A32 window on the VME bus
 * TODO: this should perhaps be a configuration option
 */
--- a/c/src/lib/libbsp/powerpc/shared/vme/vmeconfig.c
+++ b/c/src/lib/libbsp/powerpc/shared/vme/vmeconfig.c
@@ -34,23 +34,17 @@ union {
 	unsigned long	batbits;
 } dbat0u;

-  if (currentBoard < MVME_2300 || currentBoard >= MVME_1600) {
-		printk("VME bridge for this board is unknown - if it's a Tundra Universe, add the board to 'shared/vme/vmeconfig.c'\n");
-		printk("Skipping VME initialization...\n");
-		return;
-  }
-
  vmeUniverseInit();
  vmeUniverseReset();
-
  /* setup a PCI area to map the VME bus */

  dbat0u.batbits = _read_DBAT0U();

  /* if we have page tables, BAT0 is available */
  if (dbat0u.bat.vs || dbat0u.bat.vp) {
-	printk("WARNING: BAT0 is taken (no pagetables?); VME bridge must share PCI range for VME access\n");
-	printk("Skipping VME initialization...\n");
+	printk("WARNING: BAT0 is taken (no pagetables?); "
+               "VME bridge must share PCI range for VME access\n"
+	       "Skipping VME initialization...\n");
 	return;
  }

@@ -99,7 +93,7 @@ union {
  vmeUniverseMasterPortsShow(0);
  vmeUniverseSlavePortsShow(0);

-  /* install the VME insterrupt manager */
+  /* install the VME interrupt manager */
  vmeUniverseInstallIrqMgr(0,5,1,6);
  if (vmeUniverse0PciIrqLine<0)
 	BSP_panic("Unable to get interrupt line info from PCI config");
--- a/c/src/lib/libbsp/powerpc/support/old_exception_processing/ChangeLog
+++ b/c/src/lib/libbsp/powerpc/support/old_exception_processing/ChangeLog
@@ -1,3 +1,8 @@
+2004-10-20	Ralf Corsepius <ralf_corsepius@rtems.org>
+
+	PR 696/bsps
+	* cpu.c: Include bsp.h.
+
 2003-09-04	Joel Sherrill <joel@OARcorp.com>

 	* cpu.c, cpu_asm.S: URL for license changed.
--- a/c/src/lib/libbsp/powerpc/support/old_exception_processing/cpu.c
+++ b/c/src/lib/libbsp/powerpc/support/old_exception_processing/cpu.c
@@ -28,6 +28,7 @@
 *  $Id$
 */

+#include <bsp.h>
 #include <rtems/system.h>
 #include <rtems/score/isr.h>
 #include <rtems/score/context.h>
--- a/c/src/lib/libbsp/shared/ChangeLog
+++ b/c/src/lib/libbsp/shared/ChangeLog
@@ -1,3 +1,26 @@
+2005-08-19	Cedric Aubert <cedric_aubert@yahoo.fr>
+
+	PR 577/bsps
+	* console.c: The console_close() method currently calls StopRemoteTx()
+	on all invocations. It should should be ok for last close only but
+	not for any others. If you open a port multiple times, you only want
+	to call StopRemoteTx() only as part of the last close.
+
+2004-12-10	Ralf Corsepius <ralf.corsepius@rtems.org>
+
+	PR 704/bsps.
+	* ide_ctrl.c: Removed (obsolete).
+
+2004-11-16	Richard Campbell <richard.campbell@OARcorp.com>
+
+	* vmeUniverse/vmeUniverse.c: Use PCI_MEM_BASE_ADJUSTMENT because some
+	boards -- notably the MVME2100 -- return the physical address, not an
+	offset in PCI memory space.
+
+2004-11-10	Joel Sherrill <joel@oarcorp.com>
+
+	* tod.c: Add include of tod.h to remove warnings.
+
 2004-10-13	Eric Norum <norume@aps.anl.gov>

 	PR 688/bsps
--- a/c/src/lib/libbsp/shared/console.c
+++ b/c/src/lib/libbsp/shared/console.c
@@ -128,10 +128,15 @@ rtems_device_driver console_close(
 {
  rtems_libio_open_close_args_t *args = arg;

-  if ( (args->iop->flags&LIBIO_FLAGS_READ) &&
-        Console_Port_Tbl[minor].pDeviceFlow &&
-        Console_Port_Tbl[minor].pDeviceFlow->deviceStopRemoteTx) {
-    Console_Port_Tbl[minor].pDeviceFlow->deviceStopRemoteTx(minor);
+  /* Get the tty refcount to determine if we need to do deviceStopRemoteTx.
+   * Stop only if it's the last one opened.
+   */
+  if ( (current_tty->refcount == 1) ) {
+    if ( (args->iop->flags&LIBIO_FLAGS_READ) &&
+          Console_Port_Tbl[minor].pDeviceFlow &&
+          Console_Port_Tbl[minor].pDeviceFlow->deviceStopRemoteTx) {
+      Console_Port_Tbl[minor].pDeviceFlow->deviceStopRemoteTx(minor);
+    }
  }

  return rtems_termios_close (arg);
--- a/c/src/lib/libbsp/shared/ide_ctrl.c
+++ b/c/src/lib/libbsp/shared/ide_ctrl.c
@@ -1,179 +0,0 @@
-/*
- * ide_controller.c
- * 
- * This is generic rtems driver for IDE controllers.
- *
- * Copyright (C) 2001 OKTET Ltd., St.-Petersburg, Russia
- * Authors: Alexandra Kossovsky <sasha@oktet.ru>
- *          Eugeny S. Mints <Eugeny.Mints@oktet.ru>
- *
- *  The license and distribution terms for this file may be
- *  found in the file LICENSE in this distribution or at
- *  http://www.rtems.com/license/LICENSE.
- * 
- * $Id$
- *
- */
-#include <chain.h>
-#include <assert.h>
-#include <rtems/blkdev.h>
-
-#include <libchip/ide_ctrl_cfg.h>
-#include <libchip/ide_ctrl_io.h>
-
-/*
- * ide_controller_initialize --
- *     Initializes all configured IDE controllers. Controllers configuration 
- *     table is provided by BSP
- *
- * PARAMETERS:
- *     major     - device major number
- *     minor_arg - device minor number
- *     args      - arguments
- *
- * RETURNS:
- *     RTEMS_SUCCESSFUL on success, or error code if
- *     error occured
- */
-rtems_device_driver 
-ide_controller_initialize(rtems_device_major_number  major,
-                          rtems_device_minor_number  minor_arg,
-                          void                      *args)
-{
-    unsigned long       minor;
-    rtems_status_code   status;
-
-    /* FIXME: may be it should be done on compilation phase */
-    if (IDE_Controller_Count > IDE_CTRL_MAX_MINOR_NUMBER)
-        rtems_fatal_error_occurred(RTEMS_TOO_MANY);
-        
-    for (minor=0; minor < IDE_Controller_Count; minor++)
-    {
-        IDE_Controller_Table[minor].status = IDE_CTRL_NON_INITIALIZED;
-        
-        if ((IDE_Controller_Table[minor].probe != NULL && 
-             IDE_Controller_Table[minor].probe(minor)) ||
-            IDE_Controller_Table[minor].fns->ctrl_probe(minor))
-        {
-            status = rtems_io_register_name(IDE_Controller_Table[minor].name, 
-                                            major, minor);
-            if (status != RTEMS_SUCCESSFUL) 
-                rtems_fatal_error_occurred(status);
-
-            IDE_Controller_Table[minor].fns->ctrl_initialize(minor);
-            
-            IDE_Controller_Table[minor].status = IDE_CTRL_INITIALIZED;
-        }
-    }
-    return RTEMS_SUCCESSFUL;
-}
-
-/*
- * ide_controller_read_data_block --
- *     Read data block via controller's data register
- *
- * PARAMETERS:
- *     minor      - minor number of controller
- *     block_size - number of bytes to read
- *     bufs       - set of buffers to store data
- *     cbuf       - number of current buffer from the set
- *     pos        - position inside current buffer 'cbuf'
- *
- * RETURNS:
- *     NONE
- */
-void
-ide_controller_read_data_block(rtems_device_minor_number  minor,
-                               unsigned16                 block_size,
-                               blkdev_sg_buffer          *bufs,
-                               rtems_unsigned32          *cbuf,
-                               rtems_unsigned32          *pos)
-{
-    IDE_Controller_Table[minor].fns->ctrl_read_block(minor, block_size, bufs,
-                                                     cbuf, pos);
-}
-
-/*
- * ide_controller_write_data_block --
- *     Write data block via controller's data register
- *
- * PARAMETERS:
- *     minor      - minor number of controller
- *     block_size - number of bytes to write
- *     bufs       - set of buffers which store data
- *     cbuf       - number of current buffer from the set
- *     pos        - position inside current buffer 'cbuf'
- *
- * RETURNS:
- *     NONE
- */
-void
-ide_controller_write_data_block(rtems_device_minor_number  minor,
-                                unsigned16                 block_size,
-                                blkdev_sg_buffer          *bufs,
-                                rtems_unsigned32          *cbuf,
-                                rtems_unsigned32          *pos)
-
-{
-    IDE_Controller_Table[minor].fns->ctrl_write_block(minor, block_size, bufs,
-                                                      cbuf, pos);
-}
-
-/*
- * ide_controller_read_register --
- *     Read controller's register
- *
- * PARAMETERS:
- *     minor - minor number of controller
- *     reg   - register to read
- *     value - placeholder for result
- *
- * RETURNS
- *     NONE
- */
-void
-ide_controller_read_register(rtems_device_minor_number  minor,
-                             int                        reg, 
-                             unsigned16                *value)
-{
-    IDE_Controller_Table[minor].fns->ctrl_reg_read(minor, reg, value);
-}
-
-/*
- * ide_controller_write_register --
- *     Write controller's register
- *
- * PARAMETERS:
- *     minor - minor number of controller
- *     reg   - register to write
- *     value - value to write
- *
- * RETURNS:
- *     NONE
- */
-void
-ide_controller_write_register(rtems_device_minor_number minor, int reg, 
-                              unsigned16 value)
-{
-    IDE_Controller_Table[minor].fns->ctrl_reg_write(minor, reg, value);
-}
-
-/*
- * ide_controller_config_io_speed --
- *     Set controller's speed of IO operations
- *
- * PARAMETERS:
- *     minor         - minor number of controller
- *     modes_avaible - speeds available
- *
- * RETURNS:
- *     RTEMS_SUCCESSFUL on success, or error code if
- *     error occured
- */
-rtems_status_code 
-ide_controller_config_io_speed(int minor, unsigned8 modes_avaible)
-{
-    return IDE_Controller_Table[minor].fns->ctrl_config_io_speed(
-               minor, 
-               modes_avaible);
-}
--- a/c/src/lib/libbsp/shared/tod.c
+++ b/c/src/lib/libbsp/shared/tod.c
@@ -10,6 +10,7 @@

 #include <rtems.h>
 #include <libchip/rtc.h>
+#include <tod.h>

 /*
 *  Configuration Information
--- a/c/src/lib/libbsp/shared/vmeUniverse/vmeUniverse.c
+++ b/c/src/lib/libbsp/shared/vmeUniverse/vmeUniverse.c
@@ -69,7 +69,8 @@
 #endif

 typedef unsigned int pci_ulong;
-#define PCI_TO_LOCAL_ADDR(memaddr) ((pci_ulong)(memaddr) + PCI_MEM_BASE)
+#define PCI_TO_LOCAL_ADDR(memaddr) \
+    ((pci_ulong)(memaddr) + PCI_MEM_BASE_ADJUSTMENT)


 #elif defined(__vxworks)
--- a/c/src/lib/libcpu/ChangeLog
+++ b/c/src/lib/libcpu/ChangeLog
@@ -1,3 +1,8 @@
+2004-11-23	Richard Campbell <richard.campbell@oarcorp.com>
+
+	* powerpc/mpc6xx/mmu/mmuAsm.S: Enable L1 instruction cache only for
+	mpc8240 and mpc8245.
+
 2003-09-04	Joel Sherrill <joel@OARcorp.com>

 	* shared/include/cache.h, shared/src/cache_aligned_malloc.c,
--- a/c/src/lib/libcpu/powerpc/ChangeLog
+++ b/c/src/lib/libcpu/powerpc/ChangeLog
@@ -1,3 +1,26 @@
+2005-08-12	Phil Torre <ptorre@zetron.com>
+
+	PR 816/bsps
+	* mpc8xx/include/mpc8xx.h: The struct which describes SCC Ethernet mode
+	parameters (m8xxSCCENparms_t) does not match the hardware: members
+	taddr_h and taddr_l are transposed. When loading new multicast group
+	addresses into the hash table, the wrong hash bit is set.
+
+2004-11-22	Jennifer Averett <jennifer@OARcorp.com>
+
+	PR 581/bsps
+	* mpc6xx/exceptions/raw_exception.c, shared/include/cpuIdent.h:
+	Converting PSIM to new exception model required addition of PSIM CPU
+	model.
+
+2004-11-10	Richard Campbell <richard.campbell@oarcorp.com>
+
+	* configure.ac, mpc6xx/exceptions/raw_exception.c,
+	mpc6xx/exceptions/raw_exception.h, mpc6xx/mmu/bat.c,
+	mpc6xx/mmu/bat.h, mpc6xx/mmu/mmuAsm.S, shared/include/cpuIdent.c,
+	shared/include/cpuIdent.h: Add MPC8240 and MPC8245 support. There was
+	also a significant amount of spelling and whitespace cleanup.
+
 2004-05-22	Till Strauman <strauman@slac.stanford.edu>

 	PR 619/bsps
--- a/c/src/lib/libcpu/powerpc/configure.ac
+++ b/c/src/lib/libcpu/powerpc/configure.ac
@@ -31,6 +31,8 @@ AM_CONDITIONAL(shared, test "$RTEMS_CPU_MODEL" = "mpc750" \
 || test "$RTEMS_CPU_MODEL" = "mpc6xx" \
 || test "$RTEMS_CPU_MODEL" = "mpc821" \
 || test "$RTEMS_CPU_MODEL" = "mpc860" \
+|| test "$RTEMS_CPU_MODEL" = "mpc8240" \
+|| test "$RTEMS_CPU_MODEL" = "mpc8245" \
 || test "$RTEMS_CPU_MODEL" = "mpc8260" \
 || test "$RTEMS_CPU_MODEL" = "mpc8xx" )

@@ -39,7 +41,9 @@ AM_CONDITIONAL(mpc505, test "$RTEMS_CPU_MODEL" = "mpc505")
 AM_CONDITIONAL(mpc6xx, test "$RTEMS_CPU_MODEL" = "mpc6xx" \
 || test "$RTEMS_CPU_MODEL" = "mpc604" \
 || test "$RTEMS_CPU_MODEL" = "mpc7400" \
-|| test "$RTEMS_CPU_MODEL" = "mpc750" )
+|| test "$RTEMS_CPU_MODEL" = "mpc750" \
+|| test "$RTEMS_CPU_MODEL" = "mpc8240" \
+|| test "$RTENS_CPU_MODEL" = "mpc8245" )
 AM_CONDITIONAL(mpc8xx, test "$RTEMS_CPU_MODEL" = "mpc8xx" \
 || test "$RTEMS_CPU_MODEL" = "mpc821" \
 || test "$RTEMS_CPU_MODEL" = "mpc860" )
--- a/c/src/lib/libcpu/powerpc/mpc6xx/exceptions/raw_exception.c
+++ b/c/src/lib/libcpu/powerpc/mpc6xx/exceptions/raw_exception.c
@@ -1,7 +1,7 @@
 /*
 * raw_exception.c  - This file contains implementation of C function to
- *          	      Instanciate 60x ppc primary exception entries.
- *	 	      More detailled information can be found on motorola
+ *          	      Instantiate 60x ppc primary exception entries.
+ *	 	      More detailed information can be found on motorola
 *	    	      site and more precisely in the following book :
 *
 *		      MPC750 
@@ -33,6 +33,17 @@ static rtems_raw_except_connect_data  		default_raw_except_entry;
 static rtems_raw_except_global_settings* 	local_settings;

 void * codemove(void *, const void *, unsigned int, unsigned long);
+
+void* mpc60x_get_vector_addr(rtems_vector vector)
+{
+  extern rtems_cpu_table Cpu_table;
+
+  if ( Cpu_table.exceptions_in_RAM )
+    return ((void*)  (((unsigned) vector) << 8));
+
+  return ((void*)  (((unsigned) vector) << 8) + 0xfff00000);
+}
+
 int mpc750_vector_is_valid(rtems_vector vector)

 {
@@ -56,6 +67,37 @@ int mpc750_vector_is_valid(rtems_vector vector)
  }
 }

+int PSIM_vector_is_valid(rtems_vector vector)
+{
+  switch(vector) {
+  case ASM_RESET_VECTOR: /* fall through */
+  case ASM_MACH_VECTOR:
+  case ASM_PROT_VECTOR:
+  case ASM_ISI_VECTOR:
+  case ASM_EXT_VECTOR:
+  case ASM_ALIGN_VECTOR:
+  case ASM_PROG_VECTOR:
+  case ASM_FLOAT_VECTOR:
+  case ASM_DEC_VECTOR:
+    return 1;
+  case ASM_SYS_VECTOR:
+    return 0;
+  case ASM_TRACE_VECTOR:
+    return 1;
+  case ASM_PERFMON_VECTOR:
+    return 0;
+  case ASM_IMISS_VECTOR: /* fall through */
+  case ASM_DLMISS_VECTOR:
+  case ASM_DSMISS_VECTOR:
+  case ASM_ADDR_VECTOR:
+  case ASM_SYSMGMT_VECTOR:
+    return 1;
+  case ASM_ITM_VECTOR:
+    return 0;
+  }
+  return 0;
+}
+
 int mpc603_vector_is_valid(rtems_vector vector)
 {
  switch(vector) {
@@ -133,13 +175,23 @@ int mpc60x_vector_is_valid(rtems_vector vector)
        case PPC_603:
        case PPC_603e:
        case PPC_603ev:
+        case PPC_8260:
+        /* case PPC_8240: -- same value as 8260 */
+        case PPC_8245:
            if (!mpc603_vector_is_valid(vector)) {
                return 0;
            }
            break;
-        default:
-            printk("Please complete libcpu/powerpc/mpc6xx/exceptions/raw_exception.c\n");
-            printk("current_ppc_cpu = %x\n", current_ppc_cpu);
+        case PPC_PSIM:
+            if (!PSIM_vector_is_valid(vector)) {
+                return 0;
+            }
+            break;
+
+         default:
+            printk("Please complete "
+                   "libcpu/powerpc/mpc6xx/exceptions/raw_exception.c\n"
+                   "current_ppc_cpu = %x\n", current_ppc_cpu);
            return 0;
     }
     return 1;
@@ -150,6 +202,8 @@ int mpc60x_set_exception  (const rtems_raw_except_connect_data* except)
    unsigned int level;

    if (!mpc60x_vector_is_valid(except->exceptIndex)) {
+      printk("mpc60x_set_exception: vector %d is not valid\n",
+              except->exceptIndex);
      return 0;
    }
    /*
@@ -159,7 +213,11 @@ int mpc60x_set_exception  (const rtems_raw_except_connect_data* except)
     * RATIONALE : to always have the same transition by forcing the user
     * to get the previous handler before accepting to disconnect.
     */
-    if (memcmp(mpc60x_get_vector_addr(except->exceptIndex), (void*)default_raw_except_entry.hdl.raw_hdl,default_raw_except_entry.hdl.raw_hdl_size)) {
+
+    if (memcmp(mpc60x_get_vector_addr(except->exceptIndex),
+               (void*)default_raw_except_entry.hdl.raw_hdl,
+               default_raw_except_entry.hdl.raw_hdl_size)) {
+      printk("mpc60x_set_exception: raw vector not installed\n");
      return 0;
    }

--- a/c/src/lib/libcpu/powerpc/mpc6xx/exceptions/raw_exception.h
+++ b/c/src/lib/libcpu/powerpc/mpc6xx/exceptions/raw_exception.h
@@ -2,8 +2,8 @@
 * raw_execption.h
 *
 *	    This file contains implementation of C function to
- *          Instanciate 60x ppc primary exception entries.
- *	    More detailled information can be found on motorola
+ *          Instantiate 60x ppc primary exception entries.
+ *	    More detailed information can be found on motorola
 *	    site and more precisely in the following book :
 *
 *		MPC750 
@@ -159,10 +159,6 @@ extern int mpc60x_delete_exception (const rtems_raw_except_connect_data*);
 */
 extern int mpc750_vector_is_valid(rtems_vector vector);

-inline static  void* mpc60x_get_vector_addr(rtems_vector vector)
-{
-  return ((void*)  (((unsigned) vector) << 8));
-}
 /*
 * Exception global init.
 */
--- a/c/src/lib/libcpu/powerpc/mpc6xx/mmu/bat.c
+++ b/c/src/lib/libcpu/powerpc/mpc6xx/mmu/bat.c
@@ -2,8 +2,8 @@
 * bat.c
 *
 *	    This file contains the implementation of C function to
- *          Instanciate 60x/7xx ppc Block Address Translation (BAT) registers.
- *	    More detailled information can be found on motorola
+ *          Instantiate 60x/7xx ppc Block Address Translation (BAT) registers.
+ *	    More detailed information can be found on motorola
 *	    site and more precisely in the following book :
 *
 *		MPC750 
--- a/c/src/lib/libcpu/powerpc/mpc6xx/mmu/bat.h
+++ b/c/src/lib/libcpu/powerpc/mpc6xx/mmu/bat.h
@@ -2,8 +2,8 @@
 * bat.h
 *
 *	    This file contains declaration of C function to
- *          Instanciate 60x/7xx ppc Block Address Translation (BAT) registers.
- *	    More detailled information can be found on motorola
+ *          Instantiate 60x/7xx ppc Block Address Translation (BAT) registers.
+ *	    More detailed information can be found on motorola
 *	    site and more precisely in the following book :
 *
 *		MPC750 
--- a/c/src/lib/libcpu/powerpc/mpc6xx/mmu/mmuAsm.S
+++ b/c/src/lib/libcpu/powerpc/mpc6xx/mmu/mmuAsm.S
@@ -18,6 +18,7 @@
 #include <asm.h>
 #include <rtems/score/cpu.h>
 #include <libcpu/io.h>
+#include <bspopts.h>

 /* Unfortunately, the CPU types defined in cpu.h are
 * an 'enum' type and hence not available :-(
@@ -35,6 +36,7 @@
 #define PPC_860   0x50
 #define PPC_821   PPC_860
 #define PPC_8260  0x81
+#define PPC_8240  PPC_8260 

 /* ALTIVEC instructions (not recognized by off-the shelf gcc yet) */
 #define DSSALL	.long	0x7e00066c		/* DSSALL altivec instruction opcode */
@@ -136,7 +138,18 @@ L1_caches_enables:
 	beq	4f			/* not needed for 601 */
 	mfspr	r11,HID0
 	andi.	r0,r11,HID0_DCE
-	ori	r11,r11,HID0_ICE|HID0_DCE
+#if defined(mpc8240) || defined(mpc8245)
+        /*
+         * Data cache is broken for mpc8240 and mpc8245,
+         * enable instruction cache only.
+         */
+	ori	r11,r11,HID0_ICE
+#else
+        /*
+         * Enable both instruction and data caches 
+         */
+ 	ori	r11,r11,HID0_ICE|HID0_DCE
+#endif
 	ori	r8,r11,HID0_ICFI
 	bne	3f			/* don't invalidate the D-cache */
 	ori	r8,r8,HID0_DCI		/* unless it wasn't enabled */
--- a/c/src/lib/libcpu/powerpc/mpc8xx/include/mpc8xx.h
+++ b/c/src/lib/libcpu/powerpc/mpc8xx/include/mpc8xx.h
@@ -506,9 +506,9 @@ typedef struct m8xxSCCENparms_ {
      rtems_unsigned16        iaddr3;
      rtems_unsigned16        iaddr4;
      rtems_unsigned16        _boff_cnt;
-      rtems_unsigned16        taddr_l;
-      rtems_unsigned16        taddr_m;
      rtems_unsigned16        taddr_h;
+      rtems_unsigned16        taddr_m;
+      rtems_unsigned16        taddr_l;
    } ethernet;
  } un;
 } m8xxSCCENparms_t;
--- a/c/src/lib/libcpu/powerpc/shared/include/cpuIdent.c
+++ b/c/src/lib/libcpu/powerpc/shared/include/cpuIdent.c
@@ -40,8 +40,10 @@ char *get_ppc_cpu_type_name(ppc_cpu_id_t cpu)
    case PPC_620:		return "MPC620";
    case PPC_860:		return "MPC860";
    case PPC_8260:		return "MPC8260";
+    case PPC_8245:              return "MPC8245";
    default:
-      printk("Unknown CPU value of 0x%x. Please add it to <libcpu/powerpc/shared/include/cpuIdent.c>\n", cpu );
+      printk("Unknown CPU value of 0x%x. Please add it to "
+             "<libcpu/powerpc/shared/include/cpuIdent.c>\n", cpu );
  }
  return "UNKNOWN";
 }
@@ -62,9 +64,11 @@ ppc_cpu_id_t get_ppc_cpu_type()
    case PPC_620:
    case PPC_860:
    case PPC_8260:
+    case PPC_8245:
      return current_ppc_cpu;
    default:
-      printk("Unknown PVR value of 0x%x. Please add it to <libcpu/powerpc/shared/include/cpuIdent.c>\n", pvr );
+      printk("Unknown PVR value of 0x%x. Please add it to "
+             "<libcpu/powerpc/shared/include/cpuIdent.c>\n", pvr );
    return PPC_UNKNOWN;
  }
 }
--- a/c/src/lib/libcpu/powerpc/shared/include/cpuIdent.h
+++ b/c/src/lib/libcpu/powerpc/shared/include/cpuIdent.h
@@ -32,7 +32,10 @@ typedef enum
  PPC_860 = 0x50,
  PPC_821 = PPC_860,
  PPC_8260 = 0x81,
-  PPC_UNKNOWN = 0xff
+  PPC_8240 = PPC_8260,
+  PPC_8245 = 0x8081,
+  PPC_PSIM = 0xfffe,  /* GDB PowerPC simulator -- fake version */
+  PPC_UNKNOWN = 0xffff
 } ppc_cpu_id_t;

 typedef unsigned short ppc_cpu_revision_t;
--- a/c/src/libchip/ChangeLog
+++ b/c/src/libchip/ChangeLog
@@ -1,3 +1,24 @@
+2005-04-28      Jennifer Averett <jennifer.averett@oarcorp.com>
+
+        PR 781/misc
+        * serial/ns16550_p.h: Fix baud rate calculation
+
+2004-11-22	Joel Sherrill <joel@OARcorp.com>
+
+	PR 693/misc
+	* rtc/mc146818a_ioreg.c: Disable unless on a target with in/outport
+	routines.
+
+2004-11-10	Richard Campbell <richard.campbell@oarcorp.com>
+
+	* network/dec21140.c: Cleanup a bit and remove message about not
+	supported on PowerPC since it works on the MVME2100 BSP.
+
+2004-11-10	Joel Sherrill <joel@oarcorp.com>
+
+	PR 715/bsps
+	* rtc/mc146818a.c: Delete include of bsp.h
+
 2004-10-13      Eric Norum <norume@aps.anl.gov>

        PR 688/bsps
--- a/c/src/libchip/network/dec21140.c
+++ b/c/src/libchip/network/dec21140.c
@@ -627,6 +627,9 @@ dec21140Enet_initialize_hardware (struct dec21140_softc *sc)
   sc->irqInfo.off  = no_op;
   sc->irqInfo.isOn = dec21140IsOn;

+#ifdef DEC_DEBUG
+   printk( "dec2114x: Installing IRQ %d\n", sc->irqInfo.name );
+#endif
 #ifdef BSP_SHARED_HANDLER_SUPPORT
   st = BSP_install_rtems_shared_irq_handler( &sc->irqInfo );
 #else
@@ -1026,7 +1029,7 @@ rtems_dec21140_driver_attach (struct rtems_bsdnet_ifconfig *config, int attach)
    * Get the instance number for the board we're going to configure
    * from the user.
    */
-   if( (unitNumber = rtems_bsdnet_parse_driver_name( config, &unitName)) == -1 )
+   if( (unitNumber = rtems_bsdnet_parse_driver_name(config, &unitName)) == -1 )
   {
      return 0;
   }
@@ -1077,9 +1080,6 @@ rtems_dec21140_driver_attach (struct rtems_bsdnet_ifconfig *config, int attach)
      if( BSP_pciFindDevice( PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21143,
                             unitNumber-1, &pbus, &pdev, &pfun) != -1 )
      {
-         printk("dec21143 : found device '%s', PPC support has not been tested.  Using it anyway.\n", 
-                config->name );
-
         pci_write_config_dword(pbus,
                                pdev,
                                pfun,
@@ -1154,7 +1154,7 @@ rtems_dec21140_driver_attach (struct rtems_bsdnet_ifconfig *config, int attach)
                            PTE_CACHE_DISABLE | PTE_WRITABLE);
   else
      sc->base = (unsigned int *)(value & ~MEM_MASK);
-	
+
   pcib_conf_read8(signature, 60, &interrupt);
   cvalue = interrupt;
 #endif
@@ -1173,7 +1173,8 @@ rtems_dec21140_driver_attach (struct rtems_bsdnet_ifconfig *config, int attach)
                               PCI_BASE_ADDRESS_1,
                               &lvalue);

-   tmp = (unsigned int)(lvalue & (unsigned int)(~MEM_MASK)) + (unsigned int)PCI_MEM_BASE;
+   tmp = (unsigned int)(lvalue & (unsigned int)(~MEM_MASK))
+      + (unsigned int)PCI_MEM_BASE_ADJUSTMENT;

   sc->base = (unsigned int *)(tmp);

@@ -1209,7 +1210,9 @@ rtems_dec21140_driver_attach (struct rtems_bsdnet_ifconfig *config, int attach)
   sc->irqInfo.name = cvalue;


-   /* printk("dec2114x : unit %d base address %08x.\n", unitNumber, sc->base ); */
+#ifdef DEC_DEBUG
+   printk("dec2114x : unit %d base address %08x.\n", unitNumber, sc->base );
+#endif


   /*
--- a/c/src/libchip/rtc/mc146818a.c
+++ b/c/src/libchip/rtc/mc146818a.c
@@ -22,10 +22,10 @@
 *
 *  $Id$
 */
+
 #include <rtems.h>
 #include <libchip/rtc.h>
 #include <libchip/mc146818a.h>
-#include <bsp.h>

 #define From_BCD( _x ) ((((_x) >> 4) * 10) + ((_x) & 0x0F))
 #define To_BCD( _x )   ((((_x) / 10) << 4) + ((_x) % 10))
--- a/c/src/libchip/rtc/mc146818a_ioreg.c
+++ b/c/src/libchip/rtc/mc146818a_ioreg.c
@@ -19,6 +19,11 @@
 #include <rtems.h>
 #include <bsp.h>

+/*
+ *  At this point, not all CPUs or BSPs have defined in/out port routines.
+ */
+#if defined(__i386__) || defined(__PPC__)
+#if defined(inport_byte)
 unsigned32 mc146818a_get_register(
  unsigned32  ulCtrlPort,
  unsigned8   ucRegNum
@@ -43,3 +48,5 @@ void  mc146818a_set_register(
  outport_byte( ulCtrlPort, ucRegNum );
  outport_byte( ulCtrlPort+1, (unsigned8)ucData );
 }
+#endif
+#endif
--- a/Show More
+++ b/Show More
Author	SHA1	Message	Date
Joel Sherrill	d7bf841a96	2005-09-01 Joel Sherrill <joel@OARcorp.com> * VERSION: Updated to rtems-4.6.4.	2005-09-01 17:18:50 +00:00
Joel Sherrill	58cfecc76a	2005-09-01 Joel Sherrill <joel@OARcorp.com> * aclocal/version.m4: Updated to rtems-4.6.4.	2005-09-01 17:18:49 +00:00
Joel Sherrill	0bb4dd0337	2005-09-01 Joel Sherrill <joel@OARcorp.com> PR 820/rtems * inline/rtems/score/coremsg.inl, macros/rtems/score/coremsg.inl, src/coremsginsert.c: Increment of pending message count should be atomic with insertion on the pending message chain. Determination of the need to call the notification handler should also be in this atomic section of code.	2005-09-01 16:31:22 +00:00
Joel Sherrill	feedcdc65f	2005-09-01 Joel Sherrill <joel@OARcorp.com> PR 628/rtems * psx04/init.c, psx04/psx04.scn: Update tests to reflect a signal of 0 being an error.	2005-09-01 16:14:17 +00:00
Joel Sherrill	3c838f1ac8	2005-09-01 Joel Sherrill <joel@OARcorp.com> PR 796/rtems * src/semtimedwait.c: sem_timedwait is supposed to use absolute time for timeout specification. This patch is a modified version of the one suggested by Peter Dufault.	2005-09-01 14:46:02 +00:00
Joel Sherrill	45a32542db	2005-09-01 Joel Sherrill <joel@OARcorp.com> PR 350/make_build * compilers/gcc-target-default.cfg: Honor LD_PATHS set by user.	2005-09-01 13:39:14 +00:00
Joel Sherrill	f54bc05285	2005-09-01 Nuno Costa <nuno-costa@iol.pt> PR 804 * include/confdefs.h: Memory for POSIX timers not accounted for. Patch adapted from edit comment in PR filed.	2005-09-01 13:27:02 +00:00
Joel Sherrill	fd06f6c0d4	2005-09-01 Joel Sherrill <joel@OARcorp.com> * include/bsp.h: This file is only to be used by BSPs with the new interrupt API so checking for USE_ENHANCED_INTR_API is not needed.	2005-09-01 13:22:18 +00:00
Joel Sherrill	cc2efb6012	2005-09-01 Joel Sherrill <joel@OARcorp.com> * clock/Makefile.am, include/Makefile.am: Install tod.h	2005-09-01 13:20:47 +00:00
Ralf Corsepius	82973a283f	2005-08-31 Ralf Corsepius <ralf.corsepius@rtems.org> PR 819/filesystem * src/ttyname_r.c: Remove. * src/ttyname.c: Partial update from FreeBSD. * Makefile.am: Reflect changes above.	2005-08-31 04:34:58 +00:00
Joel Sherrill	4a4c78d97f	2005-08-19 Cedric Aubert <cedric_aubert@yahoo.fr> PR 577/bsps * console.c: The console_close() method currently calls StopRemoteTx() on all invocations. It should should be ok for last close only but not for any others. If you open a port multiple times, you only want to call StopRemoteTx() only as part of the last close.	2005-08-19 16:20:00 +00:00
Joel Sherrill	3d7d233c03	2005-08-18 Andrew Sinclair <Andrew.Sinclair@elprotech.com> PR 807/rtems * src/timerfireafter.c, src/timerserverfireafter.c: First patch returned without exitting dispatching critical section.	2005-08-18 13:39:00 +00:00
Joel Sherrill	ecfdafc62e	2005-08-17 Nuno Costa <nuno-costa@iol.pt> PR 805/rtems * include/rtems/posix/timer.h: Due to bad choice of error constants by original submitter, it was impossible to create more than 10 POSIX timers.	2005-08-17 22:56:30 +00:00
Joel Sherrill	f45e8840c8	2005-08-17 Andrew Sinclair <Andrew.Sinclair@elprotech.com> PR 807/rtems * rtems/src/timerfireafter.c, rtems/src/timerserverfireafter.c, score/src/watchdoginsert.c: Tighten critical section checks on an ISR using the same timer being inserted by a lower priority ISR or interupt task.	2005-08-17 22:50:30 +00:00
Joel Sherrill	5978038f77	2005-08-17 Nickolay Semyonov <snob@oktetlabs.ru> PR 744/filesystem * libcsupport/src/unlink.c, libfs/src/dosfs/msdos_eval.c: DOSFS did not support permissions on directories so the check performed by unlink would always fail. The unlink code was modified to support a not supported status being returned.	2005-08-17 19:17:37 +00:00
Joel Sherrill	5c12a265fa	2005-08-12 Chris Johns <chrisj@rtems.org> PR 808/rtems_misc * src/printk.c: Fix bug where specifying field width crashed on pc386 BSP.	2005-08-12 23:55:14 +00:00
Joel Sherrill	3424a93ace	2005-08-12 Phil Torre <ptorre@zetron.com> PR 816/bsps * mpc8xx/include/mpc8xx.h: The struct which describes SCC Ethernet mode parameters (m8xxSCCENparms_t) does not match the hardware: members taddr_h and taddr_l are transposed. When loading new multicast group addresses into the hash table, the wrong hash bit is set.	2005-08-12 23:44:55 +00:00
Ralf Corsepius	28e7d30f34	2005-08-02 Ralf Corsepius <ralf.corsepius@rtems.org> PR 817/rtems * src/gxx_wrappers.c: Rename rtems_gxx_recursive_mutex_init_function to rtems_gxx_recursive_mutex_init.	2005-08-02 12:37:44 +00:00
Joel Sherrill	cec508dafb	2005-07-06 <ralf.corsepius@rtems.org> PR 810/rtems * include/rtems/ide_part_table.h: Add C++ guards.	2005-07-06 18:06:18 +00:00
Joel Sherrill	73ca21f95e	2005-06-09 Jacques Seronie Vivien <jacques.seronievivien@astrium.eads.net> PR 790/rtems * src/extensioncreate.c, src/extensionident.c: Correct use of name. This was missed when the other ident services in rtems/src where changed.	2005-06-09 14:14:04 +00:00
Joel Sherrill	b0c516bfa1	2005-05-20 Sergei Organov <osv@javad.ru> PR networking/772. * rtems_select.c (socket_select): fixed bug setting SB_WAIT flag of so_rcv instead of so_snd when FWRITE.	2005-05-20 19:58:56 +00:00
Joel Sherrill	7918027fad	2005-05-20 Ralf Corsepius <ralf_corsepius@rtems.org> PR 717/bsps * bootloader/Makefile.am: Typo results in wrong flags being used.	2005-05-20 19:53:48 +00:00
Joel Sherrill	da56a02f6c	2005-05-20 Sergei Organov <osv@topconrd.ru> PR 750/networking * pppd/sys-rtems.c: Avoid NULL dereference in wait_input().	2005-05-20 19:31:18 +00:00
Joel Sherrill	c230bc312d	2005-05-20 Sergei Organov <osv@topconrd.ru> PR 749/networking * rtems/rtems_showroute.c: Avoid NULL dereference.	2005-05-20 19:19:17 +00:00
Jennifer Averett	c3f26834d6	2005-05-13 Jennifer Averett <jennifer.averett@oarcorp.com> PR 786/rtems Backport mallocfreespace optimization. * Makefile.am, include/rtems/score/heap.h, src/heapgetinfo.c: * src/heapgetfreeinfo.c: New file.	2005-05-13 17:13:09 +00:00
Jennifer Averett	41ef136059	2005-05-13 Jennifer Averett <jennifer.averett@oarcorp.com> PR 786/rtems Backport mallocfreespace optimization. * Makefile.am, include/rtems/rtems/region.h: * src/regiongetfreeinfo.c: New file.	2005-05-13 17:11:42 +00:00
Jennifer Averett	9d31e3498c	2005-05-13 Jennifer Averett <jennifer.averett@oarcorp.com> * src/mallocfreespace.c: PR 786/rtems Backport mallocfreespace optimization.	2005-05-13 17:09:26 +00:00
cvs2git	d2565cefae	This commit was manufactured by cvs2svn to create branch 'rtems-4-6-branch'. Cherrypick from master 2005-05-03 22:18:32 UTC Joel Sherrill <joel.sherrill@OARcorp.com> '2005-05-03 Joel Sherrill <joel@OARcorp.com>': cpukit/rtems/src/regiongetfreeinfo.c cpukit/score/src/heapgetfreeinfo.c	2005-05-03 22:18:33 +00:00
Jennifer Averett	0bdfa8d3ff	2005-04-28 Jennifer Averett <jennifer.averett@oarcorp.com> PR 781/misc * serial/ns16550_p.h: Fix baud rate calculation	2005-04-28 14:56:36 +00:00
Jennifer Averett	53923e8377	2005-04-11 Jennifer Averett<jennifer.averett@oarcorp.com> PR 778/bsps * include/bsp.h, include/gen2.h, startup/FPGA.c, startup/Hwr_init.c, startup/bspstart.c, tod/tod.c: modify SCORE_.. to BSP_.. for externally used define's.	2005-04-11 20:18:20 +00:00
Jennifer Averett	64c3f790a2	2005-04-11 Jennifer Averett <jennifer@OARcorp.com> PR 777/bsps * include/bsp.h: Add a Processor_Synchronize command in bsp.h	2005-04-11 19:58:14 +00:00
Joel Sherrill	ba10dea56a	2005-03-17 Joel Sherrill <joel@OARcorp.com> * VERSION: Updated to rtems-4.6.3.	2005-03-17 20:33:39 +00:00
Joel Sherrill	6e8a68e6c4	2005-03-17 Joel Sherrill <joel@OARcorp.com> * VERSION: Updated to rtems-4.6.3.	2005-03-17 20:07:38 +00:00
Joel Sherrill	745760302e	2005-03-17 Joel Sherrill <joel@OARcorp.com> * VERSION: Updated to rtems-4.6.3.	2005-03-17 19:29:37 +00:00
Joel Sherrill	732b2b3976	2005-03-17 Joel Sherrill <joel@OARcorp.com> * include/rtems/score/object.h, src/objectinitializeinformation.c: Fix warning.	2005-03-17 14:32:53 +00:00
Joel Sherrill	0be243352f	2005-03-17 Joel Sherrill <joel@OARcorp.com> PR 692/rtems * src/regiongetsegment.c, src/regionreturnsegment.c: The Region Manager did not follow the proper protocol when blocking and unblocking tasks waiting on buffers. This was a bug introduced with the transition to an Allocation Mutex.	2005-03-17 14:30:40 +00:00
Joel Sherrill	70541799ee	2005-03-17 Joel Sherrill <joel@OARcorp.com> * irq/.cvsignore: New file.	2005-03-17 14:26:17 +00:00
Joel Sherrill	9f781394bd	2005-03-17 Joel Sherrill <joel@OARcorp.com> PR 745/rtems * src/ratemoncreate.c, src/timercreate.c: Make sure internal timer structures are initialized so object control reuse is safe.	2005-03-17 14:24:35 +00:00
Joel Sherrill	44eb0beb20	2005-01-20 Joel Sherrill <joel@OARcorp.com> PR 743/bsps * clock/Makefile.am: Did not install tod.h.	2005-01-20 16:54:45 +00:00
Ralf Corsepius	0a7bcfd60a	2005-01-14 Ralf Corsepius <ralf.corsepius@rtems.org> PR 742/rtems * score/include/rtems/system.h: Remove stringify().	2005-01-14 05:23:21 +00:00
Ralf Corsepius	e8ece0b494	2005-01-14 Ralf Corsepius <ralf.corsepius@rtems.org> * src/gxx_wrappers.c: Backport from trunk. Add support for GCC-4.0.	2005-01-14 05:03:32 +00:00
Ralf Corsepius	410c6f8593	2004-12-10 Ralf Corsepius <ralf.corsepius@rtems.org> PR 704/bsps. * ide_ctrl.c: Removed (obsolete).	2004-12-10 09:29:41 +00:00
Joel Sherrill	0bedb7eced	2004-11-23 Richard Campbell <richard.campbell@oarcorp.com> * startup/bspstart.c: Removed mpc824x conditionals around call to L1_caches_enables, conditionals are now in mmuAsm.S. * vme/VMEConfig.h: Set up VME A16, A24 and A32 windows at different locations for mvme2100. * vme/vmeconfig.c: Fixed spelling.	2004-11-23 15:44:50 +00:00
Joel Sherrill	21b54fc117	2004-11-23 Richard Campbell <richard.campbell@oarcorp.com> * powerpc/mpc6xx/mmu/mmuAsm.S: Enable L1 instruction cache only for mpc8240 and mpc8245.	2004-11-23 15:31:19 +00:00
Joel Sherrill	9146692992	Add PR617 as fixed by conversion to new exceptions.	2004-11-22 23:37:11 +00:00
Joel Sherrill	bf423bdb2b	2004-11-22 Jennifer Averett <jennifer@OARcorp.com> * Makefile.am, wrapup/Makefile.am: Pick up SHM driver when MP enabled.	2004-11-22 23:32:33 +00:00
Jennifer Averett	624f551480	2004-11-22 Jennifer Averett <jennifer@OARcorp.com> PR 581/bsps * custom/psim.cfg: Convert PSIM to new exception model.	2004-11-22 22:35:02 +00:00
Jennifer Averett	848d015196	2004-11-22 Jennifer Averett <jennifer@OARcorp.com> * sp07/buffered_io.c: Remove warning.	2004-11-22 22:34:36 +00:00
Jennifer Averett	f778d4c531	2004-11-22 Jennifer Averett <jennifer@OARcorp.com> PR 581/bsps * mpc6xx/exceptions/raw_exception.c, shared/include/cpuIdent.h: Converting PSIM to new exception model required addition of PSIM CPU model.	2004-11-22 22:32:47 +00:00
Jennifer Averett	561f53b71e	2004-11-22 Jennifer Averett <jennifer@OARcorp.com> PR 581/bsps * Makefile.am, bsp_specs, configure.ac, clock/Makefile.am, include/bsp.h, start/Makefile.am, start/start.S, startup/Makefile.am, startup/bspstart.c, startup/linkcmds, vectors/Makefile.am, vectors/vectors.S, wrapup/Makefile.am: Convert PSIM to new exception model. * irq/Makefile.am, irq/irq.c, irq/irq.h, irq/irq_asm.S, irq/irq_init.c: New files. * clock/clock.c: Removed.	2004-11-22 22:30:59 +00:00
Jennifer Averett	24fced7e13	2004-11-22 Joel Sherrill <joel@OARcorp.com> PR 693/misc * rtc/mc146818a_ioreg.c: Disable unless on a target with in/outport routines.	2004-11-22 22:25:05 +00:00
cvs2git	52d276b6bc	This commit was manufactured by cvs2svn to create branch 'rtems-4-6-branch'. Cherrypick from master 2004-11-22 22:13:35 UTC Jennifer Averett <Jennifer.Averett@OARcorp.com> '2004-11-22 Jennifer Averett <jennifer@OARcorp.com>': c/src/lib/libbsp/powerpc/psim/irq/irq.c c/src/lib/libbsp/powerpc/psim/irq/irq.h c/src/lib/libbsp/powerpc/psim/irq/irq_asm.S c/src/lib/libbsp/powerpc/psim/irq/irq_init.c	2004-11-22 22:13:36 +00:00
Ralf Corsepius	0293ad1159	2004-11-22 Ralf Corsepius <ralf.corsepius@rtems.org> PR 721/tests * itronsem01/init.c: Fix bogus assert.	2004-11-22 08:19:13 +00:00
Joel Sherrill	30062b7576	2004-11-16 Richard Campbell <richard.campbell@OARcorp.com> * vmeUniverse/vmeUniverse.c: Use PCI_MEM_BASE_ADJUSTMENT because some boards -- notably the MVME2100 -- return the physical address, not an offset in PCI memory space.	2004-11-16 23:00:27 +00:00
Joel Sherrill	022ee190c8	2004-11-16 Richard Campbell <richard.campbell@OARcorp.com> * README.MVME2100: Update to include DBAT0. * bsp_specs: Fix spacing.	2004-11-16 22:57:50 +00:00
Joel Sherrill	70fefe6879	2004-11-10 Joel Sherrill <joel@oarcorp.com> * tod.c: Add include of tod.h to remove warnings.	2004-11-10 22:38:38 +00:00
Joel Sherrill	d700909e7e	2004-11-10 Richard Campbell <richard.campbell@oarcorp.com> * configure.ac, mpc6xx/exceptions/raw_exception.c, mpc6xx/exceptions/raw_exception.h, mpc6xx/mmu/bat.c, mpc6xx/mmu/bat.h, mpc6xx/mmu/mmuAsm.S, shared/include/cpuIdent.c, shared/include/cpuIdent.h: Add MPC8240 and MPC8245 support. There was also a significant amount of spelling and whitespace cleanup.	2004-11-10 22:37:57 +00:00
Joel Sherrill	b90855ceb3	2004-11-10 Richard Campbell <richard.campbell@oarcorp.com> * network/dec21140.c: Cleanup a bit and remove message about not supported on PowerPC since it works on the MVME2100 BSP.	2004-11-10 22:27:55 +00:00
Joel Sherrill	0b929fe94b	2004-11-10 Joel Sherrill <joel@oarcorp.com> PR 715/bsps * rtc/mc146818a.c: Delete include of bsp.h	2004-11-10 22:27:08 +00:00
Joel Sherrill	5dba517449	2004-11-10 Richard Campbell <richard.campbell@oarcorp.com> * custom/Makefile.am: Add MVME2100 BSP. * custom/mvme2100.cfg: New file.	2004-11-10 22:18:12 +00:00
Joel Sherrill	f74483f280	2004-11-10 Richard Campbell <richard.campbell@oarcorp.com> * aclocal/bsp-alias.m4: Add MVME2100 BSP.	2004-11-10 22:17:37 +00:00
Joel Sherrill	9d8590da5d	2004-11-10 Richard Campbell <richard.campbell@oarcorp.com> * configure.ac: Add TOD support in shared as part of adding MVME2100 BSP.	2004-11-10 22:16:34 +00:00
Joel Sherrill	bd91ff4e71	2004-11-10 Richard Campbell <richard.campbell@oarcorp.com> * ChangeLog, Makefile.am, bootloader/misc.c, bootloader/pci.c, bootloader/pci.h, console/console.c, console/inch.c, console/reboot.c, console/uart.c, console/uart.h, include/bsp.h, irq/irq.c, irq/irq.h, irq/irq_init.c, motorola/motorola.c, motorola/motorola.h, openpic/openpic.c, openpic/openpic.h, pci/detect_raven_bridge.c, pci/pci.c, pci/pci.h, start/start.S, startup/bspstart.c, vectors/vectors_init.c, vme/vmeconfig.c: Add MVME2100 BSP and MPC8240 support. There was also a significant amount of spelling and whitespace cleanup. * tod/.cvsignore, tod/Makefile.am, tod/todcfg.c: New files.	2004-11-10 22:15:01 +00:00
Joel Sherrill	ae460ecea9	2004-11-10 Richard Campbell <richard.campbell@oarcorp.com> * Makefile.am, configure.ac, bootloader/Makefile.am, include/Makefile.am, wrapup/Makefile.am: Add MVME2100 BSP. * README.MVME2100, tod/.cvsignore, tod/Makefile.am: New files.	2004-11-10 22:13:57 +00:00
Joel Sherrill	ef842b4665	2004-11-05 Joel Sherrill <joel@OARcorp.com> PR 706/doc * task.t: Remove not that changes explanation.	2004-11-05 14:37:31 +00:00
Ralf Corsepius	6316b74ef1	2004-10-02 Ralf Corsepius <ralf_corsepius@rtems.org> PR 697/bsps * flashentry/flashentry.S: Fix broken comments (Patch by Thomas.Doerfler@imd-systems.de)	2004-11-02 02:43:35 +00:00
Joel Sherrill	5f56c3c73c	Fixed date.	2004-10-27 19:40:48 +00:00
Ralf Corsepius	d0c64050ec	2004-10-20 Ralf Corsepius <ralf_corsepius@rtems.org> PR 696/bsps * cpu.c: Include bsp.h.	2004-10-20 08:30:22 +00:00