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2004-11-23 Richard Campbell <richard.campbell@oarcorp.com>

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* powerpc/mpc6xx/mmu/mmuAsm.S: Enable L1 instruction cache only for
	mpc8240 and mpc8245.
This commit is contained in:
Joel Sherrill
2004-11-23 15:31:19 +00:00
parent 9146692992
commit 21b54fc117
2 changed files with 18 additions and 1 deletions
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5
c/src/lib/libcpu/ChangeLog
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@@ -1,3 +1,8 @@
2004-11-23 Richard Campbell <richard.campbell@oarcorp.com>
* powerpc/mpc6xx/mmu/mmuAsm.S: Enable L1 instruction cache only for
mpc8240 and mpc8245.
2003-09-04 Joel Sherrill <joel@OARcorp.com>
* shared/include/cache.h, shared/src/cache_aligned_malloc.c,

14
c/src/lib/libcpu/powerpc/mpc6xx/mmu/mmuAsm.S
View File

@@ -18,6 +18,7 @@
#include <asm.h>
#include <rtems/score/cpu.h>
#include <libcpu/io.h>
#include <bspopts.h>
/* Unfortunately, the CPU types defined in cpu.h are
* an 'enum' type and hence not available :-(
@@ -137,7 +138,18 @@ L1_caches_enables:
beq 4f /* not needed for 601 */
mfspr r11,HID0
andi. r0,r11,HID0_DCE
ori r11,r11,HID0_ICE|HID0_DCE
#if defined(mpc8240) || defined(mpc8245)
/*
* Data cache is broken for mpc8240 and mpc8245,
* enable instruction cache only.
*/
ori r11,r11,HID0_ICE
#else
/*
* Enable both instruction and data caches
*/
ori r11,r11,HID0_ICE|HID0_DCE
#endif
ori r8,r11,HID0_ICFI
bne 3f /* don't invalidate the D-cache */
ori r8,r8,HID0_DCI /* unless it wasn't enabled */