Commit Graph

27216 Commits

Author SHA1 Message Date
Sebastian Huber
f553c6ebbe rtems: Inline rtems_clock_get_ticks_since_boot()
Update documentation.
2014-08-25 08:57:36 +02:00
Daniel Cederman
e7a42a0cfb score: Add missing define to cache manager 2014-08-25 08:52:05 +02:00
Pavel Pisa
d13ce7553b bsp/tms570: implemented and tested initialization of Cortex-R performance counters.
The code is written as BSP specific now but it should work for all
Cortex-A and R based CPUs and can be moved to ARM generic place in future.

StackOverflow suggested sequences of writes to the registers required
to start counters is used.

http://stackoverflow.com/questions/3247373/how-to-measure-program-execution-time-in-arm-cortex-a8-processor
2014-08-22 10:24:53 -05:00
Daniel Cederman
9a9ab85b45 smptests/smpcache01: Test the SMP cache manager
Invokes SMP cache management routines under different scenarios.
2014-08-22 13:10:59 +02:00
Daniel Cederman
ddbc3f8d83 score: Add SMP support to the cache manager
Adds functions that allows the user to specify which cores that should
perform the cache operation. SMP messages are sent to all the specified
cores and the caller waits until all cores have acknowledged that they
have flushed their cache. If CPU_CACHE_NO_INSTRUCTION_CACHE_SNOOPING is
defined the instruction cache invalidation function will perform the
operation on all cores using the previous method.
2014-08-22 13:10:59 +02:00
Daniel Cederman
62f373fb57 bsp/sparc: Flush only instruction cache
The flush instruction on LEON flushes both the data and the instruction
cache. Flushing of just the instruction cache can be done by setting
the "flush instruction cache" bit in the cache control register.
2014-08-22 13:10:59 +02:00
Daniel Cederman
bba83e5191 score/sparc: Add comment on icache flush after trap table update
Changes to the trap table might be missed by other cores.
If the system state is up, the other cores can be notified
using SMP messages that they need to flush their icache.
If the up state has not been reached there is no need to
notify other cores. They will do an automatic flush of the
icache just after entering the up state, but before enabling
interrupts. Cache invalidation is required for both single
and multiprocessor systems.
2014-08-22 13:10:59 +02:00
Daniel Cederman
54f3476e24 bsp/sparc: Flush icache before first time enabling interrupts
A secondary processor might miss changes done to the trap table
if the instruction cache is not flushed. Once interrupts are enabled
any other required cache flushes can be ordered via the cache
manager.
2014-08-22 13:10:59 +02:00
Daniel Cederman
aed38189be score: Rename SMP broadcast message function
Change message type to unsigned long to match other SMP message functions.
2014-08-22 13:10:59 +02:00
Daniel Cederman
a68cc1bb10 score: Add function to send a SMP message to a set of CPUs 2014-08-22 13:10:58 +02:00
Christian Mauderer
d5f5432967 libchip/dwmac: Make PHY address user configurable
This patch allows the user to configure the PHY address for the DWMAC
driver by giving a pointer to a dwmac_user_cfg structure to network
stack via rtems_bsdnet_ifconfig::drv_ctrl.
2014-08-22 11:48:27 +02:00
Pavel Pisa
66f1ca64c8 bsp/tms570: disable huge memory demanding tests for internal RAM build variant.
BSP completes build with tests and debug enabled for all three variants now

  tms570ls3137_hdk
  tms570ls3137_hdk_intram
  tms570ls3137_hdk_sdram

Even that all enabled tests builds for internal RAM variant, many
of them are expected to fail on hardware because whole tests
including code, data and runtime work area demands has to fit
into 256 kB of RAM.
2014-08-21 10:56:13 -05:00
Pavel Pisa
46265063e3 bsp/tms570: implemented support functions to satisfy complete tests build requirements.
This patch enables to build all RTEMS tests for tms570ls3137_hdk_sdram
BSP variant in in default build. Debug build with --enable-rtems-debug set
has succeed for samples subset of tests as well.
2014-08-21 09:07:29 -05:00
Joel Sherrill
57871880b2 Add configuration to detect toolset has sigaltstack() prototype 2014-08-20 18:47:02 -05:00
Peter Dufault
dc661c87e1 mpc55xx/misc/flash_support.c: Properly flush cache when writing.
Also cleanup:
    * Remove un-needed interrupt disables.
    * Address errata "e989: FLASH: Disable Prefetch during programming and erase"
    * Use RTEMS_ARRAY_SIZE() macro instead of own macro.
2014-08-20 17:08:23 -05:00
Joel Sherrill
a7ec6fac9b or1k.t: Fix spelling errors 2014-08-20 15:49:42 -05:00
Hesham ALMatary
b08829228d Add new documentation section for OpenRISC CPU architecture. 2014-08-20 15:46:15 -05:00
Joel Sherrill
2ed97d94da libbsp/arm/acinclude.m4: Regenerate for tms570 2014-08-20 14:53:18 -05:00
Hesham ALMatary
fd5701587f Add new (first) OpenRISC BSP called or1ksim.
This BSP is intended to run on or1ksim (the main OpenRISC emulator).
Fixed version according to Joel comments from the mailing list.
2014-08-20 14:46:15 -05:00
Premysl Houdek
4407ee675c BSP for TMS570LS31x Hercules Development Kit from TI (TMS570LS3137)
Included variants:
  tms570ls3137_hdk_intram - place code and data into internal SRAM
  tms570ls3137_hdk_sdram - place code into external SDRAM and data to SRAM
  tms570ls3137_hdk - variant prepared for stand-alone RTEMS aplication
                      stored and running directly from flash. Not working yet.

Chip initialization code not included in BSP.
External startup generated by TI's HalCoGen was used	for
testing and debugging.

More information about TMS570 BSP can be found at
  http://www.rtems.org/wiki/index.php/Tms570

Patch version 2
  - most of the formatting suggestion applied.
  - BSP converted to use clock shell
  - console driver "set attributes" tested. Baudrate change working
Patch version 3
  - more formatting changes.
  - removed leftover defines and test functions
Todo:
  refactor header files (name register fields)
2014-08-20 13:44:23 -04:00
Pavel Pisa
0a66c1266f lpc24xx/lpc17xx: lpc24xx_pin_set_function() keep LPC4088 W type pin in digital mode for non-analog function.
The problem wit incorrect switching of pins into analog mode manifestes
on LPC4088 based board.

LPC4088 implements pin P1.17 (ENET_MDIO) as new W type (digital pin
with analog option). The pin was listed as D category on LPC1788
which does not have analog mode control bit. If analog option is
not explicitly switched off on LPC4088 then the pin does not work
as digital pin.

Code tested on LPC1788 and no problems has been observed even that
manual specifies the IOCON_ADMODE field as reserved and should
be written as zero. But even RTEMS lpc24xx_gpio_config sets this
bit unconditionally.

Signed-off-by: Pavel Pisa <ppisa@pikron.com>
2014-08-20 13:42:26 +02:00
Sebastian Huber
bba3507723 score: PR2179: Fix initially locked PI mutex 2014-08-20 08:17:49 +02:00
Kolja Waschk
3654667f77 rtems_termios_puts: Copy and write more than one char at once
Renamed startXmit(), nToSend is unsigned, just check FL_ORCVXOF, no (void) cast anymore, compute nToSend in single if/else if/else.
2014-08-18 18:39:44 -05:00
Hesham ALMatary
de62e5d861 Add or1k tick timer register definitions 2014-08-18 17:10:00 -05:00
Sebastian Huber
1a2d349776 arm: PR2186: Fix compile error 2014-08-14 14:27:40 +02:00
Joel Sherrill
700f97ea67 or1k/.../preinstall.am: Add missing file 2014-08-12 13:46:49 -05:00
Hesham ALMatary
94d45f6ffe Add support for OpenRISC - Fixed issues
This work is based on the old or32 port (that has been
removed back in 2005) authored by Chris Ziomkowski. The patch includes the
basic functions every port should implement like: context switch, exception
handling, OpenRISC ABI and machine definitions and configurations.
2014-08-12 13:40:45 -05:00
Sebastian Huber
6cdc090ff0 bsp/lpc24xx: Add LPC40XX variants 2014-08-12 19:08:37 +02:00
Sebastian Huber
8ae373235b arm: Add support for FPv4-SP floating point unit
This floating point unit is available in Cortex-M4 processors and
defined by ARMv7-M.  This adds basic support for other VFP-D16 variants.
2014-08-12 19:08:19 +02:00
Christian Mauderer
81329f9ecf bsp/altera-cyclone-v: Add RTC driver. 2014-08-11 08:01:26 +02:00
Christian Mauderer
3f9cd87d76 bsp/altera-cyclone-v: Add a simple I2C driver. 2014-08-11 08:01:26 +02:00
Christian Mauderer
1642d27e4c bsp/altera-cyclone-v: Add socal from hwlib.
Some of the headers from the hwlib need the files from the socal subdirectory.
2014-08-11 08:01:26 +02:00
Sebastian Huber
0b9fe3ec66 sptests/sprbtree01: Add random ops test case 2014-08-08 11:11:27 +02:00
Sebastian Huber
0ef6e3bfb9 rbtree: Simplify _RBTree_Extract() 2014-08-07 15:59:29 +02:00
Sebastian Huber
993f5acd25 rbtree: Simplify insert and extract
Simplify _RBTree_Insert() and _RBTree_Extract().  Remove more
superfluous NULL pointer checks.  Change _RBTree_Is_root() to use only
the node.  Add parent parameter to _RBTree_Sibling().  Delete
_RBTree_Grandparent() and _RBTree_Parent_sibling().
2014-08-07 15:59:29 +02:00
Sebastian Huber
4752550f80 rbtree: Simplify _RBTree_Rotate()
Add and use _RBTree_Direction().
2014-08-07 15:59:25 +02:00
Sebastian Huber
d472d21780 sptests/sprbtree01: Check tree layout 2014-08-05 15:17:51 +02:00
Sebastian Huber
888edf69a9 sptests/sprbtree01: Reduce stack usage 2014-08-05 15:17:43 +02:00
Sebastian Huber
390cfcda71 posix: Simplify key implementation 2014-08-05 09:30:37 +02:00
Sebastian Huber
60fe374247 rbtree: Add and use RBTree_Compare_result 2014-08-05 09:30:37 +02:00
Sebastian Huber
40dcafaf80 Add and use RTEMS_CONTAINER_OF() 2014-08-05 09:30:33 +02:00
Sebastian Huber
b767683a5e rbtree: Rename find header in find control
Simplify _RBTree_Find_control().  Avoid superfluous NULL pointer checks.
2014-07-29 14:05:17 +02:00
Sebastian Huber
6e93c836e2 rbtree: Simplify off-tree handling
Only use the parent pointer, since this pointer is never NULL for nodes
which are part of a tree.

Rename functions from *_off_rbtree() to *_off_tree().
2014-07-29 14:05:08 +02:00
Sebastian Huber
4cd55724bb Delete unused *_Is_null() functions 2014-07-26 12:52:22 +02:00
Sebastian Huber
639117fd12 rbtree: Update maximum node in LIFO order
The test sptests/sp35 showed a NULL pointer access due to an invalid
maximum node field (e.g. a tree with one element and NULL as the maximum
node).
2014-07-26 12:01:25 +02:00
Joel Sherrill
9113798c83 todimpl.h: Add missing Doxygen 2014-07-23 16:53:24 -05:00
Joel Sherrill
0a84c29890 coretod*.c: Fix Doxygen group and comment formatting 2014-07-23 16:53:24 -05:00
Joel Sherrill
875fff0ae3 Add _TOD_Adjust to SCORE TOD Handler.
This lays the proper structure for doing future work on
time adjustment algorithms. Any TOD adjustments should be
requested at the API level and performed at the SCORE level.

Additionally updated a test.
2014-07-23 16:53:24 -05:00
Joel Sherrill
3b6352d2e6 adjtime.c: Use timestamp math and simplify 2014-07-23 14:24:49 -05:00
Sebastian Huber
8abbbdde38 rbtree: Do not set node off-tree in extract 2014-07-22 12:31:41 +02:00