The fix to address CID 1399742 (NO_EFFECT) in commit
f8b6359415 introduced a bug since
LEON3_IrqCtrl_EIrq == -1 in case no extended interrupts are supported by
the interrupt controller. Fix this by checking for
LEON3_IrqCtrl_EIrq > 0.
In addition, interrupt number 0 is reserved and should not be used.
The GICv3 support is shared between AArch32 and AArch64. For AArch32,
the new AARCH64_IS_NONSECURE is never defined. Use ARM_MULTILIB_ARCH_V4
instead.
This issue was introduced by 76c6caad52.
There is still a change in bsp_interrupt_vector_enable() for AArch32
compared to the version before 76c6caad52.
The existing fix for the ZynqMP UART hardware bug only caught the vast
majority of instances where it could occur. To fully fix the data
corruption, this fix must be applied after every baud rate change. This
makes the logic reset and kick apply in any locations where the baud
rate could be changed.
The Cortex-R52 does not support cache coherency and the shareable memory
attribute. If a region is configured to be shareable, then it falls
back to use non-cacheable memory.
Update #4202.
Provide the options necessary to enable any combination of CGEM ethernet
interfaces in LibBSD. The default is still CGEM3, so this should
continue to operate as expected on typical Zynq Ultrascale+ MPSoC
development hardware.
This change allows for the migration of higher priority tasks on the
arrival of a lower priority task limited by affinity constraints.
Change license to BSD-2-Clause according to file history and
re-licensing agreement.
Update #3053.
Move _ISR_Handler() to a separate file since it is now only used if a handler
is installed by _CPU_ISR_install_raw_handler().
Statically initialize the traps for external interrupts to use the new
_SPARC_Interrupt_trap() which directly dispatches the interrupt handlers
installed by rtems_interrupt_handler_install() via the BSP-provided
_SPARC_Interrupt_dispatch().
Since the trap table is now fully statically initialized, there is no longer a
dependency on the Cache Manager in the default configuration.
Update #4458.
Add bsp_interrupt_handler_dispatch_unchecked() as an alternative to
bsp_interrupt_handler_dispatch(). It may be used if the caller can ensure that
the vector number is valid.
Statically initialize the trap table in start.S to jump to _SPARC_Bad_trap()
for all unexpected traps. This enables a proper RTEMS fatal error handling
right from the start. Do not rely on the stack and register settings which
caused an unexpected trap. Use the ISR stack of the processor to do the fatal
error handling. Save the full context which caused the trap. Fatal error
handler may use it for error logging.
Unify the _CPU_Exception_frame_print() implementations and move it to cpukit.
Update #4459.
Move _CPU_ISR_install_raw_handler() and _CPU_ISR_install_vector() to separate
files. The goal is to make their use optional.
Update #4458.
Update #4459.
This makes it easier to review start.o and set break points to trap table
entries. This change was checked by inspecting the trap table in start.o with
objdump.
Update #4458.
The _ISR_Handler_initialization() does not touch the _ISR_Vector_table[]. Move
the definition of _ISR_Vector_table[] to a separate file.
Change license to BSD-2-Clause according to file history and re-licensing
agreement.
Update #3053.
This CPU port macro was not used. Since the _ISR_Vector_table[] is statically
allocated, CPU ports could initialize this table in _CPU_Initialize() if
necessary. Remove _CPU_Initialize_vectors() to simplify the CPU port
interface.
Change the default value of BSP_INTERRUPT_VECTOR_COUNT so that no interrupt
vectors are supported and all related directives return RTEMS_INVALID_ID.
Update #3269.
Assert BSP_INTERRUPT_VECTOR_MAX + 1 == BSP_INTERRUPT_VECTOR_COUNT.
After building all BSPs with this patch, BSP_INTERRUPT_VECTOR_MAX can be
removed and replaced by BSP_INTERRUPT_VECTOR_COUNT. The
BSP_INTERRUPT_VECTOR_COUNT allows a default implementation which supports no
interrupt vector at all. Using COUNT instead of MAX may avoid some
interpretation issues, for example is the maximum value a valid vector number
or not.
Update #3269.
Remove BSP_INTERRUPT_VECTOR_MIN and unconditionally let interrupt vector
numbers start with zero.
The BSP_INTERRUPT_VECTOR_MIN == 0 invariant was tested by the previous commit
and building all BSPs.
Update #3269.
This BSP uses a customized implementation of the interrupt extension API. It
was the only BSP which defined BSP_INTERRUPT_VECTOR_MIN to a value other than
zero. Define it to zero and use a custom bsp_interrupt_is_valid_vector()
function instead.
Update #3269.
This adds the possibility to open an I2C bus with O_NONBLOCK (or set it
later via fcntl) to get non-blocking transmissions. This means that if
the bus is busy, a read, write or transfer ioctl will return with a
EAGAIN errno.
The write to RBAR didn't have the valid flag set. Therefore the write to
RASR had an influence on the previously set region. That means for
example that if Region 0 had been enabled but 1 should be disabled due
to a size of 0, the previous code would have disabled region 0 instead.
This patch fixes that behaviour.
Close#4450
