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arm: For AArch32 use non-shareable memory

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The Cortex-R52 does not support cache coherency and the shareable memory
attribute.  If a region is configured to be shareable, then it falls
back to use non-cacheable memory.

Update #4202.
This commit is contained in:
Sebastian Huber
2021-06-24 12:20:32 +02:00
parent 9b84adb4aa
commit bb9a4b816b
1 changed files with 2 additions and 2 deletions
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4
cpukit/score/cpu/arm/include/rtems/score/aarch32-pmsa.h
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@@ -141,7 +141,7 @@ extern "C" {
( AARCH32_PMSA_ATTR_EN | \
AARCH32_PMSA_ATTR_XN | \
AARCH32_PMSA_ATTR_AP( AARCH32_PMSA_ATTR_AP_EL1_RO_EL0_NO ) | \
AARCH32_PMSA_ATTR_SH( AARCH32_PMSA_ATTR_SH_OUTER ) | \
AARCH32_PMSA_ATTR_SH( AARCH32_PMSA_ATTR_SH_NO ) | \
AARCH32_PMSA_ATTR_IDX( 0U ) )
#define AARCH32_PMSA_DATA_READ_ONLY_UNCACHED \
@@ -155,7 +155,7 @@ extern "C" {
( AARCH32_PMSA_ATTR_EN | \
AARCH32_PMSA_ATTR_XN | \
AARCH32_PMSA_ATTR_AP_EL1_RW_EL0_NO | \
AARCH32_PMSA_ATTR_SH( AARCH32_PMSA_ATTR_SH_OUTER ) | \
AARCH32_PMSA_ATTR_SH( AARCH32_PMSA_ATTR_SH_NO ) | \
AARCH32_PMSA_ATTR_IDX( 0U ) )
#define AARCH32_PMSA_DATA_READ_WRITE_UNCACHED \