Commit Graph

22 Commits

Author SHA1 Message Date
Joel Sherrill
be6e30dff3 bsps/arm: Move SPDX line to top of file
The RTEMS Software Engineering Guide specifies that the SPDX license
annotation shouldbe the first line of the file and not part of the
copyright/license comment block.
2025-08-11 19:06:32 +00:00
Amar Takhar
b714e4a809 ascii: Remove non-ASCII characters
We will soon be enforcing ASCII-only characters for source.
2025-05-22 19:35:12 +00:00
Sebastian Huber
c4c3e68790 bsps/arm: Use fatal error for data cache disable
On the Cortex-A cores, at least the L1 data cache is required to provide
support for atomic operations.

Close #5050.
2024-06-25 03:58:34 +00:00
Sebastian Huber
3a281aca37 bsps/arm: Fix L2C-310 instruction enabled/disable
Set/clear SCTLR[I] on all online processors.  Do not enable/disable the
L2C-310 cache in the instruction cache enable/disable since it is a
unified cache.
2024-06-25 03:58:34 +00:00
Sebastian Huber
ef9b49dc24 bsps/arm: Fix Doxygen group placement 2024-06-25 03:58:34 +00:00
Sebastian Huber
123e0e6fb6 bsps/cache: Fix ARM CP-15 get cache size
The rtems_cache_get_data_cache_size() and
rtems_cache_get_instruction_cache_size() functions shall return the entire
cache size for a level of 0.  Levels greater than 0 shall return the size of
the associated level.

Update #4982.
2024-06-04 15:50:57 +00:00
Sebastian Huber
ef570cf157 bsps/cache: Simplify Cortex-R5 cache support
Update #4982.
2024-06-04 15:50:57 +00:00
Sebastian Huber
f5b52a3af0 bsps/arm: Fix Doxygen group assignment 2024-05-07 11:16:49 +02:00
Sebastian Huber
ffec9f96fc arm: Fix cache support for ARM926EJ-S
The ARM926EJ-S is an ARMv5T architecture processor and lacks some
features of ARMv6 processors such as the ARM1176JZF-S.

Close #4940.
2023-08-10 08:34:34 +02:00
Sebastian Huber
f69326d0c2 bsps: Improve Doxygen file comments 2023-05-26 06:56:11 +02:00
Sebastian Huber
bcef89f236 Update company name
The embedded brains GmbH & Co. KG is the legal successor of embedded
brains GmbH.
2023-05-20 11:05:26 +02:00
Joel Sherrill
8ca4b5c8bb bsps/arm/shared: Change license to BSD-2
Updates #3053.
2022-07-08 08:42:42 -05:00
Joel Sherrill
ba619b7f36 bsps/arm/: Scripted embedded brains header file clean up
Updates #4625.
2022-03-10 08:43:50 +01:00
Sebastian Huber
b32fd22732 bsps/arm: Add arm-data-cache-loop-set-way.h
This makes it possible to reuse this loop.

Update #4202.
2020-12-23 09:19:28 +01:00
Sebastian Huber
e68827e1d9 arm/cache-cp15: Support Armv8
Update #4202.
2020-12-10 07:58:03 +01:00
Sebastian Huber
828276b081 bsps: Adjust shared Doxygen groups
Update #3706.
2019-03-08 07:42:54 +01:00
Sebastian Huber
e7d623e7e2 bsps/arm: Conditional ARMv7-AR data cache disable
Update #3667.
Close #3674.
2019-01-10 08:12:16 +01:00
Thomas Dörfler
0abe47f142 bsps/arm: Fix typo in disable cache for ARMv7-AR
Update #3667.
2019-01-10 08:12:16 +01:00
Sebastian Huber
c37807e97c bsps/arm: Add cache size support for CP15 2018-12-21 11:57:49 +01:00
Sebastian Huber
41a557bc2f bsps/arm: Add ARMv7-AR disable data cache
Close #3667.
2018-12-21 10:32:41 +01:00
Sebastian Huber
ba856559a4 ARM_CACHE_L1_CPU_SUPPORT_PROVIDES_RANGE_FUNCTIONS
Remove this superfluous define.

Update #3667.
2018-12-21 10:32:25 +01:00
Sebastian Huber
4cf93658ef bsps: Rework cache manager implementation
The previous cache manager support used a single souce file
(cache_manager.c) which included an implementation header (cache_.h).
This required the use of specialized include paths to find the right
header file.  Change this to include a generic implementation header
(cacheimpl.h) in specialized source files.

Use the following directories and files:

* bsps/shared/cache

* bsps/@RTEMS_CPU@/shared/cache

* bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILY/start/cache.c

Update #3285.
2018-01-31 12:49:09 +01:00