On some targets or configurations, the data cache cannot be disabled.
The data cache may be necessary to provide atomic operations. In SMP
configurations, the data cache may be required to ensure data coherency.
Close#5050.
This adds error reporting for ZynqMP including L1 and L2 cache, on-chip
memory (OCM) error correcting code (ECC), and DDR ECC. OCM ECC supports
fault injection from within RTEMS. DDR ECC technically supports fault
injection as well, but requires that the program injecting faults
operate exclusively outside of DDR. The AArch64 port is not currently
capable of operating exclusively in OCM due to size constraints and
would need to be booted via JTAG or via a non-relocating u-boot to
accomplish this.
## spec/stm32h7: Default nucleo-h755zi BSP to build for CORE_M7
Some of the STM32H7 parts have a secondary Cortex M4 core included and require the user to select which core they are compiling for. The `arm/nucleo-h755zi` BSP was lacking a default core selection, causing the BSP to fail to build with the default options selected. This PR changes the default option to select the larger Cortex M7 core by default.
Use first 1GiB of the DDR RAM with the exception of a potential 64KiB NULL
pointer protection area by default. The upper part of the DDR RAM may be used
by the RPU or for dynamic memory.
## Implement a new ST Nucleo STM32H755ZI BSP
Hi all, for a project I recently acquired a Nucleo STM32H755ZI. Thanks to the work of @sebhub, @c-mauderer, and Karel Gardas, it was pretty easy to create a new Nucleo BSP for this chip by copying the Nucleo H743 BSP. I was not able to get the 8 MHz HSE clock enabled, so this is currently clocked off of the PLL using the 64 MHz HSI clock and the RTC clock is disabled. Other features haven't been thoroughly tested, but since they rely on the high quality STM32H7 HAL from ST, I have pretty high confidence in them. I've been able to run most testsuites.
I have tested:
* The CM7 core
* The CM4 core
* Console output on UART3 (the default USB UART) and the shell
* GPIO
* Sample programs like `hello`, `fileio` (and shell), `paranoia`, `unlimited`, etc.
Known Broken:
* Debugging with OpenOCD is wonky. I can set breakpoints, halt the processor and inspect memory and registers and return from functions, but stepping does not work.
* The program begins to run after being flashed but soon (under 1 second) stops running. Pressing the reset button makes the program run continuously afterward. The board resets nearly instantly.
* Shell commands `ls`, `cd`, `cpuuse`, etc. hang for a while before executing. I'm not sure where the time is spent because the built-in `time` command reports that these commands execute nearly instantly.
I haven't tested:
* Pretty much everything else
<!-- Default settings, if it is a dropdown it will set after submission -->
There were some problems in the math calculating RAM length and NOCACHE
origin location. These have been resolved in this patch allowing RTEMS
RAM space to be relocated above 0xfe00000 to better accomodate other
elements in the system.
Add directives to get and set the priority of an interrupt vector.
Implement the directives for the following BSP families:
* arm/lpc24xx
* arm/lpc32xx
* powerpc/mpc55xxevb
* powerpc/qoriq
Implement the directives for the following interrupt controllers:
* GICv2 and GICv3 (arm and aarch64)
* NVIC (arm)
* PLIC (riscv)
Update #5002.
The clock from the ARM timer is derived from the system clock. This clock can
change dynamically e.g. if the system goes into reduced power or in low power
mode. Thus the clock speed adapts to the overall system performance
capabilities. For accurate timing it is recommended to use the system timers.
if BSP_CLOCK_USE_SYSTEMTIMER = 1, use the System Timer, otherwise use the ARM
Timer.
Make the clock driver parameters configurable. Use the maximum counter
frequency to get the best time resolution. Decouple the CPU counter from the
timecounter. Make the tick catch up handling more robust. Add a validation
test for the tick catch up.
Replace the BSP_CONSOLE_MINOR BSP option for the Xilinx Zynq BSPs with the new
BSP option ZYNQ_UART_KERNEL_IO_BASE_ADDR. Move the kernel I/O support to a
shared file.
This adds a test to very that remounting a completely used, but empty
NOR JFFS2 filesystem is possible. Previously, this triggered an edge
condition in the JFFS2 scan code that prevented remount of a correctly
formed and uncorrupted filesystem.
The RAM origin had an unnecessary alignment requirement and the RAM
lenght had a reference that couldn't possibly be used. This removes
those obsolete option specifiers.
When the switch to waf occurred, the SMP support in i386 was left out
causing it to accumulate a minor amount of cruft. This enables SMP for
the i386 BSPs that support it and updates them for the API drift that
has occurred since the change.
