Whether a floating-point implementation supports trapping of
floating-point exceptions is implementation defined. At least Qemu,
Cortex-A53, and Cortex-A72 do not support them.
In SMP configurations, check that we run on a configured processor. If not,
then there is not much that can be done since we do not have a stack available
for this processor. Just loop forever in this case. Do this in assemlby to
ensure that no stack memory is used.
Make the support for starting in EL2/EL3 customizable. A boot loader or
the Arm Trusted Firmware should start RTEMS in non-secure EL1 mode.
In start.S, use local labels.
For the aarch64/xilinx-zynqmp the support for starting in EL2/EL3 is
disabled by default. For the Qemu xlnx-zcu102 machine, the default is
to start in non-secure EL1 mode. This can be controlled by options, for
example "-machine xlnx-zcu102,secure=on,virtualization=on".
The information from the README.md have been merged into the
documentation.
The necessary tools for the sdcard.sh are quite tricky to build. All
necessary information to create an SD image are in the documentation
already. So the script isn't necessary any more.
Update #5088
Dynamically mapped blocks must be aligned to the MMU page size just like
startup-configured blocks. This was not being enforced and could cause a
hang with bad input.
Rename xilinx_zynqmp_rpu BSP variant to zynqmp_rpu_lock_step to
emphasize that this BSP is for the lock-step mode RPU configuration.
Add BSP variants zynqmp_rpu_split_0 and zynqmp_rpu_split_1 for the split
mode RPU configuration for core 0 and 1 respectively.
Remove copyright from DornerWorks since the files contain not contributions
from this company. Fix the copyright years of the embedded brains
contributions.
Add support for the BSP_ARM_GIC_MULTI_PROCESSOR_SECONDARY build option
for the GICv2 support. This option is useful for multiprocessor systems
without SMP support.
Do not wait in the individual _CPU_SMP_Start_processor() for the
secondary processor. Wait for all of them in
_CPU_SMP_Finalize_initialization() before the L2 cache is enabled.
There is no need to wait for the secondary processor in
_CPU_SMP_Start_processor() since _CPU_SMP_Finalize_initialization() does
nothing.
The caller of _CPU_SMP_Start_processor() ensures that we do not start
the current processor.
Remove copy and paste from the arm SMP support. The shared aarch64
implementation of rtems_cache_enable_data() does not enable a particular
cache, it just enables the C bit in the SCTLR_EL1. This is already done
in aarch64_mmu_enable(). There is no need to wait for secondary
processors in _CPU_SMP_Start_processor().
