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aarch64: Remove trapped FP exceptions support

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Whether a floating-point implementation supports trapping of
floating-point exceptions is implementation defined.  At least Qemu,
Cortex-A53, and Cortex-A72 do not support them.
This commit is contained in:
Sebastian Huber
2024-10-04 03:48:19 +02:00
parent 42c6f727d6
commit c538079ec1
1 changed files with 0 additions and 21 deletions
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21
cpukit/score/cpu/aarch64/aarch64-exception-default.c
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@@ -42,29 +42,8 @@
#include <rtems/score/cpu.h>
#include <rtems/fatal.h>
#include <rtems/score/aarch64-system-registers.h>
void _AArch64_Exception_default( CPU_Exception_frame *frame )
{
uint64_t EC = AARCH64_ESR_EL1_EC_GET( frame->register_syndrome );
/* Emulate FPSR flags for FENV if a FPU exception occurred */
if ( EC == 0x2c ) {
/*
* This must be done because FENV depends on FPSR values, but trapped FPU
* exceptions don't set FPSR bits. In the case where a signal is mapped, the
* signal code executes after the exception frame is restored and FENV
* functions executed in that context will need this information to be
* accurate.
*/
uint64_t ISS = AARCH64_ESR_EL1_EC_GET( frame->register_syndrome );
/* If the exception bits are valid, use them */
if ( ( ISS & ( 1 << 23 ) ) != 0 ) {
/* The bits of the lower byte match the FPSR exception bits */
frame->register_fpsr |= ( ISS & 0xff );
}
}
rtems_fatal( RTEMS_FATAL_SOURCE_EXCEPTION, (rtems_fatal_code) frame );
}