In the original implementation, level -1 was unused and all levels could
have block-like descriptors (level 2 block descriptors are called page
descriptors). When support for level -1 page tables was added the
constraint on level -1 block descriptors was not honored. This prevents
block descriptors from being mapped at level -1 since the hardware will
not map them properly.
This patch changes the license to BSD-2 for all source files where the
copyright is held by Aeroflex Gaisler, Cobham Gaisler, or Gaisler Research.
Updates #3053.
This patch changes the license to BSD-2 for all source files where the
copyright is held by Aeroflex Gaisler, Cobham Gaisler, or Gaisler Research.
Some files also includes copyright right statements from OAR and/or
embedded Brains in addition to Gaisler.
Updates #3053.
This patch changes the license to BSD-2 for all source files where the
copyright is held by Aeroflex Gaisler, Cobham Gaisler, or Gaisler Research.
Some files also includes copyright right statements from OAR and/or
embedded Brains in addition to Gaisler.
Updates #3053.
This patch changes the license to BSD-2 for all source files where the
copyright is held by Aeroflex Gaisler, Cobham Gaisler, or Gaisler Research.
Some files also includes copyright right statements from OAR and/or
embedded Brains in addition to Gaisler.
Updates #3053.
This patch changes the license to BSD-2 for all source files where the
copyright is held by Aeroflex Gaisler, Cobham Gaisler, or Gaisler Research.
Some files also includes copyright right statements from OAR and/or
embedded Brains in addition to Gaisler.
Updates #3053.
This patch changes the license to BSD-2 for all source files where the
copyright is held by Aeroflex Gaisler, Cobham Gaisler, or Gaisler Research.
Some files also includes copyright right statements from OAR and/or
embedded Brains in addition to Gaisler.
Updates #3053.
In SMP configurations, there may be no software interrupt handler
installed when the software interrupt is processed. Add the new
interrupt handler dispatch variant
bsp_interrupt_handler_dispatch_unlikely() for this special case.
Use the tm27 support to test a spurious interrupt. This helps to run the
validation test case on targets which have no software interrupt available for
tests (for example riscv/PLIC/CLINT in the SMP configuration).
Where CPU_ENABLE_ROBUST_THREAD_DISPATCH == TRUE, the only supported interrupt
level allowed to set is 0 (interrupts enabled). This constraint is enforced by
the API level functions which return an error status for other interrupt
levels.
The extra digest copy was introduced by an erroneous merge conflict resolution
for commit "crypto routines: Hint minimum buffer sizes to the compiler".
The AArch64 TRM specifies that when FPCR is set to trap floating point
exceptions, the FPSR exception bits are not set. This ensures that FPSR
is updated as FENV expects even if floating point exception traps are
enabled.
This adds a BSP variant for the ZynqMP BSP family to support the
Innoflight CFC-400X platform. To properly support the CFC-400X, device
trees were added to the ZynqMP platform due to both the optional
management interface as well as alternate physical configuration of the
ethernet interfaces.
- see ARM DUI 0646C Arm Cortex-M7 Devices Generic User Guide
"The RELOAD value is calculated according to its use.
For example, to generate a multi-shot timer with a period
of N processor clock cycles, use a RELOAD value of N-1.
If the SysTick interrupt is required every 100 clock pulses,
set RELOAD to 99."
- see routines used in CMSIS project for reference
Close#4746.
