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riscv: Simplify _CPU_ISR_Set_level()

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Where CPU_ENABLE_ROBUST_THREAD_DISPATCH == TRUE, the only supported interrupt
level allowed to set is 0 (interrupts enabled).  This constraint is enforced by
the API level functions which return an error status for other interrupt
levels.
This commit is contained in:
Sebastian Huber
2022-11-08 14:23:07 +01:00
parent b66cda78b2
commit 4a46161b3f
1 changed files with 13 additions and 15 deletions
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28
cpukit/score/cpu/riscv/include/rtems/score/cpu.h
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@@ -193,21 +193,19 @@ static inline bool _CPU_ISR_Is_enabled( unsigned long level )
static inline void _CPU_ISR_Set_level( uint32_t level )
{
if ( ( level & CPU_MODES_INTERRUPT_MASK) == 0 ) {
__asm__ volatile (
".option push\n"
".option arch, +zicsr\n"
"csrrs zero, mstatus, " RTEMS_XSTRING( RISCV_MSTATUS_MIE ) "\n"
".option pop"
);
} else {
__asm__ volatile (
".option push\n"
".option arch, +zicsr\n"
"csrrc zero, mstatus, " RTEMS_XSTRING( RISCV_MSTATUS_MIE ) "\n"
".option pop"
);
}
/*
* Where CPU_ENABLE_ROBUST_THREAD_DISPATCH == TRUE, the only supported
* interrupt level allowed to set is 0 (interrupts enabled). This constraint
* is enforced by the API level functions which return an error status for
* other interrupt levels.
*/
(void) level;
__asm__ volatile (
".option push\n"
".option arch, +zicsr\n"
"csrrs zero, mstatus, " RTEMS_XSTRING( RISCV_MSTATUS_MIE ) "\n"
".option pop"
);
}
uint32_t _CPU_ISR_Get_level( void );