Dynamically mapped blocks must be aligned to the MMU page size just like
startup-configured blocks. This was not being enforced and could cause a
hang with bad input.
Rename xilinx_zynqmp_rpu BSP variant to zynqmp_rpu_lock_step to
emphasize that this BSP is for the lock-step mode RPU configuration.
Add BSP variants zynqmp_rpu_split_0 and zynqmp_rpu_split_1 for the split
mode RPU configuration for core 0 and 1 respectively.
Remove copyright from DornerWorks since the files contain not contributions
from this company. Fix the copyright years of the embedded brains
contributions.
Add support for the BSP_ARM_GIC_MULTI_PROCESSOR_SECONDARY build option
for the GICv2 support. This option is useful for multiprocessor systems
without SMP support.
Do not wait in the individual _CPU_SMP_Start_processor() for the
secondary processor. Wait for all of them in
_CPU_SMP_Finalize_initialization() before the L2 cache is enabled.
There is no need to wait for the secondary processor in
_CPU_SMP_Start_processor() since _CPU_SMP_Finalize_initialization() does
nothing.
The caller of _CPU_SMP_Start_processor() ensures that we do not start
the current processor.
Remove copy and paste from the arm SMP support. The shared aarch64
implementation of rtems_cache_enable_data() does not enable a particular
cache, it just enables the C bit in the SCTLR_EL1. This is already done
in aarch64_mmu_enable(). There is no need to wait for secondary
processors in _CPU_SMP_Start_processor().
Calls from Thumb code into ARM code require the use of a BLX instruction
and an optional offset prefix instruction. The BLX instruction encoding
requires that the least significant bit be 0 in all cases while the BL
instruction for Thumb-to-Thumb calls includes that bit as part of the
offset. This ensures that bit 0 of the BLX is set to 0 as required by
the instruction encoding specification.
Fix _CPU_SMP_Get_current_processor(), since read from register MPIDR_EL1
(the least significant byte) is not always right,for example the least
significant byte of MPIDR_EL1 is always zero for cortex-a55.
aarch64 has a thread ID register TPIDR_EL1 available for for OS management
purposes. RTEMS stores per-CPU control in TPIDR_EL1 when the core startup,
so we can use _Per_CPU_Get_index() to get current processor index.
update #5064
