Resurrect proper file comment. Order copyrights according to template. Remove
white space at the end of line. Do error checks early. Define objects under
optional extern "C".
Update #5047.
Modified the body of lio_listio(), to make sure it return -1 and sets
errno to ENOSYS, when RTEMS_POSIX_API is not defined.
The psxenosys test has been modified to test for lio_listio() only
when RTEMS_POSIX_API is not defined. In the test all the puts() have
been removed. If kept they would have made the output of the test depending
on the build configuration, making the content of psxenosys.scn inconsistent.
Removing the puts() makes the .scn file valid regardless of the build
configuration.
Additionally, rtems_aio_notify() in aio_misc.c has been modified,
simplifying it and reducing the part inside the ifdef.
Closes#5125
This adds support for the 6 SPI interfaces on the STM32H7 series chips
with an initial example for the stm32h750b discovery kit development
board. Configuration is similar to existing peripherals. Chip select
lines are software-controlled since the SPI peripheral only supports a
single hardware-controlled chip select line. This implementation does
not use interrupts.
This reverts commit d81bf04501.
The commit is reverted as this is only partial solution and remaining part
to fix properly is extremely hard and usually done in completely diffetrent
way. Hence let's not enforce compiler but rather enforce RTEMS/H7 users.
This commit adds support for lio_listio().
psxaio05 has been added to test the new method.
To avoid code duplication, the body of aio_read and aio_write has been
moved in two helper methods. In this way i can use it also in lio_listio().
In addition to that, a limit on the number of total aio operation enqueued
has been added.
Updates rtems/programs/gsoc#29
This offset is already accounted for by Stack_check_Usable_stack_start()
called from Stack_check_Visit_stack() and adding it a second time can
cause interaction beyond the bounds of the stack.
The default exception handler uses the Save Program Status Register
(SPSR), however, if _ARMV4_Exception_reserved_default() would get
called, the state of this register is unpredictable. Replace potential
calls to _ARMV4_Exception_reserved_default() with an undefined
instruction.
Add BSP option BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0 to customize the ARM
GIC support. Enable this option for arm/altera-cyclone-v and
arm/xilinx-zynq BSPs by default.
The EOZ9 RTC has a similar register interface like the MCP7940M (and
quite some other I2C RTCs). This commit:
* Extracts the generic parts from MCP7940M and moves it into a generic
i2c-rtc driver.
* Uses the new i2c-rtc for the MCP7940M.
* Uses the new i2c-rtc for the new Abracom EOZ9.
Add support to configure the second region of DDR memory if the
BSP configured RAM size is greater than 2G.
Add the second region's memory to the heap.
This follows current conventions.
Two have been left behind for now until we decide what to do as they are
imports.
* cpukit/compression/xz/COPYING
* cpukit/libmisc/uuid/COPYING
Add filename length checks to prevent the creation of files and folders
that cannot be listed, unlinked or renamed by subsequent calls.
These changes are sufficient to make the jffs2fsrenamelongname and
jffs2nandfsrenamelongname testcases pass.
Updates #5073
Currently, if a BSP is built without MPU alignment enforcement, the MPU
is still enabled and can produce a non-functional binary since code can
be mixed with data within a memory region and memory regions are marked
as read-only or no-execute based on section addresses and sizes leading
to overlapping regions being defined which causes the later-defined
region to take precedence. This change disables the MPU when alignment
is not enforced, allowing the binary to function.
In _Terminate(), everything after invoking the fatal extensions is essentially
dead code. Simplify this code block and provide a reasonable safe fall-back
for badly configured applications. Just disable masked interrupts and execute
an idle loop.
Update #5067.
