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Author SHA1 Message Date
Sebastian Huber
56b0387d2f bsp/riscv: Add NS16750 support to console driver 
Update #3433.
 2018-08-01 11:15:14 +02:00
Sebastian Huber
a7cd4b737c serial/ns16550: Precision clock synthesizer 
Set the FIFO control register while DLAB == 1 in the line control
register.  At least on the QorIQ T4240 the driver still works with the
re-ordered FIFO control register access.
 2018-08-01 11:13:58 +02:00
Sebastian Huber
8a78b784c4 serial/ns16550: Use standard register names 
Use the standard register names for the divisor latches.  This makes it
easier to compare the code with other driver implementations.
 2018-08-01 10:08:59 +02:00
Sebastian Huber
529154bad2 bsp/riscv: Initialize FPU depending on ISA 
Initialize fcsr to zero for a defined rounding mode.

Update #3433.
 2018-08-01 10:08:59 +02:00
Sebastian Huber
48cbd63c84 bsp/riscv: Fix clock driver 
Do not assume that mtime is zero at boot time.

Update #3433.
 2018-08-01 10:07:18 +02:00
Sebastian Huber
71284ce893 bsps/sparc: Fix typo in start.S 
Fix typo in start.S introduced by
4678d1a8b0.
 2018-08-01 10:07:18 +02:00
Sebastian Huber
d906ce30c6 libtests: Use CONFIGURE_INIT_TASK_TABLE_SIZE 
Using CONFIGURE_MINIMUM_TASK_STACK_SIZE increases also the interrupt
stack size.  This is an issue on some BSPs.  Use
CONFIGURE_INIT_TASK_TABLE_SIZE instead.

Update #3433.
 2018-07-30 08:06:23 +02:00
Sebastian Huber
334e1d22f5 confdefs: Fix uniprocessor configuration 
Introduce a new internal define _CONFIGURE_MAXIMUM_PROCESSORS and ensure
that it is _CONFIGURE_MAXIMUM_PROCESSORS > 1 only in SMP configurations.

This avoids to allocate data structures for non-existing additional
processors in uniprocessor configuration.

Update #3459.
 2018-07-30 08:06:18 +02:00
Sebastian Huber
44c2d393bd bsp/riscv: Fix inter-processor interrupts 
The previous version worked only on a patched Qemu.  Writes to mip are
illegal according to the The RISC-V Instruction Set Manual, Volume II:
Privileged Architecture, Privileged Architecture Version 1.10.

Update #3433.
 2018-07-27 15:06:55 +02:00
Sebastian Huber
cfc95736ff riscv: Rework CPU counter support 
Update #3433.
 2018-07-27 15:06:55 +02:00
Sebastian Huber
65f52d0060 samples/minimum: Use default interrupt stack size 
Update #3433.
 2018-07-25 11:26:26 +02:00
Sebastian Huber
581a0f8866 bsp/riscv: Use interrupt driven NS16550 driver 
Update #3433.
 2018-07-25 10:07:44 +02:00
Sebastian Huber
adede135e7 bsp/riscv: Add PLIC support 
Update #3433.
 2018-07-25 10:07:44 +02:00
Sebastian Huber
bd5603868a bsp/riscv: Add simple SMP support to clock driver 
This is a hack.  The clock interrupt should be handled by each hart.

Update #3433.
 2018-07-25 10:07:44 +02:00
Sebastian Huber
6552ba8c37 bsp/riscv: Use CPU counter btimer 
Update #3433.
 2018-07-25 10:07:44 +02:00
Sebastian Huber
447fd894ae bsp/riscv: Add basic SMP startup 
Update #3433.
 2018-07-25 10:07:44 +02:00
Sebastian Huber
6b9ef097c3 riscv: Add CLINT and PLIC support 
The CLINT and PLIC need some per-processor state.

Update #3433.
 2018-07-25 10:07:43 +02:00
Sebastian Huber
c2670deb49 riscv: Use wfi instruction for idle task 
Update #3433.
 2018-07-25 10:07:43 +02:00
Sebastian Huber
f5fd8eb9e3 bsps/riscv: Update linker-symbols.h 
Update #3433.
 2018-07-25 10:07:43 +02:00
Sebastian Huber
dda6e06edb bsp/riscv: Add reset via for SiFive Test Finisher 
Update #3433.
 2018-07-25 10:07:43 +02:00
Sebastian Huber
3a263a9b02 bsp/riscv: Add and use riscv_fdt_get_address() 
Update #3433.
 2018-07-25 10:07:43 +02:00
Sebastian Huber
791d9ac5c3 bsp/riscv: Disable HTIF support by default 
The HTIF is a legacy machinery.

Update #3433.
 2018-07-25 10:07:43 +02:00
Sebastian Huber
7fe48551a2 bsp/riscv: Fix HTIF warnings 
Update #3433.
 2018-07-25 10:07:43 +02:00
Sebastian Huber
8db3f0e878 riscv: Rework exception handling 
Remove _CPU_ISR_install_raw_handler() and _CPU_ISR_install_vector()
functions.  Applications can install an exception handler via the fatal
error handler to handle synchronous exceptions.

Handle interrupt exceptions via _RISCV_Interrupt_dispatch() which must
be provided by the BSP.

Update #3433.
 2018-07-25 10:07:43 +02:00
Sebastian Huber
5694b0cce4 riscv: New CPU_Exception_frame 
Use the CPU_Interrupt_frame for the volatile context.  Add non-volatile
registers and extra state on top of it.

Update #3433.
 2018-07-25 10:07:43 +02:00
Sebastian Huber
d779a1e228 riscv: Add exception codes 
Update #3433.
 2018-07-25 10:07:42 +02:00
Sebastian Huber
56778835b6 score: _SMP_Inter_processor_interrupt_handler() 
Optimize _SMP_Inter_processor_interrupt_handler() for the common case in
which the inter-processor interrupt is only used to trigger a thread
dispatch.
 2018-07-25 10:07:42 +02:00
Sebastian Huber
a1f7d7d430 score: RTEMS_PREDICT_TRUE(), RTEMS_PREDICT_FALSE() 
Add RTEMS_PREDICT_TRUE() and RTEMS_PREDICT_FALSE() for static branch
prediction hints.

Close #3475.
 2018-07-25 10:07:42 +02:00
Sebastian Huber
406dd62c99 _SMP_Start_multitasking_on_secondary_processor() 
Pass current processor control as first parameter to make dependency
more explicit.
 2018-07-25 10:07:42 +02:00
Sebastian Huber
4678d1a8b0 bsps: bsp_start_on_secondary_processor() 
Pass current processor control as first parameter in
bsp_start_on_secondary_processor() and qoriq_start_thread() to make
dependency more explicit.
 2018-07-25 10:07:42 +02:00
Sebastian Huber
0d362ff397 score: _SMP_Inter_processor_interrupt_handler() 
Pass current processor control via parameter since it may be already
available at the caller side.
 2018-07-25 10:07:42 +02:00
Sebastian Huber
f8d00a3f19 tm27: Fix prototype warnings 2018-07-25 10:07:42 +02:00
Sebastian Huber
05259de1c9 powerpc: Fix _CPU_Instruction_illegal() 
Apparently the .word assembler directive is not the right thing on this
target.
 2018-07-25 10:07:42 +02:00
Sebastian Huber
caccc5bfc6 bsps: Fix function declaration warnings 2018-07-24 13:00:56 +02:00
Sebastian Huber
91f39a5587 smptests: Fix format warnings 2018-07-24 13:00:56 +02:00
Sebastian Huber
bf199e0c33 block05: Remove unused variable 2018-07-24 13:00:56 +02:00
Sebastian Huber
bded3f05f8 psxthreadname01: Fix out of bounds memory access 2018-07-24 13:00:55 +02:00
Sebastian Huber
001b9925fc psxtimer02: Fix parameter type cast 2018-07-24 13:00:55 +02:00
Sebastian Huber
f133386ac8 sptests/sp20: Remove unused variable 2018-07-24 13:00:55 +02:00
Sebastian Huber
c192109f72 samples: Fix warnings 2018-07-24 10:06:49 +02:00
Sebastian Huber
61c51dbb18 bsp/beagle: Fix warnings 2018-07-24 09:11:08 +02:00
Sebastian Huber
3a646426aa score: Add _CPU_Instruction_illegal() 
On some architectures/simulators it is difficult to provoke an
exception with misaligned or illegal data loads.  Use an illegal
instruction instead.

Update #3433.
 2018-07-23 14:14:04 +02:00
Sebastian Huber
b74353ef9c score: Add _CPU_Instruction_no_operation() 
This helps to reduce the use of architecture-specific defines throughout
the code base.
 2018-07-20 09:11:05 +02:00
Sebastian Huber
42f2fdfd4e score: Move context validation declarations 
The context validation support functions _CPU_Context_validate() and
_CPU_Context_volatile_clobber() are used only by one test program
(spcontext01).  Move the function declarations to the CPU port
implementation header file.
 2018-07-20 09:11:05 +02:00
Sebastian Huber
248ca7ad40 score: Remove obsolete CPU port defines 2018-07-20 09:11:05 +02:00
Sebastian Huber
1554a8c517 dtc: Update VERSION 2018-07-20 08:52:37 +02:00
Sebastian Huber
ec2de39666 libfdt: fdt_address_cells() and fdt_size_cells() 
Add internal fdt_cells() to avoid copy and paste.  Test error cases and
default values.  Fix typo in fdt_size_cells() documentation comment.

Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
 2018-07-20 08:52:36 +02:00
Sebastian Huber
513daa3fa5 capture: Include missing header file 2018-07-19 13:07:14 +02:00
Sebastian Huber
b4f15d8e3b jffs2: Rename README to VERSION 
This makes it easer to find files describing an upstream version, e.g.
via "find -name VERSION".

Update #3465.
 2018-07-19 07:11:34 +02:00
Sebastian Huber
2af004eb0a dtc: Add VERSION file 
Close #3471.
 2018-07-19 07:01:12 +02:00