In addtion to 1023, the GICC_IAR register may return 1022 as a special value.
Simply check for a valid interrupt vector for the dispatching.
Check the GICC_IAR again after the dispatch to quickly process a next interrupt
without having to go through the interrupt prologue and epiloge.
Device trees allow mixing different kinds of GPIOs in one property. For
that it is usefull to only provide a pointer to an arbitrary location in
the property and initialize a GPIO from that.
CAVEAT: license change from BSD to Apache2 license!
Explanation:
The imported files come from CMSIS v5 project available on:
https://github.com/ARM-software/CMSIS_5/tree/develop
The files imported are located inside the CMSIS/Core/Include
project sub-directory.
The project does not provide any NOTICE file in its root directory nor
in the directory of the imported files.
The NOTICE file and its usage in the Apache 2 license was/is
so far the only issue mentioned in discussion of RTEMS developers/users
when considering inclusion of the code under Apache 2 license
into the RTEMS project.
Since the CMSIS v5 project is free from this legal hinder, we may freely
use it and update files to the latest version.
Technical: the patch replaces code from 2015 with the latest version
which brings quite a lot of bug fixes and most importantly opens
possibilities to support MCUs based on new ARM cores.
Set the VBAR to the vector table in the start section before
bsp_start_hook_0() is called to earlier handle exceptions in RTEMS.
Set the VBAR to the normal vector table in start.S for the main
processor. Secondary processors set it in bsp_start_hook_0().
Update #4202.
Add a workaround for Cortex-A9 Errata 845369: A short loop including a DMB
instruction might cause a denial of service on another which executes a CP15
broadcast operation.
Close#4115.
Add a workaround for Cortex-A9 Errata 845369: Under Very Rare Timing
Circumstances Transition into Streaming Mode Might Create Data Corruption.
Update #4115.
This adds support for the GICv3 interrupt controller along with the
redistributor to control SGIs and PPIs which wasn't present in GICv2
implementations. GICv3 implementations only optionally support
memory-mapped GICC interface interaction and require system register
access be implemented, so the GICC interface is accessed only
through system registers.
The imx BSP contained a hack to change the workspace entry of the MMU
table. This makes the used define visible for other BSPs too so that the
same hack can be used for example in raspberry pi too.
The small page MMU support reduces the granularity for memory settings
through the MMU from 1MiB sections to 4KiB small pages.
Enable it by default on the realview_pbx_a9_qemu BSP.
The old driver worked well for EEPROMS with the RTEMS EEPROM driver. But
it had problems with a lot of other situations. Although it's not a
direct port, the new driver is heavily modeled after the FreeBSD ti_i2c
driver.
Closes#3764.
The following variants
* GICv1 with Security Extensions,
* GICv2 without Security Extensions, or
* within Secure processor mode
have the ability to assign group 0 or 1 to individual interrupts. Group
0 interrupts can be configured to raise an FIQ exception. This enables
the use of NMIs with respect to RTEMS.
BSPs can enable this feature with the BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0
define. Use arm_gic_irq_set_group() to change the group of an
interrupt (default group is 1, if BSP_ARM_GIC_ENABLE_FIQ_FOR_GROUP_0 is
defined).
