This fixes a logic inversion that was preventing creation of a Bad Block
Table (BBT) from scratch on devices that lack one. This was discovered
during upstream integration testing. The BBT management layer in this
driver is not designed to be easily testable other than on real hardware.
Stacked mode doubles the number of sectors and device size while
parallel mode doubles the sector size and the device size. Make sure
that this is accounted for in the device size accessor.
This cleans up outputUsesInterrupts usage with rtems_termios_device_mode
enum values. The outputUsesInterrupts member was typed as an int, named
as if it were a boolean value, and used as if it were a
rtems_termios_device_mode enum. In this patch, values assigned to
outputUsesInterrupts have been converted to the corresponding
rtems_termios_device_mode enum value, conversions from
deviceOutputUsesInterrupts have been made explicit, and uses of
rtems_termios_device_mode enum values with deviceOutputUsesInterrupts
have been converted to booleans.
Expose functions to directly manipulate the bad block table (BBT). These
functions are necessary to correct possible BBT corruption caused by
bugs in the BBT management layer.
The XNandPsu_EraseBlock function takes a target device and a block
offset for erasure. Ensure the block offset is within the size of the
target device.
When marking the trailing blocks on a device as reserved for Bad Block
Table usage, ensure that the correct blocks are marked. This resolves an
off-by-one error that was marking one block too low and leaving the last
block in the device unmarked.
The Bad Block Table is a per-device catalog of the dispositions of each
block in the device. Only read enough data to determine the dispositions
of blocks for the device being read.
The xnandpsu driver includes functionality to map back and forth between
the flash-based BBT and the memory-based BBT with the values in each
being a bitwise inversion of each other. This resolves several bugs in
this process and simplifies the inversion from operating on the block
representation to operating on the entire BBT entry (4 blocks, 2 bits
per block, one byte total).
Bugs resolved in XNandPsu_ConvertBbt():
* The calculation of memory BBT entry offset was off by a factor of 4
* The entry offset into the flash BBT has been removed since each flash
BBT directly describes the flash space it is contained within and has
no reference to other devices in the chip
Bugs resolved in XNandPsu_WriteBbt():
* The BBT length calculated was reduced to NumTargetBlocks from
NumBlocks since only the relevant portion of the in-memory BBT should
be written to the flash-based BBT space
* An offset was applied to values retrieved from the in-memory BBT so
that only the relevant portion was converted and written to the
flash-based BBT
The xnandpsu driver conditionally tries to wrap page index to NAND chip
size causing an off-by-one error where the first page of the second chip
is not wrapped correctly. This removes the conditional so that page
index is always wrapped.
On configurations where multiple NAND chips are in use, the erasure
loop in XNandPsu_Erase() can reset the loop counter variable once it
gets to blocks in the second chip causing an infinite loop overwriting
parts of the first chip. This change ensures that the loop counter is
not accidentally reset.
This fixes some issues in the Xilinx support code that are critical to
support the Cortex-R5F cores present in my Xilinx SoCs. The imported
Cortex-R5 xil_cache.c matches the existing information in
bsps/shared/xil/VERSION.
When a buffer is modified by both hardware components such as DMA and by
software components, the buffer cache state must be kept in sync so that
data is not accidentally thrown away during future invalidations.
When polling hardware registers in high performance situations, don't
rely on usleep or other standard sleep functions since they will
necessarily rely on kernel ticks to be woken up. This can easily cause
an immense reduction in throughput.
The changes here ensure correct cache maintenance around DMA operations.
One cache flush was missing and two cache invalidations occurred before
the corresponding read that would make them necessary.
Fixes the following Coverity warning:
** CID 1539495: Integer handling issues (CONSTANT_EXPRESSION_RESULT)
/bsps/shared/dev/rtc/mcp7940m.c: 317 in mcp7940m_set_time()
Basically coverity warns that (buf[...] & 0x7) can't be bigger than 7.
Just remove the unnecessary comparison.
The MCP7940M is a I2C RTC chip. The new driver uses the dev/i2c API to
support the RTC. It is written with the intention, that the driver can
be adapted to other RTCs with a similar register layout by just
replacing the initialization function.
The NOR driver was not written with SMP systems and caching in mind.
This makes the IsBusy flag volatile for updates across cores and
introduces cache flushing and invalidation where necessary for data
manipulated by the DMA engine in the QSPI peripheral.
When given the exact bounds of a sector, the current algorithm
calculates that 3 sectors need to be erased. This corrects the
calculation such that only 1 sector needs to be erased for erasures that
exactly match sector boundaries.
This change causes NOR writes to be broken according to page boundaries.
Writes across page boundaries cause the writes beyond the boundary to
fail silently. This also introduces a new function that will explicitly
write pages.
Add <rtems/termiosdevice.h> which does not depend on <rtems/libio.h> to
provide rtems_termios_device_context and rtems_termios_device_handler.
For polled serial device drivers, this removes a header file dependency
to the full file system support.
If a different chip variant is used in the i.mxrt BSP, a different
header would have to be included. Make sure that the fsl-edma driver
uses a header that doesn't have to be adapted.
The library is imported in minimalist version just to support future
amd64efi BSP.
The FreeBSD tree commit id with imported libefi version is:
ce7b20e5129cf0f269951b313d336a9c7d54d790
This adds helper functions for working with NOR flash connected to the
Xilinx GQSPI controller. The helper functions are based on Xilinx's
QSPIPSU flash interrupt example.
This adds Xilinx's driver for the Xilinx GQSPI controller embedded in
the ZynqMP SoC. Within that device alone, it is possible to access this
peripheral from MicroBlaze, ARMv7, and ARMv8 cores. The imported files
are and should be able to remain unmodified. Import information is kept
in bsps/shared/dev/spi/VERSION.
The address of the nandpsu peripheral is specific to the ZynqMP SoC and
not relevant to other devices that might have one or more instances of
this peripheral.
