ISR locks are low-level locks to protect critical sections accessed by
threads and interrupt service routines.
On single processor configurations the ISR locks degrade to simple ISR
disable/enable sequences. No additional storage or objects are
required.
This synchronization primitive is supported on SMP configurations. Here
SMP locks are used.
Delete _ISR_Enable_on_this_core(), _ISR_Flash_on_this_core(),
_ISR_SMP_Disable(), _ISR_SMP_Enable(), _ISR_SMP_Flash().
The ISR disable/enable interface has no parameter to pass a specific
object. Thus it is only possible to implement a single global lock
object with this interface. Using the ISR disable/enable as the giant
lock on SMP configurations is not feasible.
Potentially blocking resource obtain sequences protected by the thread
dispatch disable level are subdivided into smaller ISR disabled critical
sections. This works since on single processor configurations there is
only one thread of execution that can block. On SMP this is different
(image a mutex obtained concurrently by different threads on different
processors).
The thread dispatch disable level is currently used as the giant lock.
There is not need to complicate things with this unused interface.
If we enter _Thread_Dispatch() then _Thread_Dispatch_disable_level must
be zero. Single processor RTEMS assumes that stores of non-zero values
to _Thread_Dispatch_disable_level are observed by interrupts as non-zero values.
Move the _Thread_Dispatch_set_disable_level( 1 ) out of the first ISR
disabled critical section. In case interrupts happen between the
_Thread_Dispatch_set_disable_level( 1 ) and _ISR_Disable( level ) then
the interrupt will observe a non-zero _Thread_Dispatch_disable_level and
will not issue a _Thread_Dispatch() and we can enter the ISR disabled
section directly after interrupt processing.
This change leads to symmetry between the single processor and SMP
configuration.
The original version is missing void and result is that (*x >> 16) is
optimized to ldh rX,[rY]. But it is not allowed/supported to access
bus/address range used by AITC by other than 32 bit wide accesses
and 16-bit access results in the data abort exception.
The corrected version works on real hardware and is even
more readable.
Signed-off-by: Pavel Pisa <ppisa@pikron.com>
Move implementation specific parts of object.h and object.inl into new
header file objectimpl.h. The object.h contains now only the
application visible API.
Move implementation specific parts of tqdata.h, threadq.h and
threadq.inl into new header file threadqimpl.h. The threadq.h contains
now only the application visible API.
Delete tqdata.h.
Move implementation specific parts of states.h and states.inl into new
header file statesimpl.h. The states.h contains now only the
application visible API.
Move implementation specific parts of thread.h and thread.inl into new
header file threadimpl.h. The thread.h contains now only the
application visible API.
Remove superfluous header file includes from various files.
Move implementation specific parts of prioritybitmap.h and
prioritybitmap.inl into new header file prioritybitmapimpl.h. The
prioritybitmap.h contains now only the application visible API.
Move content of bitfield.h into prioritybitmapimpl.h.
