forked from Imagelibrary/rtems
10b51ae739
If we enter _Thread_Dispatch() then _Thread_Dispatch_disable_level must be zero. Single processor RTEMS assumes that stores of non-zero values to _Thread_Dispatch_disable_level are observed by interrupts as non-zero values. Move the _Thread_Dispatch_set_disable_level( 1 ) out of the first ISR disabled critical section. In case interrupts happen between the _Thread_Dispatch_set_disable_level( 1 ) and _ISR_Disable( level ) then the interrupt will observe a non-zero _Thread_Dispatch_disable_level and will not issue a _Thread_Dispatch() and we can enter the ISR disabled section directly after interrupt processing. This change leads to symmetry between the single processor and SMP configuration.
This is the Real-Time Executive for Multiprocessing Systems (RTEMS). The version number for this software is indicated in the VERSION file. See the documentation manuals in doc/ with daily builds available online at http://rtems.org/onlinedocs/doc-current/share/rtems/html/ and released builds at http://www.rtems.org/onlinedocs/releases/ for information on building, installing, and using RTEMS. The INSTALL file tells you to come back here. See the RTEMS Wiki at http://wiki.rtems.org/wiki/index.php/Main_Page for community knowledge and tutorials. RTEMS Doxygen available at http://www.rtems.org/onlinedocs/doxygen/cpukit/html Get help on the mailing lists: * For general-purpose questions related to using RTEMS, use the rtems-users ml: http://www.rtems.org/mailman/listinfo/rtems-users * For questions and discussion related to development of RTEMS, use the rtems-devel ml: http://www.rtems.org/mailman/listinfo/rtems-devel See http://www.rtems.org/bugzilla/ to report a bug.