The last optimization missed was incorrect in regards to
PSR write instruction delay must be 3 instructions.
New optimizations:
* align to 32-byte cache line.
* rearrange code into three "blocks" of 4 instructions that
is executed by syscall 2 and 3. This is to optimize for
16/32 byte cache lines.
* use delay-slot instruction in trap table to reduce by one
instruction.
* use the fact that "wr %PSR" implements XOR to reduce by
one instruction.
The following BSPs do not have tick support so the tests fail:
arm1136jfs
arm1136js
arm7tdmi
arm920
armcortexa9 (does not run any more)
avrtest
h8sim
h8sxsim
m32csim
m32rsim
moxiesim
simsh1
simsh2
simsh4
v850e1sim
v850e2sim
v850e2v3sim
v850esim
v850essim
v850sim
This list was provided by Joel in the following post:
http://www.rtems.org/pipermail/rtems-devel/2014-April/006526.html
BSPs for simulators which do not include a clock tick interrupt source
are incapable of running some tests successfully. This is a common
characteristic of some BSPs and a fixed set of tests. There is no point
in duplicating this list of tests in those BSPs test configuration.
Read testsuites/testdata/require-tick-isr.tcfg for details.
Add basic support for the Multiprocessor Resource Sharing Protocol
(MrsP).
The Multiprocessor Resource Sharing Protocol (MrsP) is defined in A.
Burns and A.J. Wellings, A Schedulability Compatible Multiprocessor
Resource Sharing Protocol - MrsP, Proceedings of the 25th Euromicro
Conference on Real-Time Systems (ECRTS 2013), July 2013. It is a
generalization of the Priority Ceiling Protocol to SMP systems. Each
MrsP semaphore uses a ceiling priority per scheduler instance. These
ceiling priorities can be specified with rtems_semaphore_set_priority().
A task obtaining or owning a MrsP semaphore will execute with the
ceiling priority for its scheduler instance as specified by the MrsP
semaphore object. Tasks waiting to get ownership of a MrsP semaphore
will not relinquish the processor voluntarily. In case the owner of a
MrsP semaphore gets preempted it can ask all tasks waiting for this
semaphore to help out and temporarily borrow the right to execute on one
of their assigned processors.
The help out feature is not implemented with this patch.
Switch to the standard ARM startup code. This requires adding the
standard interrupt code. The interrupt code does nothing at this
point in time. I do not know if the ARM simulator in GDB supports
interrupts.
Do not use the Per_CPU_Control::started in
_SMP_Start_multitasking_on_secondary_processor() since this field may be
not up to date when a secondary processor reads it. Use the read-only
scheduler assignment instead.
Add a new fatal error SMP_FATAL_MULTITASKING_START_ON_INVALID_PROCESSOR.
This prevents out-of-bounds access.
It is currently not possible to test these fatal errors. One option
would be to fake values of the _CPU_SMP_Get_current_processor(), but
unfortunately this function is inline on some architectures.
The syscall functions overlapped with RTEMS, for example _write, _read, etc.
Change these to be internal to the BSP and avoid any clash with names in
RTEMS. Add support for SWI_Write0.
Change the console driver to use SWI_Write0. This outputs the character
to the host's stdout. Writing to file name 0 is not captured and managed
by GDB's simulation code while the SWI_Write0 is. The managed stdout
data is encapulated in the MI protocol while writes to file handle 0 are
dropped by GDB when in MI mode.
This is a shell script that lists the BSPs in the source tree by
architecture. The BSP name is given plus the relative path to
BSP source files.
The script uses the same hack, ie looking for *.cfg files, as the
build system so it sees what the build system sees.
The exit SPARC system call doesn't have a function entry
point like the others do. This is probably why people use
TA 0x0 instruction directly for shutting down the system.
The same smp fatal code is used in percpu
_Per_CPU_State_change(). In order to determine which CPU
requested a fatal shutdown and which CPU responds to it a
unique code should be used.
A unique code makes it also possible to handle the CPUs
differently in the fatal exception handler.
Avoid using newlib's gmtime_r call which fails with a max signed int.
Add an RTEMS specific version for 1/1/1988 to 31/12/2100.
Update sp2038 to test every day from 1/1/1988 to 31/12/2100. Only days
need be tested as the code splits the seconds based on days.
Enable usage of _Thread_Set_life_protection() in thread dispatch
critical sections. This can be used to enable the thread
life-protection with thread dispatching disabled and then enable thread
dispatching.
Extract code from _Scheduler_SMP_Enqueue_ordered() and move it to the
new function _Scheduler_SMP_Enqueue_scheduled_ordered() to avoid
untestable execution paths.
Add and use function _Scheduler_SMP_Unblock().
This function is only used by _Thread_Change_priority(). Make it static
to avoid the function call overhead in the performance critical function
_Thread_Change_priority().
The function to change a thread priority was too complex. Simplify it
with a new scheduler operation. This increases the average case
performance due to the simplified logic. The interrupt disabled
critical section is a bit prolonged since now the extract, update and
enqueue steps are executed atomically. This should however not impact
the worst-case interrupt latency since at least for the Deterministic
Priority Scheduler this sequence can be carried out with a wee bit of
instructions and no loops.
Add _Scheduler_Change_priority() to replace the sequence of
- _Thread_Set_transient(),
- _Scheduler_Extract(),
- _Scheduler_Enqueue(), and
- _Scheduler_Enqueue_first().
Delete STATES_TRANSIENT, _States_Is_transient() and
_Thread_Set_transient() since this state is now superfluous.
With this change it is possible to get rid of the
SCHEDULER_SMP_NODE_IN_THE_AIR state. This considerably simplifies the
implementation of the new SMP locking protocols.
