forked from Imagelibrary/rtems
d6f1ec91b6
The last optimization missed was incorrect in regards to PSR write instruction delay must be 3 instructions. New optimizations: * align to 32-byte cache line. * rearrange code into three "blocks" of 4 instructions that is executed by syscall 2 and 3. This is to optimize for 16/32 byte cache lines. * use delay-slot instruction in trap table to reduce by one instruction. * use the fact that "wr %PSR" implements XOR to reduce by one instruction.
This is the Real-Time Executive for Multiprocessing Systems (RTEMS). The version number for this software is indicated in the VERSION file. See the documentation manuals in doc/ with daily builds available online at http://rtems.org/onlinedocs/doc-current/share/rtems/html/ and released builds at http://www.rtems.org/onlinedocs/releases/ for information on building, installing, and using RTEMS. The INSTALL file tells you to come back here. See the RTEMS Wiki at http://wiki.rtems.org/wiki/index.php/Main_Page for community knowledge and tutorials. RTEMS Doxygen available at http://www.rtems.org/onlinedocs/doxygen/cpukit/html Get help on the mailing lists: * For general-purpose questions related to using RTEMS, use the rtems-users ml: http://www.rtems.org/mailman/listinfo/rtems-users * For questions and discussion related to development of RTEMS, use the rtems-devel ml: http://www.rtems.org/mailman/listinfo/rtems-devel See http://www.rtems.org/bugzilla/ to report a bug.