When compiling the lwIP port for the TMS570, there
were issues with the BSP. Headers are expected in a folder
named ti_herc which did not exist. This fixes the issue.
Furthermore, there were multiple warnings about define redefinitions.
This was fixed as well.
These patches were submitted a few months ago, but it was found out
that the default-by-family: [] were missing in the GPIO .yml lines.
This was fixed in this patch.
This patch accounts for different pins for the ETH peripheral
on STM32H7 devices. For example, the Nucleo H743ZI has slightly
different pins than other STM32H7 boards.
Prefer RTEMS_FATAL_SOURCE_EXCEPTION over
INTERNAL_ERROR_ILLEGAL_USE_OF_FLOATING_POINT_UNIT since the fatal code
(rtems_exception_frame) provides more context.
Fully support the interrupt extension API to set/get the interrupt affinity.
Remove LEON3_irq_to_cpu which defined the interrupt to processor mapping in a
BSP-specific way.
Update #3269.
Skip the data cache initialization if we are a secondary processor.
The bug was introduced by e164df5e33 and
did not show up in tests using Qemu since the data cache behaviour is
not emulated.
Calling the memory FLASH and EXTRAM instead of FLEXSPI and SDRAM makes
it simpler to support other types of external RAM. This patch also
removes some of the calculations and improves names and documentation to
avoid pitfalls. It removes a unnecessary memory definition.
Update #4180
This reverts commit 10041a4cfc.
This type of configuration does not belong in RTEMS and is better
constrained to libbsd where the defines are actually being used.
The fix to address CID 1399742 (NO_EFFECT) in commit
f8b6359415 introduced a bug since
LEON3_IrqCtrl_EIrq == -1 in case no extended interrupts are supported by
the interrupt controller. Fix this by checking for
LEON3_IrqCtrl_EIrq > 0.
In addition, interrupt number 0 is reserved and should not be used.
The GICv3 support is shared between AArch32 and AArch64. For AArch32,
the new AARCH64_IS_NONSECURE is never defined. Use ARM_MULTILIB_ARCH_V4
instead.
This issue was introduced by 76c6caad52.
There is still a change in bsp_interrupt_vector_enable() for AArch32
compared to the version before 76c6caad52.
The existing fix for the ZynqMP UART hardware bug only caught the vast
majority of instances where it could occur. To fully fix the data
corruption, this fix must be applied after every baud rate change. This
makes the logic reset and kick apply in any locations where the baud
rate could be changed.
The Cortex-R52 does not support cache coherency and the shareable memory
attribute. If a region is configured to be shareable, then it falls
back to use non-cacheable memory.
Update #4202.
Provide the options necessary to enable any combination of CGEM ethernet
interfaces in LibBSD. The default is still CGEM3, so this should
continue to operate as expected on typical Zynq Ultrascale+ MPSoC
development hardware.
