This moves the management console implementation into its own file so
that BSPs which do not need it do not carry the code around with them.
Closes#5120
This adds generic JFFS2 interworking code that allows JFFS2 to be used
on top of any flashdev backend. It currently only supports NOR flashdev
backends.
Accesses to the L2C registers performed by the L2C driver are now
serialized with spin locks. This avoids concurrent access to the L2C
registers by multiple processors. Proposed by GRLIB-TN-0021.
Update #4925.
This updates the implementation of the LEON3 processor power-down
function.
It now contains the workaround for the GR712RC power-down errata
described in GR712RC-UM, version 2.16, section 1.7.8. The workaround is
compatible with other LEON3/LEON4 components.
Update #4875.
The two RTCs supported by that driver (MCP7940M and EOZ9) use slightly
different register order. Add support for a different order to the
i2c-rtc driver.
The devfg driver loads the PL with a bitfile image. The driver can also
support scrubbing.
These drivers are from Patrick Gauvin <pggauvin at gmail.com> and a thread
on the devel list: https://lists.rtems.org/pipermail/devel/2017-May/017705.html
When using QEMU configurations that support SMP for Zynq7000 systems,
the second core is started at the same time as the first core instead of
waiting for an event to trigger a check for the value at 0xfffffff0
before jumping into RTEMS code. This makes the erroneously started core
wait as expected and prevents prefetch and data aborts from occurring
before the MMU has been properly configured. This was recently exposed
by cleanup done to the ARM GICv2 driver that removed some delays which
were allowing this to operate normally.
The RT_TSW_OK field is set to 1 if there was no error. The Message Error
(ME) field indicates an error and must be set to 0 if there was no error
so the result of tsw&RT_TSW_OK must be negated. It is then left-shifted
to the Messsage Error (ME) bit field of the message information word.
Fix issue CID 1399772
This removes the headers imported from the embeddedsw repository in
favor of a much thinner shim. This also removes the complicated build
system configuration necessary to support use of these headers. The
primary reason for removal is that certain external Xilinx libraries
also require use of these headers and this causes version mismatches and
header conflicts that can be avoided.
- Add support for four new ports, UART2-UART5.
- Add build options to allow console device configuration.
- Segregate device-specific definitions from the device family files. X macros
are used to maintain a single source of truth and have the configuration
done at compile-time
- Add raspberrypi_uart_init() to make it convenient for users to install uart
devices
Close#5130
Co-authored-by: Ning Yang <yangn0@qq.com>
* It is not granted that we will always access to natually aligned
access. So, before handling endianess do byte-a-byte load using
the appropriate libfdt function to avoid unaligned access issues
Signed-off-by: Francescodario Cuzzocrea <bosconovic@gmail.com>
On other targets, the rtems_cache_flush_entire_data() also performs a
clean and invalidate.
This is a workaround for "Answer 68874 - Zynq UltraScale+ MPSoC, APU -
An Eviction Might Overtake A Cache Clean Operation".
Let the caller provide the translation table base and the used page
tables to ease testing.
Simplify the error handling by using early returns.
Return RTEMS_TOO_MANY instead of RTEMS_NO_MEMORY if the page tables are
all used.
