This zlib source is a hacked down version just for the decompression
phase for the bootloader used by this family of BSPs. The proper
fix is to redo the hackery with a new version of zlib. But that
is risky so this is just addressing the warnings.
Updates #5276
GCC 14 generates an error for the wrong signature function being
passed in. The underlying type was a void * so adjusting the
signature of the ISR handler was not an option. Added cast.
Closes#5272
Provide missing GCC atomics helpers as part of BSPs where GCC
does not know how to provide it since the CPU's ISA has no
atomic instructions. The implementation provided in
bsps/shared/atomics/__atomic_test_and_set.c should work
on any single core CPU.
The BSPs that need thie function tend to have older cores. This
is the list of BSPs:
arm - csb336, csb337, csb637, edb7312, gumstix, kit637_v6, lpc24xx_ea,
lpc24xx_ncs_ram, lpc24xx_ncs_rom_ext, lpc24xx_ncs_rom_int,
lpc24xx_plx800_ram, lpc24xx_plx800_rom_int, lpc32xx_mzx,
lpc32xx_mzx_stage_1, lpc32xx_mzx_stage_2, lpc32xx_phycore,
rtl22xx, rtl22xx_t, smdk2410
m68k - av5282, mcf5329
mips - jmr3904
moxie - moxiesim
nios2 - nios2_iss
riscv - grv32i, grv32im, niosvc10lp, noel32im, rv32i, rv32im,
sparc - ut699
Applied suggested formatting changes to the following files which
were modified for technical reasons in the previous commit.
bsps/powerpc/gen5200/include/tm27.h
bsps/powerpc/mvme5500/include/tm27.h
bsps/powerpc/psim/include/tm27.h
The gen5200, mvme5500, and psim BSP families had an implementation of
tm27.h which used stub functions with casts as null handlers to fill
in the IRQ structure. The IRQ structure as also missing a field. The
change was to use a set of appropriately signatured stub functions
and correct the structure initialization.
This code likely has produced warnings for a long time but with
GCC 14, these warnings turned into errors.
Closes#5266
This updates the AArch64 Raspberry Pi BSP to use the watchdog to perform
the system reset instead of attempting to use the PSCI reset which isn't
present on the Raspberry Pi platform.
* Cleaned up the uC5282 ISR stuff to make the casts and whatnot more
readable. Also made the offsets relative to the VBR (which is at 0x0
for this BSP) to silence a GCC warning.
* Refactored the default exception handler to map a struct to the stack
instead of taking the address of pc and under-indexing it. The
compiler was not particularly happy about the previous implementation.
_SMP_Processor_configured_maximum is 32 bit, LREG macro is ld on rv64,
lw on rv32. Changing the load to explicit 'lw' to always load 4 bytes
Closes#5251
There are only the 3 names in our entire source that use non-ASCII characters.
Our documentation can still use any type of character. We want to limit source
to ASCII for safety reasons.
board_memories: WINDOWS-1250
aes.c: ISO-8859-3
sdramc.c: WINDOWS-1250
These have been converted to utf-8 with the broken characters fixed. The
original encoding is wrong and has been corrupted. Now they are ASCII.
The GICD_IROUTER register technically starts at offset 0x6000, but the
first 32 IRQ entries are reserved making IRQ 32's entry at 0x6100 the
first usable entry. This register is not currently used, so only a
comment is added to that effect.
Closes#5223
The Motorola MC68040 did not completely implement IEEE754 in hardware.
The FPSP code was required to complete the support. With no more
MC68040 BSPs in RTEMS, this code can be removed.
Updates #5031
An extern for the linker symbol _ttbl_base was declared incorrectly
and gcc reported an overwrite of the four byte area by 16K. Switched
to using the standard linker symbol macros and the warning was
removed.
This is an update of many lingering embedded brains GmbH licenses from
the RTEMS License to the 2-BSD license where possible depending on the
joint copyrights.
Updates #3053.
This is an update of IMD (precursor to embedded brains) licenses from
the RTEMS License to the 2-BSD license where possible depending on the
joint copyrights.
Updates #3053.
For example, with edge triggered external interrupts we may see spurious
interrupts. Ignore them instead of issuing a fatal error.
Use eieio to synchronize access to the IACK and EOI registers.
Use a loop to immediately services the next pending interrupt without
having to go through the exception epiloge and prologue.
Close#5172.
