removed all set_vector() function prototypes from
all the respective bsp.h header files and removed
bsps/shared/start/setvec.c from respective .yml files.
* Fixes#5256.
* Specify an initial baud rate to use during startup.
After the PL011 code refactor in
0f42153959, an initial baud rate
is required. arm_pl011_first_open is called from boot_card and
will fail without a baud rate specified. This can cause certain
future uses of /dev/console, such as opening a shell, to fail.
The rtems_interrupt_disable macros expand to some code that
is indented. GCC sees this as misleading indentation next
to the while loop without braces.
The macro Install_tm27_vector() included an extern for tm27IrqData
inside the scope of the macro. This generated a "nested extern
declaration warning. Moved the extern outside the scope.
The PowerPC has both 32 and 64 bit CPUs within a single architecture
and collection of BSPs. This change set addresses cases where the
format specifier, type, or cast was not correct or portable across
32 and 64 bit environments.
This refactors the AArch64 exception handling to remove the mutable code
sections that are generally flagged as a bad idea by code analysis
tools. This also removes any casting between data pointers and function
pointers to avoid the need to use pragmas to disable warnings about such
casting.
This adds support for a the Image header protocol similar to the zImage
protocol that Linux kernels use to describe their expectations of the
system configuration.
The AArch64-specific timer selection mechanism was using the wrong macro
for selecting the timer interrupt and would therefore partially ignore
configurations that selected the use of virtual timers. The virtual
timer will now be used correctly when selected.
The functions lpc24xx_uart_set_register() and
lpc24xx_uart_set_register() were unused if all of the
feature macros LPC24XX_CONFIG_CONSOLE and LPC24XX_CONFIG_UART_[123]
were undefined.
lpc32xx_mlc_write_blocks() had a different prototype in the header
from the implementation. Changed to match the prototype and Doxygen.
LPC32XX_SCRATCH_AREA_SIZE was tested with "ifdef" not "if" which
resulted in it being used as an array size when undefined or
set to 0.
This header file defines multiple empty structures which are
reported as errors by the test spstdc17 using GCC 15. Added an element
named "unused" to each structure. The macro LPC32XX_FILL() was
checked to ensure it handles the modified structure correctly.
Closes#5295.
Removed all uses and implementations of set_vector() function across ERC32,
LEON2, and LEON3 BSPs. Replaced with rtems_interrupt_handler_install() and
rtems_interrupt_entry_install().
- Added ERC32_Clear_and_unmask_interrupt() and LEON_Clear_and_unmask_interrupt()
for unmasking logic previously in set_vector().
- Deleted set_vector() definitions and implementations in each BSP.
- Updated related obj.yml files.
- Replaced set_vector() with rtems_interrupt_catch() in shared/gnatcommon.c.
This BSP supports a custom STM32U5 based board. It uses a similar
structure like the existing STM32H7 BSP and therefore should be well
adaptable to other boards.
Co-authored-by: Christian Mauderer <christian.mauderer@embedded-brains.de>
Include armv7m_cachel1.h in core_cm33.h file to allow access to
cache functions.
Co-authored-by: Christian Mauderer <christian.mauderer@embedded-brains.de>
Files are imported from https://github.com/ARM-software/CMSIS_5 revision
55b19837f5703e418ca37894d5745b1dc05e4c91
Like already checked in RTEMS commit
6b2318acef, the project still don't have a
NOTICE file.
Avoid reading from the pl011 data register unnecessarily. There is no
need to preserve the contents of this register as it is not normal
memory. This unnecessary read causes console spam when running under the
Xen hypervisor when the read FIFO is empty since the read is not
expected.
Before, the console driver needed
`BSP_CONSOLE_USE_INTERRUPTS` to be defined or it
would not build. The intent was to use polled
mode if the macro was equal to zero.
This change makes it so interrupt mode is used if
the macro is defined and polled mode is used if
the macro is not defined.
The old logic would lead to an error when
multiprocessing was enabled and
`LEON3_GPTIMER_BASE` was defined due to
`leon3_timer_core_index` being undefined.
The new logic fixes this and keeps the same
intent:
- If multiprocessing is not enabled, the timer
index is 0
- If multiprocessing is enabled and
`LEON3_GPTIMER_BASE` is defined, the timer
index is twice the CPU boot index
- If multiprocessing is enabled and
`LEON3_GPTIMER_BASE` is not defined, we
fallback to the old logic using the GPTIMER
core index.
Close#5258
The gen5200, gen83xx, and tqm8xx BSP families have multiple variants
which produced the same stray semi-colon warning from GCC 15 for
using LINKER_SYMBOLS() with a semi-colon at the end of the line.
Closes#5277.
