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Whitespace removal.

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This commit is contained in:
Ralf Corsepius
2009-11-29 15:27:07 +00:00
parent d4b4664b99
commit efdfd48add
57 changed files with 966 additions and 966 deletions
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40
c/src/lib/libbsp/mips/csb350/clock/clockdrv.c
View File

@@ -5,7 +5,7 @@
*
* Copyright (c) 2005 by Cogent Computer Systems
* Written by Jay Monkman <jtm@lopingdog.com>
*
*
* The license and distribution terms for this file may be
* found in found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
@@ -46,27 +46,27 @@ uint32_t last_match;
void au1x00_clock_init(void)
{
uint32_t wakemask;
/* Clear the trim register */
AU1X00_SYS_TOYTRIM(AU1X00_SYS_ADDR) = 0;
/* Clear the TOY counter */
while (AU1X00_SYS_CNTCTRL(AU1X00_SYS_ADDR) & AU1X00_SYS_CNTCTRL_TS);
AU1X00_SYS_TOYWRITE(AU1X00_SYS_ADDR) = 0;
while (AU1X00_SYS_CNTCTRL(AU1X00_SYS_ADDR) & AU1X00_SYS_CNTCTRL_TS);
wakemask = AU1X00_SYS_WAKEMSK(AU1X00_SYS_ADDR);
/* Clear the trim register */
AU1X00_SYS_TOYTRIM(AU1X00_SYS_ADDR) = 0;
/* Clear the TOY counter */
while (AU1X00_SYS_CNTCTRL(AU1X00_SYS_ADDR) & AU1X00_SYS_CNTCTRL_TS);
AU1X00_SYS_TOYWRITE(AU1X00_SYS_ADDR) = 0;
while (AU1X00_SYS_CNTCTRL(AU1X00_SYS_ADDR) & AU1X00_SYS_CNTCTRL_TS);
wakemask = AU1X00_SYS_WAKEMSK(AU1X00_SYS_ADDR);
wakemask |= AU1X00_SYS_WAKEMSK_M20;
AU1X00_SYS_WAKEMSK(AU1X00_SYS_ADDR) = wakemask;
AU1X00_SYS_WAKEMSK(AU1X00_SYS_ADDR) = wakemask;
AU1X00_IC_WAKESET(AU1X00_IC0_ADDR) = AU1X00_IC_IRQ_TOY_MATCH2;
tick_interval = 32768 * rtems_configuration_get_microseconds_per_tick();
tick_interval = tick_interval / 1000000;
printk("tick_interval = %d\n", tick_interval);
last_match = AU1X00_SYS_TOYREAD(AU1X00_SYS_ADDR);
AU1X00_SYS_TOYMATCH2(AU1X00_SYS_ADDR) = last_match + (50*tick_interval);
tick_interval = 32768 * rtems_configuration_get_microseconds_per_tick();
tick_interval = tick_interval / 1000000;
printk("tick_interval = %d\n", tick_interval);
last_match = AU1X00_SYS_TOYREAD(AU1X00_SYS_ADDR);
AU1X00_SYS_TOYMATCH2(AU1X00_SYS_ADDR) = last_match + (50*tick_interval);
AU1X00_IC_MASKSET(AU1X00_IC0_ADDR) = AU1X00_IC_IRQ_TOY_MATCH2;
while (AU1X00_SYS_CNTCTRL(AU1X00_SYS_ADDR) & AU1X00_SYS_CNTCTRL_TM0);
while (AU1X00_SYS_CNTCTRL(AU1X00_SYS_ADDR) & AU1X00_SYS_CNTCTRL_TM0);
}
#define Clock_driver_support_initialize_hardware() \
@@ -74,7 +74,7 @@ void au1x00_clock_init(void)
au1x00_clock_init(); \
} while(0)
#define Clock_driver_support_shutdown_hardware()

12
c/src/lib/libbsp/mips/csb350/console/console-io.c
View File

@@ -47,13 +47,13 @@ void console_outbyte_polled(
while ((uart0->linestat & 0x20) == 0) {
continue;
}
uart0->txdata = ch;
au_sync();
}
/*
* console_inbyte_nonblocking
* console_inbyte_nonblocking
*
* This routine polls for a character.
*/
@@ -74,11 +74,11 @@ int console_inbyte_nonblocking(
#include <rtems/bspIo.h>
void csb250_output_char(char c)
{
console_outbyte_polled( 0, c );
void csb250_output_char(char c)
{
console_outbyte_polled( 0, c );
if (c == '\n') {
console_outbyte_polled( 0, '\r' );
console_outbyte_polled( 0, '\r' );
}
}

2
c/src/lib/libbsp/mips/csb350/include/bsp.h
View File

@@ -34,7 +34,7 @@ extern "C" {
*/
extern struct rtems_bsdnet_ifconfig *config;
int rtems_au1x00_emac_attach(struct rtems_bsdnet_ifconfig *config,
int rtems_au1x00_emac_attach(struct rtems_bsdnet_ifconfig *config,
int attaching);
#define RTEMS_BSP_NETWORK_DRIVER_NAME "eth0"
#define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_au1x00_emac_attach

168
c/src/lib/libbsp/mips/csb350/network/network.c
View File

@@ -3,7 +3,7 @@
*
* Copyright (c) 2005 by Cogent Computer Systems
* Written by Jay Monkman <jtm@lopingdog.com>
*
*
* The license and distribution terms for this file may be
* found in found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
@@ -61,23 +61,23 @@ typedef struct
* This entry *must* be the first in the sonic_softc structure.
*/
struct arpcom arpcom;
/*
* Interrupt vector
*/
rtems_vector_number vector;
/*
* Indicates configuration
*/
int acceptBroadcast;
/*
* Tasks waiting for interrupts
*/
rtems_id rx_daemon_tid;
rtems_id tx_daemon_tid;
/*
* Buffers
*/
@@ -125,7 +125,7 @@ typedef struct
unsigned long rx_watchdog;
unsigned long rx_pkts;
unsigned long rx_dropped;
unsigned long tx_deferred;
unsigned long tx_underrun;
unsigned long tx_aborted;
@@ -136,7 +136,7 @@ static au1x00_emac_softc_t softc[NUM_IFACES];
/* function prototypes */
int rtems_au1x00_emac_attach (struct rtems_bsdnet_ifconfig *config,
int rtems_au1x00_emac_attach (struct rtems_bsdnet_ifconfig *config,
int attaching);
void au1x00_emac_init(void *arg);
void au1x00_emac_init_hw(au1x00_emac_softc_t *sc);
@@ -160,10 +160,10 @@ static void mii_write(au1x00_emac_softc_t *sc, uint8_t reg, uint16_t val)
/* write to address 0 - we only support address 0 */
AU1X00_MAC_MIIDATA(sc->ctrl_regs) = val;
AU1X00_MAC_MIICTRL(sc->ctrl_regs) = (((reg & 0x1f) << 6) |
AU1X00_MAC_MIICTRL(sc->ctrl_regs) = (((reg & 0x1f) << 6) |
AU1X00_MAC_MIICTRL_MW);
au_sync();
/* wait for it to complete */
while (AU1X00_MAC_MIICTRL(sc->ctrl_regs) & AU1X00_MAC_MIICTRL_MB) {
continue;
@@ -180,7 +180,7 @@ static void mii_read(au1x00_emac_softc_t *sc, uint8_t reg, uint16_t *val)
/* write to address 0 - we only support address 0 */
AU1X00_MAC_MIICTRL(sc->ctrl_regs) = ((reg & 0x1f) << 6);
au_sync();
/* wait for it to complete */
while (AU1X00_MAC_MIICTRL(sc->ctrl_regs) & AU1X00_MAC_MIICTRL_MB) {
continue;
@@ -214,13 +214,13 @@ int rtems_au1x00_emac_attach (
int unitnumber;
char *unitname;
static au1x00_emac_softc_t *sc;
/*
* Parse driver name
*/
if ((unitnumber = rtems_bsdnet_parse_driver_name (config, &unitname)) < 0)
return 0;
/*
* Is driver free?
*/
@@ -240,9 +240,9 @@ int rtems_au1x00_emac_attach (
/*
* zero out the control structure
*/
memset((void *)sc, 0, sizeof(*sc));
sc->unitnumber = unitnumber;
sc->int_ctrlr = AU1X00_IC0_ADDR;
@@ -260,7 +260,7 @@ int rtems_au1x00_emac_attach (
/* If the ethernet controller is already set up, read the MAC address */
if ((*sc->en_reg & 0x33) == 0x33) {
sc->arpcom.ac_enaddr[5] = ((AU1X00_MAC_ADDRHIGH(sc->ctrl_regs) >> 8) &
sc->arpcom.ac_enaddr[5] = ((AU1X00_MAC_ADDRHIGH(sc->ctrl_regs) >> 8) &
0xff);
sc->arpcom.ac_enaddr[4] = ((AU1X00_MAC_ADDRHIGH(sc->ctrl_regs) >> 0) &
0xff);
@@ -268,9 +268,9 @@ int rtems_au1x00_emac_attach (
0xff);
sc->arpcom.ac_enaddr[2] = ((AU1X00_MAC_ADDRLOW(sc->ctrl_regs) >> 16) &
0xff);
sc->arpcom.ac_enaddr[1] = ((AU1X00_MAC_ADDRLOW(sc->ctrl_regs) >> 8) &
sc->arpcom.ac_enaddr[1] = ((AU1X00_MAC_ADDRLOW(sc->ctrl_regs) >> 8) &
0xff);
sc->arpcom.ac_enaddr[0] = ((AU1X00_MAC_ADDRLOW(sc->ctrl_regs) >> 0) &
sc->arpcom.ac_enaddr[0] = ((AU1X00_MAC_ADDRLOW(sc->ctrl_regs) >> 0) &
0xff);
} else {
/* It's not set up yet, so we set a MAC address */
@@ -281,7 +281,7 @@ int rtems_au1x00_emac_attach (
sc->arpcom.ac_enaddr[1] = 0x23;
sc->arpcom.ac_enaddr[0] = 0x00;
}
if (config->mtu) {
mtu = config->mtu;
@@ -290,7 +290,7 @@ int rtems_au1x00_emac_attach (
}
sc->acceptBroadcast = !config->ignore_broadcast;
/*
* Set up network interface values
*/
@@ -317,19 +317,19 @@ int rtems_au1x00_emac_attach (
void au1x00_emac_init(void *arg)
{
au1x00_emac_softc_t *sc = arg;
au1x00_emac_softc_t *sc = arg;
struct ifnet *ifp = &sc->arpcom.ac_if;
/*
*This is for stuff that only gets done once (au1x00_emac_init()
* gets called multiple times
/*
*This is for stuff that only gets done once (au1x00_emac_init()
* gets called multiple times
*/
if (sc->tx_daemon_tid == 0)
{
/* Set up EMAC hardware */
au1x00_emac_init_hw(sc);
/* install the interrupt handler */
if (sc->unitnumber == 0) {
set_vector(au1x00_emac_isr, AU1X00_IRQ_MAC0, 1);
@@ -338,48 +338,48 @@ void au1x00_emac_init(void *arg)
}
AU1X00_IC_MASKCLR(sc->int_ctrlr) = sc->int_mask;
au_sync();
/* set src bit */
AU1X00_IC_SRCSET(sc->int_ctrlr) = sc->int_mask;
/* high level */
AU1X00_IC_CFG0SET(sc->int_ctrlr) = sc->int_mask;
AU1X00_IC_CFG1CLR(sc->int_ctrlr) = sc->int_mask;
AU1X00_IC_CFG2SET(sc->int_ctrlr) = sc->int_mask;
/* assign to request 0 - negative logic */
AU1X00_IC_ASSIGNSET(sc->int_ctrlr) = sc->int_mask;
au_sync();
/* Start driver tasks */
sc->tx_daemon_tid = rtems_bsdnet_newproc("ENTx",
4096,
au1x00_emac_tx_daemon,
sc->tx_daemon_tid = rtems_bsdnet_newproc("ENTx",
4096,
au1x00_emac_tx_daemon,
sc);
sc->rx_daemon_tid = rtems_bsdnet_newproc("ENRx",
4096,
au1x00_emac_rx_daemon,
sc->rx_daemon_tid = rtems_bsdnet_newproc("ENRx",
4096,
au1x00_emac_rx_daemon,
sc);
}
/* EMAC doesn't support promiscuous, so ignore requests */
if (ifp->if_flags & IFF_PROMISC)
printf ("Warning - AU1X00 EMAC doesn't support Promiscuous Mode!\n");
/*
* Tell the world that we're running.
*/
ifp->if_flags |= IFF_RUNNING;
/*
* start tx, rx
* start tx, rx
*/
AU1X00_MAC_CONTROL(sc->ctrl_regs) |= (AU1X00_MAC_CTRL_TE |
AU1X00_MAC_CONTROL(sc->ctrl_regs) |= (AU1X00_MAC_CTRL_TE |
AU1X00_MAC_CTRL_RE);
au_sync();
} /* au1x00_emac_init() */
@@ -390,7 +390,7 @@ void au1x00_emac_init_hw(au1x00_emac_softc_t *sc)
struct ifnet *ifp = &sc->arpcom.ac_if;
/* reset the MAC */
*sc->en_reg = 0x40;
*sc->en_reg = 0x40;
au_sync();
for (i = 0; i < 10000; i++) {
continue;
@@ -404,9 +404,9 @@ void au1x00_emac_init_hw(au1x00_emac_softc_t *sc)
}
/*
*sc->en_reg = (AU1X00_MAC_EN_CE |
AU1X00_MAC_EN_E2 |
AU1X00_MAC_EN_E1 |
*sc->en_reg = (AU1X00_MAC_EN_CE |
AU1X00_MAC_EN_E2 |
AU1X00_MAC_EN_E1 |
AU1X00_MAC_EN_E0);
*/
*sc->en_reg = 0x33;
@@ -445,7 +445,7 @@ void au1x00_emac_init_hw(au1x00_emac_softc_t *sc)
au_sync();
printk("mac_control was set to 0x%x\n", AU1X00_MAC_CONTROL(sc->ctrl_regs));
printk("mac_control addr is 0x%x\n", &AU1X00_MAC_CONTROL(sc->ctrl_regs));
/* initialize our receive buffer descriptors */
for (i = 0; i < NUM_RX_DMA_BUFS; i++) {
MGETHDR(m, M_WAIT, MT_DATA);
@@ -456,7 +456,7 @@ void au1x00_emac_init_hw(au1x00_emac_softc_t *sc)
/*
* The receive buffer must be aligned with a cache line
* boundary.
* boundary.
*/
if (mtod(m, uint32_t) & 0x1f) {
uint32_t *p = mtod(m, uint32_t *);
@@ -491,7 +491,7 @@ void au1x00_emac_init_hw(au1x00_emac_softc_t *sc)
void au1x00_emac_start(struct ifnet *ifp)
{
au1x00_emac_softc_t *sc = ifp->if_softc;
rtems_event_send(sc->tx_daemon_tid, START_TX_EVENT);
ifp->if_flags |= IFF_OACTIVE;
}
@@ -499,15 +499,15 @@ void au1x00_emac_start(struct ifnet *ifp)
void au1x00_emac_stop (au1x00_emac_softc_t *sc)
{
struct ifnet *ifp = &sc->arpcom.ac_if;
ifp->if_flags &= ~IFF_RUNNING;
/*
* Stop the transmitter and receiver.
*/
/* Disable TX/RX */
AU1X00_MAC_CONTROL(sc->ctrl_regs) &= ~(AU1X00_MAC_CTRL_TE |
AU1X00_MAC_CONTROL(sc->ctrl_regs) &= ~(AU1X00_MAC_CTRL_TE |
AU1X00_MAC_CTRL_RE);
au_sync();
}
@@ -577,7 +577,7 @@ void au1x00_emac_rx_daemon (void *arg)
/* while there are packets to receive */
while (!(sc->rx_dma[sc->rx_head].addr & (AU1X00_MAC_DMA_RXADDR_DN |
while (!(sc->rx_dma[sc->rx_head].addr & (AU1X00_MAC_DMA_RXADDR_DN |
AU1X00_MAC_DMA_RXADDR_EN))) {
status = sc->rx_dma[sc->rx_head].stat;
if (status & AU1X00_MAC_DMA_RXSTAT_MI) {
@@ -621,51 +621,51 @@ void au1x00_emac_rx_daemon (void *arg)
}
/* If no errrors, accept packet */
if ((status & (AU1X00_MAC_DMA_RXSTAT_CR |
AU1X00_MAC_DMA_RXSTAT_DB |
if ((status & (AU1X00_MAC_DMA_RXSTAT_CR |
AU1X00_MAC_DMA_RXSTAT_DB |
AU1X00_MAC_DMA_RXSTAT_RF)) == 0) {
sc->rx_pkts++;
/* find the start of the mbuf */
m = sc->rx_mbuf[sc->rx_head];
/* set the length of the mbuf */
m->m_len = AU1X00_MAC_DMA_RXSTAT_LEN(sc->rx_dma[sc->rx_head].stat);
m->m_len -= 4; /* remove ethernet CRC */
m->m_pkthdr.len = m->m_len;
/* strip off the ethernet header from the mbuf */
/* but save the pointer to it */
eh = mtod (m, struct ether_header *);
m->m_data += sizeof(struct ether_header);
/* give the received packet to the stack */
ether_input(ifp, eh, m);
/* get a new buf and make it ready for the MAC */
MGETHDR(m, M_WAIT, MT_DATA);
MCLGET(m, M_WAIT);
m->m_pkthdr.rcvif = ifp;
m->m_nextpkt = 0;
/*
* The receive buffer must be aligned with a cache line
* boundary.
* boundary.
*/
{
uint32_t *p = mtod(m, uint32_t *);
*p = (mtod(m, uint32_t) + 0x1f) & ~0x1f;
}
} else {
sc->rx_dropped++;
/* find the mbuf so we can reuse it*/
m = sc->rx_mbuf[sc->rx_head];
}
/* set up the receive dma to use the mbuf's cluster */
sc->rx_dma[sc->rx_head].addr = (mtod(m, uint32_t) & ~0xe0000000);
au_sync();
@@ -673,7 +673,7 @@ void au1x00_emac_rx_daemon (void *arg)
sc->rx_dma[sc->rx_head].addr |= AU1X00_MAC_DMA_RXADDR_EN;
au_sync();
/* increment the buffer index */
sc->rx_head++;
@@ -697,20 +697,20 @@ void au1x00_emac_sendpacket (struct ifnet *ifp, struct mbuf *m)
AU1X00_MAC_DMA_TXADDR_DN)) != 0) {
continue;
}
/* copy the mbuf chain into the transmit buffer */
l = m;
txbuf = (uint32_t)sc->tx_buf[sc->tx_head];
while (l != NULL)
{
memcpy(((char *)txbuf + pkt_offset), /* offset into pkt for mbuf */
(char *)mtod(l, void *), /* cast to void */
(char *)mtod(l, void *), /* cast to void */
l->m_len); /* length of this mbuf */
pkt_offset += l->m_len; /* update offset */
l = l->m_next; /* get next mbuf, if any */
l = l->m_next; /* get next mbuf, if any */
}
/* Pad if necessary */
@@ -722,12 +722,12 @@ void au1x00_emac_sendpacket (struct ifnet *ifp, struct mbuf *m)
/* send it off */
sc->tx_dma[sc->tx_head].stat = 0;
sc->tx_dma[sc->tx_head].len = pkt_offset;
sc->tx_dma[sc->tx_head].addr = ((txbuf & ~0xe0000000) |
sc->tx_dma[sc->tx_head].addr = ((txbuf & ~0xe0000000) |
AU1X00_MAC_DMA_TXADDR_EN);
au_sync();
/*
/*
*Without this delay, some outgoing packets never
* make it out the device. Nothing in the documentation
* explains this.
@@ -747,7 +747,7 @@ void au1x00_emac_sendpacket (struct ifnet *ifp, struct mbuf *m)
} /* au1x00_emac_sendpacket () */
/* Show interface statistics */
void au1x00_emac_stats (au1x00_emac_softc_t *sc)
{
@@ -769,7 +769,7 @@ void au1x00_emac_stats (au1x00_emac_softc_t *sc)
printf("RX runt:%-8lu", sc->rx_runt);
printf(" RX watchdog:%-8lu", sc->rx_watchdog);
printf(" RX dropped:%-8lu\n", sc->rx_dropped);
printf("TX Packets:%-8lu", sc->tx_pkts);
printf(" TX Deferred:%-8lu", sc->tx_deferred);
printf(" TX Underrun:%-8lu\n", sc->tx_underrun);
@@ -784,38 +784,38 @@ au1x00_emac_ioctl (struct ifnet *ifp, int command, caddr_t data)
{
au1x00_emac_softc_t *sc = ifp->if_softc;
int error = 0;
switch (command) {
case SIOCGIFADDR:
case SIOCSIFADDR:
ether_ioctl (ifp, command, data);
break;
case SIOCSIFFLAGS:
switch (ifp->if_flags & (IFF_UP | IFF_RUNNING))
{
case IFF_RUNNING:
au1x00_emac_stop (sc);
break;
case IFF_UP:
au1x00_emac_init (sc);
break;
case IFF_UP | IFF_RUNNING:
au1x00_emac_stop (sc);
au1x00_emac_init (sc);
break;
default:
break;
} /* switch (if_flags) */
break;
case SIO_RTEMS_SHOW_STATS:
au1x00_emac_stats (sc);
break;
/*
* FIXME: All sorts of multicast commands need to be added here!
*/
@@ -841,7 +841,7 @@ rtems_isr au1x00_emac_isr (rtems_vector_number v)
sc->interrupts++;
/*
* Since there's no easy way to find out the source of the
* Since there's no easy way to find out the source of the
* interrupt, we have to look at the tx and rx dma buffers
*/
/* receive interrupt */
@@ -850,7 +850,7 @@ rtems_isr au1x00_emac_isr (rtems_vector_number v)
sc->rx_interrupts++;
sc->rx_dma[sc->rx_tail].addr &= ~AU1X00_MAC_DMA_RXADDR_DN;
au_sync();
sc->rx_tail++;
if (sc->rx_tail >= NUM_RX_DMA_BUFS) {
sc->rx_tail = 0;
@@ -865,7 +865,7 @@ rtems_isr au1x00_emac_isr (rtems_vector_number v)
uint32_t status;
tx_flag = 1;
sc->tx_interrupts++;
status = sc->tx_dma[sc->tx_tail].stat;
if (status & AU1X00_MAC_DMA_TXSTAT_DF) {
sc->tx_deferred++;
@@ -876,7 +876,7 @@ rtems_isr au1x00_emac_isr (rtems_vector_number v)
if (status & AU1X00_MAC_DMA_TXSTAT_FA) {
sc->tx_aborted++;
}
sc->tx_dma[sc->tx_tail].addr = 0;
au_sync();

12
c/src/lib/libbsp/mips/csb350/start/start.S
View File

@@ -3,7 +3,7 @@
*
* Copyright (c) 2005 by Cogent Computer Systems
* Written by Jay Monkman <jtm@lopingdog.com>
*
*
* The license and distribution terms for this file may be
* found in found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
@@ -29,7 +29,7 @@
_start:
.set noreorder
/* Get the address of start into $5 in a position independent
/* Get the address of start into $5 in a position independent
* fashion. This lets us know whether we have been relocated or not.
*/
$LF1 = . + 8
@@ -47,7 +47,7 @@ _branch:
li v0, SR_PE|SR_FR|SR_KX|SR_SX|SR_UX
mtc0 v0, C0_SR
2:
/* Fix high bits, if any, of the PC so that exception handling
/* Fix high bits, if any, of the PC so that exception handling
doesn't get confused. */
la v0, 3f
jr v0
@@ -75,7 +75,7 @@ zerobss:
case main wants to write them back to the stack. The caller is
supposed to allocate stack space for parameters in registers in
the old MIPS ABIs. We must do this even though we aren't passing
arguments, because main might be declared to have them.
arguments, because main might be declared to have them.
Some ports need a larger alignment for the stack, so we subtract
32, which satisifes the stack for the arguments and keeps the
@@ -98,7 +98,7 @@ init:
/* destructors */
move a0,v0 /* pass through the exit code */
.end init
/*
* _sys_exit -- Exit from the application. Normally we cause a user trap
* to return to the ROM monitor for another run. NOTE: This is
@@ -121,5 +121,5 @@ _sys_exit:
b 7b /* but loop back just in-case */
nop
.end _sys_exit
/* EOF crt0.S */

2
c/src/lib/libbsp/mips/csb350/startup/bspreset.c
View File

@@ -14,7 +14,7 @@
void bsp_reset(void)
{
void (*reset_func)(void);
reset_func = (void *)0xbfc00000;
mips_set_sr( 0x00200000 ); /* all interrupts off, boot exception vectors */

2
c/src/lib/libbsp/mips/csb350/startup/bspstart.c
View File

@@ -30,7 +30,7 @@ au1x00_uart_t *uart3 = (au1x00_uart_t *)AU1X00_UART3_ADDR;
*/
void bsp_start( void )
{
unsigned int compare = 0;
unsigned int compare = 0;
mips_set_sr( 0x7f00 ); /* all interrupts unmasked but globally off */
/* depend on the IRC to take care of things */

4
c/src/lib/libbsp/mips/csb350/timer/timer.c
View File

@@ -1,10 +1,10 @@
/*
/*
* This file implements a benchmark timer using the count/compare
* CP0 registers.
*
* Copyright (c) 2005 by Cogent Computer Systems
* Written by Jay Monkman <jtm@lopingdog.com>
*
*
* The license and distribution terms for this file may be
* found in found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.

24
c/src/lib/libbsp/mips/hurricane/clock/ckinit.c
View File

@@ -90,7 +90,7 @@ uint32_t Clock_isrs; /* ISRs until next tick */
/*
* These are set by clock driver during its init
*/
rtems_device_major_number rtems_clock_major = ~0;
rtems_device_minor_number rtems_clock_minor;
@@ -163,24 +163,24 @@ void Install_clock(
/*
* Hardware specific initialize goes here
*/
/* Set up USC heartbeat timer to generate interrupts */
disable_hbi(); /* Disable heartbeat interrupt in USC */
/* Install interrupt handler */
Old_ticker = (rtems_isr_entry) set_vector( USC_isr, CLOCK_VECTOR, 1 );
init_hbt(); /* Initialize heartbeat timer */
reset_wdt(); /* Reset watchdog timer */
enable_wdi(); /* Enable watchdog interrupt in USC */
enable_hbi(); /* Enable heartbeat interrupt in USC */
/* Enable USC interrupt in MIPS processor */
mips_enable_in_interrupt_mask(CLOCK_VECTOR_MASK);
/*
* Schedule the clock cleanup routine to execute if the application exits.
*/
@@ -211,14 +211,14 @@ rtems_device_driver Clock_initialize(
)
{
Install_clock( Clock_isr );
/*
* make major/minor avail to others such as shared memory driver
*/
rtems_clock_major = major;
rtems_clock_minor = minor;
return RTEMS_SUCCESSFUL;
}

2
c/src/lib/libbsp/mips/hurricane/clock/clock.S
View File

@@ -1,4 +1,4 @@
/* clock.s
/* clock.s
*
* This file contains the assembly code for the Hurricane BSP clock driver.
*

12
c/src/lib/libbsp/mips/hurricane/console/console.c
View File

@@ -54,16 +54,16 @@ rtems_device_driver console_initialize(
)
{
rtems_status_code status;
status = rtems_io_register_name(
"/dev/console",
major,
(rtems_device_minor_number) 0
);
if (status != RTEMS_SUCCESSFUL)
rtems_fatal_error_occurred(status);
return RTEMS_SUCCESSFUL;
}
@@ -157,7 +157,7 @@ rtems_device_driver console_open(
#endif
return RTEMS_SUCCESSFUL;
}
/*
* Close entry point
*/
@@ -189,7 +189,7 @@ rtems_device_driver console_read(
char *buffer;
int maximum;
int count = 0;
rw_args = (rtems_libio_rw_args_t *) arg;
buffer = rw_args->buffer;
@@ -208,7 +208,7 @@ rtems_device_driver console_read(
}
/*
* write bytes to the serial port. Stdout and stderr are the same.
* write bytes to the serial port. Stdout and stderr are the same.
*/
rtems_device_driver console_write(

2
c/src/lib/libbsp/mips/hurricane/include/bsp.h
View File

@@ -35,7 +35,7 @@ extern uint32_t mips_get_timer( void );
* Simple spin delay in microsecond units for device drivers.
* This is very dependent on the clock speed of the target.
*
* NOTE: This macro generates a warning like "integer constant out
* NOTE: This macro generates a warning like "integer constant out
* of range" which is safe to ignore. In 64 bit mode, unsigned32
* types are actually 64 bits long so that comparisons between
* unsigned32 types and pointers are valid. The warning is caused

60
c/src/lib/libbsp/mips/hurricane/start/start.S
View File

@@ -19,7 +19,7 @@ two paragraphs in the transferred software.
COPYRIGHT IDT CORPORATION 1996
LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
*/
*/
/*************************************************************************
**
@@ -37,7 +37,7 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
#include <rtems/asm.h>
#if 0
#if 0
.extern _fdata,4 /* this is defined by the linker */
.extern _edata,4 /* this is defined by the linker */
.extern _idata,4 /* this is defined by the linker */
@@ -53,11 +53,11 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
at least 16 megabytes of RAM */
#define HARD_CODED_MEM_SIZE 0x1000000
#define TMP_STKSIZE 1024
#define TMP_STKSIZE 1024
/*
** P_STACKSIZE is the size of the Prom Stack.
** the prom stack grows downward
** P_STACKSIZE is the size of the Prom Stack.
** the prom stack grows downward
*/
#define P_STACKSIZE 0x2000 /* sets stack size to 8k */
@@ -72,7 +72,7 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
** c) Clear all IntMask Enables
** d) Set kernel/disabled mode
** 2) Initialize Cause Register
** a) clear software interrupt bits
** a) clear software interrupt bits
** 3) Determine FPU installed or not
** if not, clear CoProcessor 1 usable bit
** 4) Clear bss area
@@ -84,15 +84,15 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
** 9) Flush Instruction and Data caches
** 10) If there is a Translation Lookaside Buffer, Clear the TLB
** 11) Execute initialization code if the IDT/c library is to be used
**
**
** 12) Jump to user's "main()" (boot_card() for RTEMS)
** 13) Jump to promexit
**
** IDT/C 5.x defines _R3000, IDT/C 6.x defines _R4000 internally.
** IDT/C 5.x defines _R3000, IDT/C 6.x defines _R4000 internally.
** This is used to mark code specific to R3xxx or R4xxx processors.
** IDT/C 6.x defines __mips to be the ISA level for which we're
** generating code. This is used to make sure the stack etc. is
** double word aligned, when using -mips3 (default) or -mips2,
** IDT/C 6.x defines __mips to be the ISA level for which we're
** generating code. This is used to make sure the stack etc. is
** double word aligned, when using -mips3 (default) or -mips2,
** when compiling with IDT/C6.x
**
***************************************************************************/
@@ -110,7 +110,7 @@ FRAME(start,sp,0,ra)
nop
mtc0 zero,C0_CAUSE /* clear software interrupts */
nop
la t0,0xBE200000 /* on Hurricane board, enable interrupt output signal from UART ch. B */
li t1,0x8 /* UART INT B signal is left tri-state'd after reset, this results in processor interrupt signal being driven active low */
sw t1,0x10(t0)
@@ -119,10 +119,10 @@ FRAME(start,sp,0,ra)
mtc0 v0,C0_CONFIG
/*
** check to see if an fpu is really plugged in
** check to see if an fpu is really plugged in
*/
li t3,0xaaaa5555 /* put a's and 5's in t3 */
mtc1 t3,fp0 /* try to write them into fp0 */
mtc1 t3,fp0 /* try to write them into fp0 */
mtc1 zero,fp1 /* try to write zero in fp */
mfc1 t0,fp0
mfc1 t1,fp1
@@ -140,7 +140,7 @@ FRAME(start,sp,0,ra)
mtc0 v0, C0_SR /* reset status register */
2:
la gp, _gp
la gp, _gp
#if 0
/* Initialize data sections from "rom" copy */
@@ -160,7 +160,7 @@ FRAME(start,sp,0,ra)
la v1,end /* end of bss */
4: sw zero,0(v0)
bltu v0,v1,4b
add v0,4
add v0,4
/************************************************************************
@@ -173,7 +173,7 @@ FRAME(start,sp,0,ra)
**
*************************************************************************/
/* For MIPS 3, we need to be sure that the stack is aligned on a
* double word boundary.
* double word boundary.
*/
andi t0, v0, 0x7
beqz t0, 11f /* Last three bits Zero, already aligned */
@@ -185,11 +185,11 @@ FRAME(start,sp,0,ra)
add v1, v0, TMP_STKSIZE /* end of bss + length of tmp stack */
sub v1, v1, (4*4) /* overhead */
move sp, v1 /* set sp to top of stack */
4: sw zero, 0(v0)
4: sw zero, 0(v0)
bltu v0, v1, 4b /* clear out temp stack */
add v0, 4
/* jal init_exc_vecs */ /* install exception handlers */
add v0, 4
/* jal init_exc_vecs */ /* install exception handlers */
/* nop */ /* MUST do before memory probes */
/* Force processor into uncached space during memory/cache probes */
@@ -216,7 +216,7 @@ FRAME(start,sp,0,ra)
move v0, a0 /* mem_size */
/* For MIPS 3, we need to be sure that the stack (and hence v0
* here) is aligned on a double word boundary.
* here) is aligned on a double word boundary.
*/
andi t0, v0, 0x7
beqz t0, 12f /* Last three bits Zero, already aligned */
@@ -228,9 +228,9 @@ FRAME(start,sp,0,ra)
/**************************************************************************
**
** Permanent Stack - now know top of memory, put permanent stack there
** Permanent Stack - now know top of memory, put permanent stack there
**
***************************************************************************/
***************************************************************************/
la t2, _fbss /* cache mode as linked */
and t2, 0xF0000000 /* isolate segment */
@@ -244,9 +244,9 @@ FRAME(start,sp,0,ra)
move v1, v0
subu v1, P_STACKSIZE /* clear requested stack size */
7: sw zero, 0(v1) /* clear P_STACKSIZE stack */
7: sw zero, 0(v1) /* clear P_STACKSIZE stack */
bltu v1,v0,7b
add v1, 4
add v1, 4
.set reorder
/* FIX THIS - This corrupts memory spaces */
@@ -258,7 +258,7 @@ FRAME(start,sp,0,ra)
**
** If this chip supports a Translation Lookaside Buffer, clear it
**
***************************************************************************/
***************************************************************************/
.set noreorder
mfc0 t1, C0_SR /* look at Status Register */
@@ -279,7 +279,7 @@ FRAME(start,sp,0,ra)
/************************************************************************
**
** Initialization required if using IDT/c or libc.a, standard C Lib
** Initialization required if using IDT/c or libc.a, standard C Lib
**
** can SKIP if not necessary for application
**
@@ -309,7 +309,7 @@ FRAME(start,sp,0,ra)
1:
beq zero,zero,1b
nop
ENDFRAME(start)
/*
@@ -327,7 +327,7 @@ FRAME(_sys_exit,sp,0,ra)
13:
b 13b # but loop back just in-case
nop
ENDFRAME(_sys_exit)

2
c/src/lib/libbsp/mips/hurricane/startup/bspstart.c
View File

@@ -19,7 +19,7 @@
#include <bsp.h>
uint32_t bsp_clicks_per_microsecond;
/*
* bsp_start
*

76
c/src/lib/libbsp/mips/hurricane/startup/exception.S
View File

@@ -184,7 +184,7 @@ _chk_int:
/* wastes a lot of stack space for context?? */
ADDIU sp,sp,-EXCP_STACK_SIZE
STREG ra, R_RA*R_SZ(sp) /* store ra on the stack */
STREG ra, R_RA*R_SZ(sp) /* store ra on the stack */
STREG v0, R_V0*R_SZ(sp)
STREG v1, R_V1*R_SZ(sp)
STREG a0, R_A0*R_SZ(sp)
@@ -201,13 +201,13 @@ _chk_int:
STREG t7, R_T7*R_SZ(sp)
mflo t0
STREG t8, R_T8*R_SZ(sp)
STREG t0, R_MDLO*R_SZ(sp)
STREG t0, R_MDLO*R_SZ(sp)
STREG t9, R_T9*R_SZ(sp)
mfhi t0
STREG gp, R_GP*R_SZ(sp)
STREG t0, R_MDHI*R_SZ(sp)
STREG t0, R_MDHI*R_SZ(sp)
STREG fp, R_FP*R_SZ(sp)
.set noat
STREG AT, R_AT*R_SZ(sp)
.set at
@@ -277,7 +277,7 @@ _ISR_Handler_cleanup:
* #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE )
* restore stack
* #endif
*
*
* if ( !_Context_Switch_necessary && !_ISR_Signals_to_thread_executing )
* goto the label "exit interrupt (simple case)"
*/
@@ -311,7 +311,7 @@ _ISR_Handler_cleanup:
/* save off our stack frame so the context switcher can get to it */
la t0,__exceptionStackFrame
STREG sp,(t0)
jal _Thread_Dispatch
NOP
@@ -321,7 +321,7 @@ _ISR_Handler_cleanup:
STREG zero,(t0)
NOP
/*
/*
** turn interrupts back off while we restore context so
** a badly timed interrupt won't accidentally mess things up
*/
@@ -335,7 +335,7 @@ _ISR_Handler_cleanup:
or t0,t1
#elif __mips == 1
/* ints off, current & prev kernel mode on (kernel mode enabled is bit clear..argh!) */
li t1,SR_IEC | SR_KUP | SR_KUC
li t1,SR_IEC | SR_KUP | SR_KUC
not t1
and t0, t1
#endif
@@ -347,14 +347,14 @@ _ISR_Handler_cleanup:
**
** make sure previous int enable is on because we're returning from an interrupt
** which means interrupts have to be enabled
li t1,SR_IEP
or t0,t1
*/
#endif
mtc0 t0, C0_SR
NOP
/*
* prepare to get out of interrupt
* return from interrupt (maybe to _ISR_Dispatch)
@@ -370,7 +370,7 @@ _ISR_Handler_exit:
LDREG t8, R_MDLO*R_SZ(sp)
LDREG t0, R_T0*R_SZ(sp)
mtlo t8
LDREG t8, R_MDHI*R_SZ(sp)
LDREG t8, R_MDHI*R_SZ(sp)
LDREG t1, R_T1*R_SZ(sp)
mthi t8
LDREG t2, R_T2*R_SZ(sp)
@@ -390,10 +390,10 @@ _ISR_Handler_exit:
LDREG a3, R_A3*R_SZ(sp)
LDREG v1, R_V1*R_SZ(sp)
LDREG v0, R_V0*R_SZ(sp)
LDREG k1, R_EPC*R_SZ(sp)
mtc0 k1,C0_EPC
.set noat
LDREG AT, R_AT*R_SZ(sp)
.set at
@@ -407,14 +407,14 @@ _ISR_Handler_quick_exit:
/* Interrupts from USC320 are serviced here */
.global USC_isr
.extern Clock_isr
.extern Clock_isr
USC_isr:
/* check if it's a USC320 heartbeat interrupt */
la k0,INT_STAT /* read INT_STAT register */
lw k0,(k0)
nop /* reading from external device */
sll k0,(31-21) /* test bit 21 (HBI) */
bgez k0,USC_isr2 /* branch if not a heartbeat interrupt */
NOP
@@ -434,7 +434,7 @@ USC_isr1:
nop
USC_isr2:
j ra /* no serviceable interrupt, return without doing anything */
nop
nop
.set reorder
@@ -450,7 +450,7 @@ FRAME(_BRK_Handler,sp,0,ra)
and k1,k1,k0
la k0,INT_CFG3
sw k1,(k0)
la k0,_brk_esr_link /* Jump to next exception handler in PMON exception chain */
lw k0,(k0)
lw k0,4(k0)
@@ -478,7 +478,7 @@ FRAME(init_exc_vecs,sp,0,ra)
.set noreorder
.extern mon_onintr
/* Install interrupt handler in PMON exception handling chain */
addiu sp,sp,-8
@@ -517,30 +517,30 @@ FRAME(init_hbt,sp,0,ra)
la t0,SYSTEM # Unlock USC registers
li t1,0xA5
sb t1,(t0)
la t0,WD_HBI # Initialize heatbeat and watchdog timers
# (1 / 64 MHz) * 4000 * (63 + 1) = 4000.0 microseconds
# (1 / 64 MHz) * 4000 * (63 + 1) = 4000.0 microseconds
# Watchdog period is heartbeat period times watchdog timer constant (bits 7 - 0)
# Watchdog period = 4000 * 5 = 20000 microseconds
li t1,(WD_EN | HBI_4000_PS | 0x00003F00 | 0x5)
# (1 / 64 MHz) * 4000 * (15 + 1) = 1000.0 microseconds
# (1 / 64 MHz) * 4000 * (15 + 1) = 1000.0 microseconds
# Watchdog period is heartbeat period times watchdog timer constant (bits 7 - 0)
# Watchdog period = 1000 * 20 = 20000 microseconds
li t1,(WD_EN | HBI_4000_PS | 0x00000F00 | 0x14)
# (1 / 64 MHz) * 40000 * (15 + 1) = 10000.0 microseconds
# (1 / 64 MHz) * 40000 * (15 + 1) = 10000.0 microseconds
# Watchdog period is heartbeat period times watchdog timer constant (bits 7 - 0)
# Watchdog period = 10000 * 20 = 200000 microseconds
li t1,(WD_EN | HBI_4000_PS | 0x00009600 | 0x14)
sw t1,(t0)
la t0,SYSTEM # Lock USC registers
li t1,0x60
sb t1,(t0)
.set reorder
j ra
nop
@@ -555,9 +555,9 @@ FRAME(reset_wdt,sp,0,ra)
.set noreorder
la t0,WD_HBI+2 # Load address watchdog timer reset byte
li t1,WD_INIT
li t1,WD_INIT
sb t1,(t0)
.set reorder
j ra
nop
@@ -575,7 +575,7 @@ FRAME(disable_wdt,sp,0,ra)
li t2,~WD_EN
and t1,t1,t2
sw t1,(t0)
.set reorder
j ra
nop
@@ -588,13 +588,13 @@ ENDFRAME(disable_wdt)
*/
FRAME(enable_hbi,sp,0,ra)
.set noreorder
la t0,INT_CFG3 # Enable heartbeat interrupt in USC320
lw t1,(t0)
li t2,(HBI_MASK | MODE_TOTEM_POLE)
or t1,t1,t2
sw t1,(t0)
.set reorder
j ra
nop
@@ -612,7 +612,7 @@ FRAME(disable_hbi,sp,0,ra)
li t2,~HBI_MASK
and t1,t1,t2
sw t1,(t0)
.set reorder
j ra
nop
@@ -626,13 +626,13 @@ ENDFRAME(disable_hbi)
*/
FRAME(enable_wdi,sp,0,ra)
.set noreorder
la t0,INT_CFG1 # Enable watchdog interrupt in USC320
lw t1,(t0)
li t2,(WDI_MASK | MODE_TOTEM_POLE)
or t1,t1,t2
sw t1,(t0)
.set reorder
j ra
nop
@@ -645,17 +645,17 @@ ENDFRAME(enable_wdi)
*/
FRAME(disable_wdi,sp,0,ra)
.set noreorder
la t0,INT_CFG1 # Disable watchdog interrupt in USC320
lw t1,(t0)
li t2,~(WDI_MASK | MODE_TOTEM_POLE)
and t1,t1,t2
sw t1,(t0)
la t0,INT_STAT # Clear watchdog interrupt status bit
li t1,WDI_MASK
sw t1,(t0)
.set reorder
j ra
nop
@@ -666,7 +666,7 @@ ENDFRAME(disable_wdi)
.data
k1tmp: .word 0 /* Temporary strage for K1 during interrupt service */
/*************************************************************
*
* Exception handler links, used in PMON exception handler chains
@@ -676,7 +676,7 @@ k1tmp: .word 0 /* Temporary strage for K1 during interrupt service */
_int_esr_link:
.word 0
.word hurricane_ISR_Handler
/* Break exception service routine link */
.global _brk_esr_link
_brk_esr_link:
@@ -684,5 +684,5 @@ _brk_esr_link:
.word _BRK_Handler

16
c/src/lib/libbsp/mips/hurricane/startup/idttlb.S
View File

@@ -182,7 +182,7 @@ ENDFRAME(ret_tlbhi)
FRAME(ret_tlbpid,sp,0,ra)
#if __mips == 1
.set noreorder
mfc0 v0,C0_TLBHI # fetch tlb high
mfc0 v0,C0_TLBHI # fetch tlb high
nop
and v0,TLBHI_PIDMASK # isolate and position
srl v0,TLBHI_PIDSHIFT
@@ -215,8 +215,8 @@ FRAME(tlbprobe,sp,0,ra)
mfc0 t0,C0_SR /* fetch status reg */
and a0,TLBHI_VPNMASK /* isolate just the vpn */
and t0,~SR_PE /* don't inadvertantly clear pe */
mtc0 zero,C0_SR
mfc0 t1,C0_TLBHI
mtc0 zero,C0_SR
mfc0 t1,C0_TLBHI
sll a1,TLBHI_PIDSHIFT /* possition the pid */
and a1,TLBHI_PIDMASK
or a0,a1 /* build entry hi value */
@@ -267,7 +267,7 @@ ENDFRAME(tlbprobe)
FRAME(resettlb,sp,0,ra)
#if __mips == 1
.set noreorder
mfc0 t0,C0_TLBHI # fetch the current hi
mfc0 t0,C0_TLBHI # fetch the current hi
mfc0 v0,C0_SR # fetch the status reg.
li t2,K0BASE&TLBHI_VPNMASK
and v0,~SR_PE # dont inadvertantly clear PE
@@ -325,13 +325,13 @@ FRAME(map_tlb,sp,0,ra)
mtc0 zero,C0_SR
mtc0 a1,C0_TLBHI # set the hi entry
mtc0 a2,C0_TLBLO # set the lo entry
mtc0 a2,C0_TLBLO # set the lo entry
mtc0 a0,C0_INX # load the index
nop
tlbwi # put the hi/lo in tlb entry indexed
nop
mtc0 a3,C0_TLBHI # put back the tlb hi reg
mtc0 v0,C0_SR # restore the status register
mtc0 a3,C0_TLBHI # put back the tlb hi reg
mtc0 v0,C0_SR # restore the status register
j ra
nop
.set reorder
@@ -353,7 +353,7 @@ FRAME(map_tlb4000,sp,0,ra)
mfc0 t1,C0_TLBHI # save current TLBPID
mfc0 v0,C0_SR # save SR and disable interrupts
mtc0 zero,C0_SR
mtc0 t2,C0_PAGEMASK # set
mtc0 t2,C0_PAGEMASK # set
mtc0 a1,C0_TLBHI # set VPN and TLBPID
mtc0 a2,C0_TLBLO0 # set PPN and access bits
mtc0 a3,C0_TLBLO1 # set PPN and access bits

8
c/src/lib/libbsp/mips/rbtx4925/console/console-io.c
View File

@@ -71,7 +71,7 @@ rtems_device_driver console_initialize(
major,
(rtems_device_minor_number) 0
);
if (status != RTEMS_SUCCESSFUL)
rtems_fatal_error_occurred(status);
@@ -168,7 +168,7 @@ rtems_device_driver console_open(
#endif
return RTEMS_SUCCESSFUL;
}
/*
* Close entry point
*/
@@ -200,7 +200,7 @@ rtems_device_driver console_read(
char *buffer;
int maximum;
int count = 0;
rw_args = (rtems_libio_rw_args_t *) arg;
buffer = rw_args->buffer;
@@ -219,7 +219,7 @@ rtems_device_driver console_read(
}
/*
* write bytes to the serial port. Stdout and stderr are the same.
* write bytes to the serial port. Stdout and stderr are the same.
*/
rtems_device_driver console_write(

64
c/src/lib/libbsp/mips/rbtx4925/start/start.S
View File

@@ -21,7 +21,7 @@ COPYRIGHT IDT CORPORATION 1996
LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
$Id$
*/
*/
/*************************************************************************
**
@@ -38,10 +38,10 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
#warning Call to boot_card has changed and needs checking.
#warning The call is "void boot_card(const char* cmdline);"
#warning Please check and remove these warnings.
.extern mon_flush_cache
#if 0
.extern mon_flush_cache
#if 0
.extern _fdata,4 /* this is defined by the linker */
.extern _edata,4 /* this is defined by the linker */
.extern _idata,4 /* this is defined by the linker */
@@ -59,8 +59,8 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
#define TMP_STKSIZE 1024
/*
** P_STACKSIZE is the size of the Prom Stack.
** the prom stack grows downward
** P_STACKSIZE is the size of the Prom Stack.
** the prom stack grows downward
*/
#define P_STACKSIZE 0x2000 /* sets stack size to 8k */
@@ -76,7 +76,7 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
** c) Clear all IntMask Enables
** d) Set kernel/disabled mode
** 2) Initialize Cause Register
** a) clear software interrupt bits
** a) clear software interrupt bits
** 3) Determine FPU installed or not
** if not, clear CoProcessor 1 usable bit
** 4) Initialize data areas. Clear bss area.
@@ -88,15 +88,15 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
** 9) Flush Instruction and Data caches
** 10) If there is a Translation Lookaside Buffer, Clear the TLB
** 11) Execute initialization code if the IDT/c library is to be used
**
**
** 12) Jump to user's "main()"
** 13) Jump to promexit
**
** IDT/C 5.x defines _R3000, IDT/C 6.x defines _R4000 internally.
** IDT/C 5.x defines _R3000, IDT/C 6.x defines _R4000 internally.
** This is used to mark code specific to R3xxx or R4xxx processors.
** IDT/C 6.x defines __mips to be the ISA level for which we're
** generating code. This is used to make sure the stack etc. is
** double word aligned, when using -mips3 (default) or -mips2,
** IDT/C 6.x defines __mips to be the ISA level for which we're
** generating code. This is used to make sure the stack etc. is
** double word aligned, when using -mips3 (default) or -mips2,
** when compiling with IDT/C6.x
**
***************************************************************************/
@@ -119,10 +119,10 @@ FRAME(start,sp,0,ra)
mtc0 v0,C0_CONFIG
/*
** check to see if a fpu is really plugged in
** check to see if a fpu is really plugged in
*/
li t3,0xaaaa5555 /* put a's and 5's in t3 */
mtc1 t3,fp0 /* try to write them into fp0 */
mtc1 t3,fp0 /* try to write them into fp0 */
mtc1 zero,fp1 /* try to write zero in fp */
mfc1 t0,fp0
mfc1 t1,fp1
@@ -140,7 +140,7 @@ FRAME(start,sp,0,ra)
mtc0 v0, C0_SR /* reset status register */
2:
la gp, _gp /* Initialize gp register (pointer to "small" data)*/
la gp, _gp /* Initialize gp register (pointer to "small" data)*/
#if 0
/* Initialize data sections from "rom" copy */
@@ -160,7 +160,7 @@ FRAME(start,sp,0,ra)
la v1,end /* end of bss */
4: sw zero,0(v0)
bltu v0,v1,4b
add v0,4
add v0,4
/************************************************************************
@@ -173,7 +173,7 @@ FRAME(start,sp,0,ra)
**
*************************************************************************/
/* For MIPS 3, we need to be sure that the stack is aligned on a
* double word boundary.
* double word boundary.
*/
andi t0, v0, 0x7
beqz t0, 11f /* Last three bits Zero, already aligned */
@@ -185,16 +185,16 @@ FRAME(start,sp,0,ra)
add v1, v0, TMP_STKSIZE /* end of bss + length of tmp stack */
sub v1, v1, (4*4) /* overhead */
move sp, v1 /* set sp to top of stack */
4: sw zero, 0(v0)
4: sw zero, 0(v0)
bltu v0, v1, 4b /* clear out temp stack */
add v0, 4
/* jal init_exc_vecs */ /* install exception handlers */
add v0, 4
/* jal init_exc_vecs */ /* install exception handlers */
/* nop */ /* MUST do before memory probes */
/* Force processor into uncached space during memory/cache probes */
la v0, 5f
li v1, K1BASE
li v1, K1BASE
or v0, v1
j v0
nop
@@ -216,7 +216,7 @@ FRAME(start,sp,0,ra)
move v0, a0 /* mem_size */
/* For MIPS 3, we need to be sure that the stack (and hence v0
* here) is aligned on a double word boundary.
* here) is aligned on a double word boundary.
*/
andi t0, v0, 0x7
beqz t0, 12f /* Last three bits Zero, already aligned */
@@ -228,9 +228,9 @@ FRAME(start,sp,0,ra)
/**************************************************************************
**
** Permanent Stack - now know top of memory, put permanent stack there
** Permanent Stack - now know top of memory, put permanent stack there
**
***************************************************************************/
***************************************************************************/
la t2, _fbss /* cache mode as linked */
and t2, 0xF0000000 /* isolate segment */
@@ -244,9 +244,9 @@ FRAME(start,sp,0,ra)
move v1, v0
subu v1, P_STACKSIZE /* clear requested stack size */
7: sw zero, 0(v1) /* clear P_STACKSIZE stack */
7: sw zero, 0(v1) /* clear P_STACKSIZE stack */
bltu v1,v0,7b
add v1, 4
add v1, 4
/* Invalidate data cache*/
@@ -286,12 +286,12 @@ FRAME(start,sp,0,ra)
2: mtc0 t2, C0_CONFIG /* set C0_Config */
nop
/* Lock first 4k of PMON into instruction cache. This includes interrupt service code which
/* Lock first 4k of PMON into instruction cache. This includes interrupt service code which
we don't want to run out of slow flash device. */
la t0,0x9fc00000
li t1, 0x1000
move t3, t0
addu t1, t0, t1
1: bge t0, t1, 2f
@@ -314,7 +314,7 @@ FRAME(start,sp,0,ra)
/*
** Clear Translation Lookaside Buffer (TLB)
*/
*/
jal init_tlb /* clear the tlb */
/*
@@ -331,7 +331,7 @@ FRAME(start,sp,0,ra)
1:
beq zero,zero,1b
nop
ENDFRAME(start)
/*
@@ -349,7 +349,7 @@ FRAME(_sys_exit,sp,0,ra)
13:
b 13b # but loop back just in-case
nop
ENDFRAME(_sys_exit)

2
c/src/lib/libbsp/mips/rbtx4925/startup/bspstart.c
View File

@@ -16,7 +16,7 @@
#include <bsp.h>
#include <libcpu/isr_entries.h>
/*
* bsp_start
*

46
c/src/lib/libbsp/mips/rbtx4925/startup/exception.S
View File

@@ -137,7 +137,7 @@ void _ISR_Handler()
FRAME(rbtx4925_ISR_Handler,sp,0,ra)
.set noreorder
#if 0
#if 0
/* Activate TX4925 PIO19 signal for diagnostics */
lui k0,0xff1f
ori k0,k0,0xf500
@@ -148,7 +148,7 @@ FRAME(rbtx4925_ISR_Handler,sp,0,ra)
ori k0,k0,0xf500
sw k1,(k0)
#endif
mfc0 k0,C0_CAUSE /* Determine if an interrupt generated this exception */
nop
and k1,k0,CAUSE_EXCMASK
@@ -190,7 +190,7 @@ _chk_int:
/* wastes a lot of stack space for context?? */
ADDIU sp,sp,-EXCP_STACK_SIZE
STREG ra, R_RA*R_SZ(sp) /* store ra on the stack */
STREG ra, R_RA*R_SZ(sp) /* store ra on the stack */
STREG v0, R_V0*R_SZ(sp)
STREG v1, R_V1*R_SZ(sp)
STREG a0, R_A0*R_SZ(sp)
@@ -207,13 +207,13 @@ _chk_int:
STREG t7, R_T7*R_SZ(sp)
mflo t0
STREG t8, R_T8*R_SZ(sp)
STREG t0, R_MDLO*R_SZ(sp)
STREG t0, R_MDLO*R_SZ(sp)
STREG t9, R_T9*R_SZ(sp)
mfhi t0
STREG gp, R_GP*R_SZ(sp)
STREG t0, R_MDHI*R_SZ(sp)
STREG t0, R_MDHI*R_SZ(sp)
STREG fp, R_FP*R_SZ(sp)
.set noat
STREG AT, R_AT*R_SZ(sp)
.set at
@@ -287,7 +287,7 @@ _chk_int:
mtc0 t1,C0_SR
nop
#endif
_ISR_Handler_cleanup:
/*
@@ -317,7 +317,7 @@ _ISR_Handler_cleanup:
* #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE )
* restore stack
* #endif
*
*
* if ( !_Context_Switch_necessary && !_ISR_Signals_to_thread_executing )
* goto the label "exit interrupt (simple case)"
*/
@@ -351,7 +351,7 @@ _ISR_Handler_cleanup:
/* save off our stack frame so the context switcher can get to it */
la t0,__exceptionStackFrame
STREG sp,(t0)
jal _Thread_Dispatch
NOP
@@ -361,7 +361,7 @@ _ISR_Handler_cleanup:
STREG zero,(t0)
NOP
/*
/*
** turn interrupts back off while we restore context so
** a badly timed interrupt won't accidentally mess things up
*/
@@ -375,7 +375,7 @@ _ISR_Handler_cleanup:
mtc0 t0, C0_SR
NOP
/*
* prepare to get out of interrupt
* return from interrupt (maybe to _ISR_Dispatch)
@@ -391,7 +391,7 @@ _ISR_Handler_exit:
LDREG t8, R_MDLO*R_SZ(sp)
LDREG t0, R_T0*R_SZ(sp)
mtlo t8
LDREG t8, R_MDHI*R_SZ(sp)
LDREG t8, R_MDHI*R_SZ(sp)
LDREG t1, R_T1*R_SZ(sp)
mthi t8
LDREG t2, R_T2*R_SZ(sp)
@@ -411,10 +411,10 @@ _ISR_Handler_exit:
LDREG a3, R_A3*R_SZ(sp)
LDREG v1, R_V1*R_SZ(sp)
LDREG v0, R_V0*R_SZ(sp)
LDREG k1, R_EPC*R_SZ(sp)
mtc0 k1,C0_EPC
.set noat
LDREG AT, R_AT*R_SZ(sp)
.set at
@@ -428,7 +428,7 @@ _ISR_Handler_quick_exit:
#if 0
.global int7_isr
.extern Interrupt_7_isr
.extern Interrupt_7_isr
int7_isr:
/* Verify interrupt is from Timer */
la k0,IRCS /* read Interrupt Current Status register */
@@ -464,7 +464,7 @@ FRAME(_BRK_Handler,sp,0,ra)
la k0,INT_CFG3
sw k1,(k0)
#endif
la k0,_brk_esr_link /* Jump to next exception handler in PMON exception chain */
lw k0,(k0)
lw k0,4(k0)
@@ -492,7 +492,7 @@ FRAME(init_exc_vecs,sp,0,ra)
.set noreorder
.extern mon_onintr
/* Install interrupt handler in PMON exception handling chain */
addiu sp,sp,-8
@@ -522,7 +522,7 @@ ENDFRAME(init_exc_vecs)
*/
FRAME(enable_int7,sp,0,ra)
.set noreorder
la t0,IRDM1 # Set interrupt controller detection mode (bits 2-3 = 0 for int 7 active low)
li t1,0x0
sw t1,(t0)
@@ -530,7 +530,7 @@ FRAME(enable_int7,sp,0,ra)
la t0,IRLVL4 # Set interrupt controller level (bit 8-10 = 2 for int 7 at level 2)
li t1,0x200
sw t1,(t0)
la t0,IRMSK # Set interrupt controller mask
li t1,0x0
sw t1,(t0)
@@ -566,7 +566,7 @@ ENDFRAME(disable_int7)
* tx4925exception:
* Diagnostic code that can be hooked to PMON interrupt handler.
* Generates pulse on PIO22 pin.
* Called from _exception code in PMON (see mips.s of PMON).
* Called from _exception code in PMON (see mips.s of PMON).
* Return address is located in k1.
*/
FRAME(tx4925exception,sp,0,ra)
@@ -609,7 +609,7 @@ ENDFRAME(tx4925exception)
.data
k1tmp: .word 0 /* Temporary strage for K1 during interrupt service */
/*************************************************************
*
* Exception handler links, used in PMON exception handler chains
@@ -619,7 +619,7 @@ k1tmp: .word 0 /* Temporary strage for K1 during interrupt service */
_int_esr_link:
.word 0
.word rbtx4925_ISR_Handler
/* Break exception service routine link */
.global _brk_esr_link
_brk_esr_link:
@@ -627,5 +627,5 @@ _brk_esr_link:
.word _BRK_Handler

16
c/src/lib/libbsp/mips/rbtx4925/startup/idttlb.S
View File

@@ -186,7 +186,7 @@ ENDFRAME(ret_tlbhi)
FRAME(ret_tlbpid,sp,0,ra)
#if __mips == 1
.set noreorder
mfc0 v0,C0_TLBHI # fetch tlb high
mfc0 v0,C0_TLBHI # fetch tlb high
nop
and v0,TLBHI_PIDMASK # isolate and position
srl v0,TLBHI_PIDSHIFT
@@ -219,8 +219,8 @@ FRAME(tlbprobe,sp,0,ra)
mfc0 t0,C0_SR /* fetch status reg */
and a0,TLBHI_VPNMASK /* isolate just the vpn */
and t0,~SR_PE /* don't inadvertantly clear pe */
mtc0 zero,C0_SR
mfc0 t1,C0_TLBHI
mtc0 zero,C0_SR
mfc0 t1,C0_TLBHI
sll a1,TLBHI_PIDSHIFT /* possition the pid */
and a1,TLBHI_PIDMASK
or a0,a1 /* build entry hi value */
@@ -271,7 +271,7 @@ ENDFRAME(tlbprobe)
FRAME(resettlb,sp,0,ra)
#if __mips == 1
.set noreorder
mfc0 t0,C0_TLBHI # fetch the current hi
mfc0 t0,C0_TLBHI # fetch the current hi
mfc0 v0,C0_SR # fetch the status reg.
li t2,K0BASE&TLBHI_VPNMASK
and v0,~SR_PE # dont inadvertantly clear PE
@@ -329,13 +329,13 @@ FRAME(map_tlb,sp,0,ra)
mtc0 zero,C0_SR
mtc0 a1,C0_TLBHI # set the hi entry
mtc0 a2,C0_TLBLO # set the lo entry
mtc0 a2,C0_TLBLO # set the lo entry
mtc0 a0,C0_INX # load the index
nop
tlbwi # put the hi/lo in tlb entry indexed
nop
mtc0 a3,C0_TLBHI # put back the tlb hi reg
mtc0 v0,C0_SR # restore the status register
mtc0 a3,C0_TLBHI # put back the tlb hi reg
mtc0 v0,C0_SR # restore the status register
j ra
nop
.set reorder
@@ -357,7 +357,7 @@ FRAME(map_tlb4000,sp,0,ra)
mfc0 t1,C0_TLBHI # save current TLBPID
mfc0 v0,C0_SR # save SR and disable interrupts
mtc0 zero,C0_SR
mtc0 t2,C0_PAGEMASK # set
mtc0 t2,C0_PAGEMASK # set
mtc0 a1,C0_TLBHI # set VPN and TLBPID
mtc0 a2,C0_TLBLO0 # set PPN and access bits
mtc0 a3,C0_TLBLO1 # set PPN and access bits

54
c/src/lib/libbsp/mips/rbtx4938/clock/yamon_api.h
View File

@@ -8,7 +8,7 @@
* ######################################################################
*
* mips_start_of_legal_notice
*
*
* Copyright (c) 2003 MIPS Technologies, Inc. All rights reserved.
*
*
@@ -52,9 +52,9 @@
* and conditions covering this code from MIPS Technologies or an authorized
* third party.
*
*
*
* mips_end_of_legal_notice
*
*
*
************************************************************************/
@@ -170,7 +170,7 @@ typedef void *t_yamon_ref;
* Parameters :
* ------------
*
* 'rc' (OUT) : Return code
* 'rc' (OUT) : Return code
*
* Return values :
* ---------------
@@ -178,7 +178,7 @@ typedef void *t_yamon_ref;
* None (never returns)
*
************************************************************************/
typedef void
typedef void
(*t_yamon_exit)(
t_yamon_uint32 rc ); /* Return code */
@@ -207,7 +207,7 @@ typedef void
* None
*
************************************************************************/
typedef void
typedef void
(*t_yamon_print)(
t_yamon_uint32 port, /* Output port (not used, always tty0) */
const char *s ); /* String to output */
@@ -238,7 +238,7 @@ typedef void
* None
*
************************************************************************/
typedef void
typedef void
(*t_yamon_print_count)(
t_yamon_uint32 port, /* Output port (not used, always tty0 */
char *s, /* String to output */
@@ -357,33 +357,33 @@ typedef void
*
* Registers an exception handler, also known as an "Exception Service
* Routine" (ESR) for the specified exception.
*
*
* Two special exception IDs are defined :
* YAMON_DEFAULT_HANDLER used for a default ESR.
* YAMON_DEFAULT_EJTAG_ESR used for EJTAG exceptions.
*
*
* The default ESR is called if no other ESR is registered
* for an exception. If no default ESR is registered, a static
* (i.e. not registered) "super default" function is invoked.
* This function prints out the registers and halts.
*
* Deregistration of an ESR may be be done by calling this function
* Deregistration of an ESR may be be done by calling this function
* with 'esr' set to NULL.
* An ESR can also be deregistered using the 'yamon_deregister_esr'
* function.
*
* An ESR may be registered even if a previously registered
* An ESR may be registered even if a previously registered
* ESR has not been deregistered. In this case the previously
* registered ESR is lost.
*
* The ESR will get called with registers in the state they were
* when the exception occurred. This includes all CP0 registers and
* The ESR will get called with registers in the state they were
* when the exception occurred. This includes all CP0 registers and
* CPU registers $0..$31, except for k0,k1 ($26,$27).
*
* In case an ESR does not want to handle the exception, it may
* call the return function passed in the 'retfunc' parameter.
*
* Case 1 : 'retfunc' called by ESR registered for the
* Case 1 : 'retfunc' called by ESR registered for the
* INTERRUPT exception.
*
* We assume an application has registered this ESR and wants
@@ -396,7 +396,7 @@ typedef void
*
* Case 3 : 'retfunc' is called by the ESR registered as default ESR.
*
* The exception will be handled as though no ESR is registered
* The exception will be handled as though no ESR is registered
* (i.e. the "super default" function is called).
*
* Parameters :
@@ -436,7 +436,7 @@ typedef t_yamon_int32
* -------------
*
* Deregisters ESR..
*
*
* Parameters :
* ------------
*
@@ -464,7 +464,7 @@ typedef t_yamon_int32
* Description :
* -------------
*
* Registers an Interrupt Service Routine (ISR) for the specified
* Registers an Interrupt Service Routine (ISR) for the specified
* CPU interrupt.
* The highest service priority is attached to HW-INT5, which is
* connected to the CPU-built-in CP0-timer. SW_INT0 gets the lowest
@@ -474,15 +474,15 @@ typedef t_yamon_int32
*
* A special ID is defined :
* YAMON_DEFAULT_HANDLER used for a default ISR.
*
*
* The default ISR is called if no other ISR is registered
* for a CPU interrupt.
*
* Deregistration of the default ISR may be done by calling
* this function with 'isr' set to NULL.
* Also, a new default ISR may be registered even if a
* Also, a new default ISR may be registered even if a
* previously registered ISR has not been deregistered.
* ISRs for specific CPU interrupts must be deregistered using
* ISRs for specific CPU interrupts must be deregistered using
* 'yamon_deregister_cpu_isr'.
*
* Parameters :
@@ -521,7 +521,7 @@ typedef t_yamon_int32
* -------------
*
* Deregisters ISR for CPU interrupt.
*
*
* Parameters :
* ------------
*
@@ -549,20 +549,20 @@ typedef t_yamon_int32
* Description :
* -------------
*
* Registers an Interrupt Service Routine (ISR) for the specified
* source in the interrupt controller.
* Registers an Interrupt Service Routine (ISR) for the specified
* source in the interrupt controller.
*
* A special ID is defined :
* YAMON_DEFAULT_HANDLER used for a default ISR.
*
*
* The default ISR is called if no other ISR is registered
* for an interrupt.
*
* Deregistration of the default ISR may be done by calling
* this function with 'isr' set to NULL.
* Also, a new default ISR may be registered even if a
* Also, a new default ISR may be registered even if a
* previously registered ISR has not been deregistered.
* ISRs for specific interrupts must be deregistered using
* ISRs for specific interrupts must be deregistered using
* 'yamon_deregister_ic_isr'.
*
* Parameters :
@@ -601,7 +601,7 @@ typedef t_yamon_int32
* -------------
*
* Deregisters ISR for source in interrupt controller.
*
*
* Parameters :
* ------------
*

8
c/src/lib/libbsp/mips/rbtx4938/console/console-io.c
View File

@@ -73,7 +73,7 @@ rtems_device_driver console_initialize(
major,
(rtems_device_minor_number) 0
);
if (status != RTEMS_SUCCESSFUL)
rtems_fatal_error_occurred(status);
@@ -174,7 +174,7 @@ rtems_device_driver console_open(
#endif
return RTEMS_SUCCESSFUL;
}
/*
* Close entry point
*/
@@ -206,7 +206,7 @@ rtems_device_driver console_read(
char *buffer;
int maximum;
int count = 0;
rw_args = (rtems_libio_rw_args_t *) arg;
buffer = rw_args->buffer;
@@ -225,7 +225,7 @@ rtems_device_driver console_read(
}
/*
* write bytes to the serial port. Stdout and stderr are the same.
* write bytes to the serial port. Stdout and stderr are the same.
*/
rtems_device_driver console_write(

54
c/src/lib/libbsp/mips/rbtx4938/console/yamon_api.h
View File

@@ -8,7 +8,7 @@
* ######################################################################
*
* mips_start_of_legal_notice
*
*
* Copyright (c) 2003 MIPS Technologies, Inc. All rights reserved.
*
*
@@ -52,9 +52,9 @@
* and conditions covering this code from MIPS Technologies or an authorized
* third party.
*
*
*
* mips_end_of_legal_notice
*
*
*
************************************************************************/
@@ -170,7 +170,7 @@ typedef void *t_yamon_ref;
* Parameters :
* ------------
*
* 'rc' (OUT) : Return code
* 'rc' (OUT) : Return code
*
* Return values :
* ---------------
@@ -178,7 +178,7 @@ typedef void *t_yamon_ref;
* None (never returns)
*
************************************************************************/
typedef void
typedef void
(*t_yamon_exit)(
t_yamon_uint32 rc ); /* Return code */
@@ -207,7 +207,7 @@ typedef void
* None
*
************************************************************************/
typedef void
typedef void
(*t_yamon_print)(
t_yamon_uint32 port, /* Output port (not used, always tty0) */
const char *s ); /* String to output */
@@ -238,7 +238,7 @@ typedef void
* None
*
************************************************************************/
typedef void
typedef void
(*t_yamon_print_count)(
t_yamon_uint32 port, /* Output port (not used, always tty0 */
char *s, /* String to output */
@@ -357,33 +357,33 @@ typedef void
*
* Registers an exception handler, also known as an "Exception Service
* Routine" (ESR) for the specified exception.
*
*
* Two special exception IDs are defined :
* YAMON_DEFAULT_HANDLER used for a default ESR.
* YAMON_DEFAULT_EJTAG_ESR used for EJTAG exceptions.
*
*
* The default ESR is called if no other ESR is registered
* for an exception. If no default ESR is registered, a static
* (i.e. not registered) "super default" function is invoked.
* This function prints out the registers and halts.
*
* Deregistration of an ESR may be be done by calling this function
* Deregistration of an ESR may be be done by calling this function
* with 'esr' set to NULL.
* An ESR can also be deregistered using the 'yamon_deregister_esr'
* function.
*
* An ESR may be registered even if a previously registered
* An ESR may be registered even if a previously registered
* ESR has not been deregistered. In this case the previously
* registered ESR is lost.
*
* The ESR will get called with registers in the state they were
* when the exception occurred. This includes all CP0 registers and
* The ESR will get called with registers in the state they were
* when the exception occurred. This includes all CP0 registers and
* CPU registers $0..$31, except for k0,k1 ($26,$27).
*
* In case an ESR does not want to handle the exception, it may
* call the return function passed in the 'retfunc' parameter.
*
* Case 1 : 'retfunc' called by ESR registered for the
* Case 1 : 'retfunc' called by ESR registered for the
* INTERRUPT exception.
*
* We assume an application has registered this ESR and wants
@@ -396,7 +396,7 @@ typedef void
*
* Case 3 : 'retfunc' is called by the ESR registered as default ESR.
*
* The exception will be handled as though no ESR is registered
* The exception will be handled as though no ESR is registered
* (i.e. the "super default" function is called).
*
* Parameters :
@@ -436,7 +436,7 @@ typedef t_yamon_int32
* -------------
*
* Deregisters ESR..
*
*
* Parameters :
* ------------
*
@@ -464,7 +464,7 @@ typedef t_yamon_int32
* Description :
* -------------
*
* Registers an Interrupt Service Routine (ISR) for the specified
* Registers an Interrupt Service Routine (ISR) for the specified
* CPU interrupt.
* The highest service priority is attached to HW-INT5, which is
* connected to the CPU-built-in CP0-timer. SW_INT0 gets the lowest
@@ -474,15 +474,15 @@ typedef t_yamon_int32
*
* A special ID is defined :
* YAMON_DEFAULT_HANDLER used for a default ISR.
*
*
* The default ISR is called if no other ISR is registered
* for a CPU interrupt.
*
* Deregistration of the default ISR may be done by calling
* this function with 'isr' set to NULL.
* Also, a new default ISR may be registered even if a
* Also, a new default ISR may be registered even if a
* previously registered ISR has not been deregistered.
* ISRs for specific CPU interrupts must be deregistered using
* ISRs for specific CPU interrupts must be deregistered using
* 'yamon_deregister_cpu_isr'.
*
* Parameters :
@@ -521,7 +521,7 @@ typedef t_yamon_int32
* -------------
*
* Deregisters ISR for CPU interrupt.
*
*
* Parameters :
* ------------
*
@@ -549,20 +549,20 @@ typedef t_yamon_int32
* Description :
* -------------
*
* Registers an Interrupt Service Routine (ISR) for the specified
* source in the interrupt controller.
* Registers an Interrupt Service Routine (ISR) for the specified
* source in the interrupt controller.
*
* A special ID is defined :
* YAMON_DEFAULT_HANDLER used for a default ISR.
*
*
* The default ISR is called if no other ISR is registered
* for an interrupt.
*
* Deregistration of the default ISR may be done by calling
* this function with 'isr' set to NULL.
* Also, a new default ISR may be registered even if a
* Also, a new default ISR may be registered even if a
* previously registered ISR has not been deregistered.
* ISRs for specific interrupts must be deregistered using
* ISRs for specific interrupts must be deregistered using
* 'yamon_deregister_ic_isr'.
*
* Parameters :
@@ -601,7 +601,7 @@ typedef t_yamon_int32
* -------------
*
* Deregisters ISR for source in interrupt controller.
*
*
* Parameters :
* ------------
*

64
c/src/lib/libbsp/mips/rbtx4938/start/start.S
View File

@@ -21,7 +21,7 @@ COPYRIGHT IDT CORPORATION 1996
LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
$Id$
*/
*/
/*************************************************************************
**
@@ -42,9 +42,9 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
/* The following include file was deprecated */
/* #include <idtmon.h> */
.extern mon_flush_cache
.extern mon_flush_cache
#if 0
#if 0
.extern _fdata,4 /* this is defined by the linker */
.extern _edata,4 /* this is defined by the linker */
.extern _idata,4 /* this is defined by the linker */
@@ -59,11 +59,11 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
#define HARD_CODED_MEM_SIZE 0x1000000 /* RBTX4938 has 16 megabytes of RAM */
#define PMON_VECTOR 0xbfc00500
#define TMP_STKSIZE 1024
#define TMP_STKSIZE 1024
/*
** P_STACKSIZE is the size of the Prom Stack.
** the prom stack grows downward
** P_STACKSIZE is the size of the Prom Stack.
** the prom stack grows downward
*/
#define P_STACKSIZE 0x2000 /* sets stack size to 8k */
@@ -78,7 +78,7 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
** c) Clear all IntMask Enables
** d) Set kernel/disabled mode
** 2) Initialize Cause Register
** a) clear software interrupt bits
** a) clear software interrupt bits
** 3) Determine FPU installed or not
** if not, clear CoProcessor 1 usable bit
** 4) Initialize data areas. Clear bss area.
@@ -90,15 +90,15 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
** 9) Flush Instruction and Data caches
** 10) If there is a Translation Lookaside Buffer, Clear the TLB
** 11) Execute initialization code if the IDT/c library is to be used
**
**
** 12) Jump to user's "main()"
** 13) Jump to promexit
**
** IDT/C 5.x defines _R3000, IDT/C 6.x defines _R4000 internally.
** IDT/C 5.x defines _R3000, IDT/C 6.x defines _R4000 internally.
** This is used to mark code specific to R3xxx or R4xxx processors.
** IDT/C 6.x defines __mips to be the ISA level for which we're
** generating code. This is used to make sure the stack etc. is
** double word aligned, when using -mips3 (default) or -mips2,
** IDT/C 6.x defines __mips to be the ISA level for which we're
** generating code. This is used to make sure the stack etc. is
** double word aligned, when using -mips3 (default) or -mips2,
** when compiling with IDT/C6.x
**
***************************************************************************/
@@ -121,10 +121,10 @@ FRAME(start,sp,0,ra)
mtc0 v0,C0_CONFIG
/*
** check to see if a fpu is really plugged in
** check to see if a fpu is really plugged in
*/
li t3,0xaaaa5555 /* put a's and 5's in t3 */
mtc1 t3,fp0 /* try to write them into fp0 */
mtc1 t3,fp0 /* try to write them into fp0 */
mtc1 zero,fp1 /* try to write zero in fp */
mfc1 t0,fp0
mfc1 t1,fp1
@@ -142,7 +142,7 @@ FRAME(start,sp,0,ra)
mtc0 v0, C0_SR /* reset status register */
2:
la gp, _gp /* Initialize gp register (pointer to "small" data)*/
la gp, _gp /* Initialize gp register (pointer to "small" data)*/
#if 0
/* Initialize data sections from "rom" copy */
@@ -162,7 +162,7 @@ FRAME(start,sp,0,ra)
la v1,end /* end of bss */
4: sw zero,0(v0)
bltu v0,v1,4b
add v0,4
add v0,4
/************************************************************************
@@ -175,7 +175,7 @@ FRAME(start,sp,0,ra)
**
*************************************************************************/
/* For MIPS 3, we need to be sure that the stack is aligned on a
* double word boundary.
* double word boundary.
*/
andi t0, v0, 0x7
beqz t0, 11f /* Last three bits Zero, already aligned */
@@ -187,16 +187,16 @@ FRAME(start,sp,0,ra)
add v1, v0, TMP_STKSIZE /* end of bss + length of tmp stack */
sub v1, v1, (4*4) /* overhead */
move sp, v1 /* set sp to top of stack */
4: sw zero, 0(v0)
4: sw zero, 0(v0)
bltu v0, v1, 4b /* clear out temp stack */
add v0, 4
/* jal init_exc_vecs */ /* install exception handlers */
add v0, 4
/* jal init_exc_vecs */ /* install exception handlers */
/* nop */ /* MUST do before memory probes */
/* Force processor into uncached space during memory/cache probes */
la v0, 5f
li v1, K1BASE
li v1, K1BASE
or v0, v1
j v0
nop
@@ -218,7 +218,7 @@ FRAME(start,sp,0,ra)
move v0, a0 /* mem_size */
/* For MIPS 3, we need to be sure that the stack (and hence v0
* here) is aligned on a double word boundary.
* here) is aligned on a double word boundary.
*/
andi t0, v0, 0x7
beqz t0, 12f /* Last three bits Zero, already aligned */
@@ -230,9 +230,9 @@ FRAME(start,sp,0,ra)
/**************************************************************************
**
** Permanent Stack - now know top of memory, put permanent stack there
** Permanent Stack - now know top of memory, put permanent stack there
**
***************************************************************************/
***************************************************************************/
la t2, _fbss /* cache mode as linked */
and t2, 0xF0000000 /* isolate segment */
@@ -246,9 +246,9 @@ FRAME(start,sp,0,ra)
move v1, v0
subu v1, P_STACKSIZE /* clear requested stack size */
7: sw zero, 0(v1) /* clear P_STACKSIZE stack */
7: sw zero, 0(v1) /* clear P_STACKSIZE stack */
bltu v1,v0,7b
add v1, 4
add v1, 4
/* Invalidate data cache*/
@@ -288,12 +288,12 @@ FRAME(start,sp,0,ra)
2: mtc0 t2, C0_CONFIG /* set C0_Config */
nop
/* Lock first 4k of PMON into instruction cache. This includes interrupt service code which
/* Lock first 4k of PMON into instruction cache. This includes interrupt service code which
we don't want to run out of slow flash device. */
la t0,0x9fc00000
li t1, 0x1000
move t3, t0
addu t1, t0, t1
1: bge t0, t1, 2f
@@ -316,7 +316,7 @@ FRAME(start,sp,0,ra)
/*
** Clear Translation Lookaside Buffer (TLB)
*/
*/
jal init_tlb /* clear the tlb */
/*
@@ -333,7 +333,7 @@ FRAME(start,sp,0,ra)
1:
beq zero,zero,1b
nop
ENDFRAME(start)
/*
@@ -351,7 +351,7 @@ FRAME(_sys_exit,sp,0,ra)
13:
b 13b # but loop back just in-case
nop
ENDFRAME(_sys_exit)

46
c/src/lib/libbsp/mips/rbtx4938/startup/exception.S
View File

@@ -137,7 +137,7 @@ void _ISR_Handler()
FRAME(rbtx4938_ISR_Handler,sp,0,ra)
.set noreorder
#if 0
#if 0
/* Activate TX4938 PIO19 signal for diagnostics */
lui k0,0xff1f
ori k0,k0,0xf500
@@ -148,7 +148,7 @@ FRAME(rbtx4938_ISR_Handler,sp,0,ra)
ori k0,k0,0xf500
sw k1,(k0)
#endif
mfc0 k0,C0_CAUSE /* Determine if an interrupt generated this exception */
nop
and k1,k0,CAUSE_EXCMASK
@@ -190,7 +190,7 @@ _chk_int:
/* wastes a lot of stack space for context?? */
ADDIU sp,sp,-EXCP_STACK_SIZE
STREG ra, R_RA*R_SZ(sp) /* store ra on the stack */
STREG ra, R_RA*R_SZ(sp) /* store ra on the stack */
STREG v0, R_V0*R_SZ(sp)
STREG v1, R_V1*R_SZ(sp)
STREG a0, R_A0*R_SZ(sp)
@@ -207,13 +207,13 @@ _chk_int:
STREG t7, R_T7*R_SZ(sp)
mflo t0
STREG t8, R_T8*R_SZ(sp)
STREG t0, R_MDLO*R_SZ(sp)
STREG t0, R_MDLO*R_SZ(sp)
STREG t9, R_T9*R_SZ(sp)
mfhi t0
STREG gp, R_GP*R_SZ(sp)
STREG t0, R_MDHI*R_SZ(sp)
STREG t0, R_MDHI*R_SZ(sp)
STREG fp, R_FP*R_SZ(sp)
.set noat
STREG AT, R_AT*R_SZ(sp)
.set at
@@ -287,7 +287,7 @@ _chk_int:
mtc0 t1,C0_SR
nop
#endif
_ISR_Handler_cleanup:
/*
@@ -317,7 +317,7 @@ _ISR_Handler_cleanup:
* #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE )
* restore stack
* #endif
*
*
* if ( !_Context_Switch_necessary && !_ISR_Signals_to_thread_executing )
* goto the label "exit interrupt (simple case)"
*/
@@ -351,7 +351,7 @@ _ISR_Handler_cleanup:
/* save off our stack frame so the context switcher can get to it */
la t0,__exceptionStackFrame
STREG sp,(t0)
jal _Thread_Dispatch
NOP
@@ -361,7 +361,7 @@ _ISR_Handler_cleanup:
STREG zero,(t0)
NOP
/*
/*
** turn interrupts back off while we restore context so
** a badly timed interrupt won't accidentally mess things up
*/
@@ -375,7 +375,7 @@ _ISR_Handler_cleanup:
mtc0 t0, C0_SR
NOP
/*
* prepare to get out of interrupt
* return from interrupt (maybe to _ISR_Dispatch)
@@ -391,7 +391,7 @@ _ISR_Handler_exit:
LDREG t8, R_MDLO*R_SZ(sp)
LDREG t0, R_T0*R_SZ(sp)
mtlo t8
LDREG t8, R_MDHI*R_SZ(sp)
LDREG t8, R_MDHI*R_SZ(sp)
LDREG t1, R_T1*R_SZ(sp)
mthi t8
LDREG t2, R_T2*R_SZ(sp)
@@ -411,10 +411,10 @@ _ISR_Handler_exit:
LDREG a3, R_A3*R_SZ(sp)
LDREG v1, R_V1*R_SZ(sp)
LDREG v0, R_V0*R_SZ(sp)
LDREG k1, R_EPC*R_SZ(sp)
mtc0 k1,C0_EPC
.set noat
LDREG AT, R_AT*R_SZ(sp)
.set at
@@ -428,7 +428,7 @@ _ISR_Handler_quick_exit:
#if 0
.global int7_isr
.extern Interrupt_7_isr
.extern Interrupt_7_isr
int7_isr:
/* Verify interrupt is from Timer */
la k0,IRCS /* read Interrupt Current Status register */
@@ -464,7 +464,7 @@ FRAME(_BRK_Handler,sp,0,ra)
la k0,INT_CFG3
sw k1,(k0)
#endif
la k0,_brk_esr_link /* Jump to next exception handler in PMON exception chain */
lw k0,(k0)
lw k0,4(k0)
@@ -492,7 +492,7 @@ FRAME(init_exc_vecs,sp,0,ra)
.set noreorder
.extern mon_onintr
/* Install interrupt handler in PMON exception handling chain */
addiu sp,sp,-8
@@ -522,7 +522,7 @@ ENDFRAME(init_exc_vecs)
*/
FRAME(enable_int7,sp,0,ra)
.set noreorder
la t0,IRDM1 # Set interrupt controller detection mode (bits 2-3 = 0 for int 7 active low)
li t1,0x0
sw t1,(t0)
@@ -530,7 +530,7 @@ FRAME(enable_int7,sp,0,ra)
la t0,IRLVL4 # Set interrupt controller level (bit 8-10 = 2 for int 7 at level 2)
li t1,0x200
sw t1,(t0)
la t0,IRMSK # Set interrupt controller mask
li t1,0x0
sw t1,(t0)
@@ -566,7 +566,7 @@ ENDFRAME(disable_int7)
* tx4938exception:
* Diagnostic code that can be hooked to PMON interrupt handler.
* Generates pulse on PIO22 pin.
* Called from _exception code in PMON (see mips.s of PMON).
* Called from _exception code in PMON (see mips.s of PMON).
* Return address is located in k1.
*/
FRAME(tx4938exception,sp,0,ra)
@@ -609,7 +609,7 @@ ENDFRAME(tx4938exception)
.data
k1tmp: .word 0 /* Temporary strage for K1 during interrupt service */
/*************************************************************
*
* Exception handler links, used in PMON exception handler chains
@@ -619,7 +619,7 @@ k1tmp: .word 0 /* Temporary strage for K1 during interrupt service */
_int_esr_link:
.word 0
.word rbtx4938_ISR_Handler
/* Break exception service routine link */
.global _brk_esr_link
_brk_esr_link:
@@ -627,5 +627,5 @@ _brk_esr_link:
.word _BRK_Handler

16
c/src/lib/libbsp/mips/rbtx4938/startup/idttlb.S
View File

@@ -186,7 +186,7 @@ ENDFRAME(ret_tlbhi)
FRAME(ret_tlbpid,sp,0,ra)
#if __mips == 1
.set noreorder
mfc0 v0,C0_TLBHI # fetch tlb high
mfc0 v0,C0_TLBHI # fetch tlb high
nop
and v0,TLBHI_PIDMASK # isolate and position
srl v0,TLBHI_PIDSHIFT
@@ -219,8 +219,8 @@ FRAME(tlbprobe,sp,0,ra)
mfc0 t0,C0_SR /* fetch status reg */
and a0,TLBHI_VPNMASK /* isolate just the vpn */
and t0,~SR_PE /* don't inadvertantly clear pe */
mtc0 zero,C0_SR
mfc0 t1,C0_TLBHI
mtc0 zero,C0_SR
mfc0 t1,C0_TLBHI
sll a1,TLBHI_PIDSHIFT /* possition the pid */
and a1,TLBHI_PIDMASK
or a0,a1 /* build entry hi value */
@@ -271,7 +271,7 @@ ENDFRAME(tlbprobe)
FRAME(resettlb,sp,0,ra)
#if __mips == 1
.set noreorder
mfc0 t0,C0_TLBHI # fetch the current hi
mfc0 t0,C0_TLBHI # fetch the current hi
mfc0 v0,C0_SR # fetch the status reg.
li t2,K0BASE&TLBHI_VPNMASK
and v0,~SR_PE # dont inadvertantly clear PE
@@ -329,13 +329,13 @@ FRAME(map_tlb,sp,0,ra)
mtc0 zero,C0_SR
mtc0 a1,C0_TLBHI # set the hi entry
mtc0 a2,C0_TLBLO # set the lo entry
mtc0 a2,C0_TLBLO # set the lo entry
mtc0 a0,C0_INX # load the index
nop
tlbwi # put the hi/lo in tlb entry indexed
nop
mtc0 a3,C0_TLBHI # put back the tlb hi reg
mtc0 v0,C0_SR # restore the status register
mtc0 a3,C0_TLBHI # put back the tlb hi reg
mtc0 v0,C0_SR # restore the status register
j ra
nop
.set reorder
@@ -357,7 +357,7 @@ FRAME(map_tlb4000,sp,0,ra)
mfc0 t1,C0_TLBHI # save current TLBPID
mfc0 v0,C0_SR # save SR and disable interrupts
mtc0 zero,C0_SR
mtc0 t2,C0_PAGEMASK # set
mtc0 t2,C0_PAGEMASK # set
mtc0 a1,C0_TLBHI # set VPN and TLBPID
mtc0 a2,C0_TLBLO0 # set PPN and access bits
mtc0 a3,C0_TLBLO1 # set PPN and access bits

14
c/src/lib/libbsp/mips/shared/gdbstub/mips-stub.c
View File

@@ -118,7 +118,7 @@
* As an example, "0* " means the same thing as "0000".
*
*******************************************************************************/
#include <string.h>
#include <signal.h>
@@ -255,7 +255,7 @@ static struct z0break z0break_arr[BREAKNUM];
static struct z0break *z0break_avail = NULL;
static struct z0break *z0break_list = NULL;
/*
* Convert an int to hex.
*/
@@ -334,7 +334,7 @@ mem2hex (void *_addr, int length, char *buf)
return (buf);
}
/*
* Convert a hex character to an int.
*/
@@ -531,7 +531,7 @@ bin2mem (
return mem;
}
/*
* Scan the input stream for a sequence for the form $<data>#<checksum>.
*/
@@ -649,7 +649,7 @@ putpacket (char *buffer)
while (getAck () != '+');
}
/*
* Saved instruction data for single step support
*/
@@ -808,7 +808,7 @@ doSStep (void)
return;
}
/*
* Translate the R4600 exception code into a Unix-compatible signal.
*/
@@ -917,7 +917,7 @@ void gdb_stub_report_exception_info(
*optr++ = '\0';
}
/*
* Scratch frame used to retrieve contexts for different threads, so as

22
c/src/lib/libbsp/powerpc/gen5200/bestcomm/bestcomm_api.c
View File

@@ -1,17 +1,17 @@
/******************************************************************************
*
* Copyright (c) 2004 Freescale Semiconductor, Inc.
*
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
@@ -52,7 +52,7 @@ static const char* const TaskVersionString = "BestComm API v2.2 20041209";
/*
* Hidden API data per task.
*/
static BDIdx BDHead[MAX_TASKS];
static BDIdx BDTail[MAX_TASKS];
@@ -103,7 +103,7 @@ const char *TaskVersion(void)
* \returns TASK_ERR_NO_ERR on successful initialization.
* or TASK_ERR_API_ALREADY_INITIALIZED.
*
* This function is only used with physical addresses.
* This function is only used with physical addresses.
*
* This function will also initialize API internal variables. The return
* value TASK_ERR_API_ALREADY_INITIALIZED is intended to help determine if
@@ -116,12 +116,12 @@ int TasksInitAPI(uint8 *MBarRef)
* for use by other functions.
*/
MBarGlobal = MBarRef;
/*
* The offset is 0 if physical and virtual are the same.
*/
MBarPhysOffsetGlobal = 0;
/*
* IF API has not been initialized yet then...
* Make sure all BestComm interrupts are disabled and not pending.
@@ -131,7 +131,7 @@ int TasksInitAPI(uint8 *MBarRef)
*/
return TASK_ERR_NO_ERR;
}
/*!
* \brief Initialize the API when virtual memory is used.
* \param MBarRef Reference pointer to the device register memory
@@ -158,8 +158,8 @@ int TasksInitAPI_VM(uint8 *MBarRef, uint8 *MBarPhys)
* for use by other functions.
*/
MBarGlobal = MBarRef;
MBarPhysOffsetGlobal = MBarPhys - MBarRef;
MBarPhysOffsetGlobal = MBarPhys - MBarRef;
/*
* If API has not been initialized yet then...
* Make sure all BestComm interrupts are disabled and not pending.
@@ -169,7 +169,7 @@ int TasksInitAPI_VM(uint8 *MBarRef, uint8 *MBarPhys)
*/
return TASK_ERR_NO_ERR;
}
/*!
* \brief \em Deprecated
* \param sdma Base address of the BestComm register set

8
c/src/lib/libbsp/powerpc/gen5200/bestcomm/bestcomm_api.h
View File

@@ -4,17 +4,17 @@
/******************************************************************************
*
* Copyright (c) 2004 Freescale Semiconductor, Inc.
*
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
@@ -247,7 +247,7 @@ typedef struct {
#include "bestcomm_priv.h"
#include "dma_image.capi.h"
/*!
* \brief Initialize a single task.
* \param TaskName Type of task to initialize. E.g. PCI transmit,

6
c/src/lib/libbsp/powerpc/gen5200/bestcomm/bestcomm_priv.h
View File

@@ -4,17 +4,17 @@
/******************************************************************************
*
* Copyright (c) 2004 Freescale Semiconductor, Inc.
*
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL

6
c/src/lib/libbsp/powerpc/gen5200/bestcomm/dma_image.c
View File

@@ -1,17 +1,17 @@
/******************************************************************************
*
* Copyright (c) 2004 Freescale Semiconductor, Inc.
*
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL

6
c/src/lib/libbsp/powerpc/gen5200/bestcomm/dma_image.capi.h
View File

@@ -4,17 +4,17 @@
/******************************************************************************
*
* Copyright (c) 2004 Freescale Semiconductor, Inc.
*
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL

8
c/src/lib/libbsp/powerpc/gen5200/bestcomm/dma_image.h
View File

@@ -4,17 +4,17 @@
/******************************************************************************
*
* Copyright (c) 2004 Freescale Semiconductor, Inc.
*
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
@@ -46,7 +46,7 @@ void init_dma_image_TASK_GEN_DP_BD_0(uint8 *vMem_taskBar, sint64 vMemOffset);
void init_dma_image_TASK_GEN_DP_BD_1(uint8 *vMem_taskBar, sint64 vMemOffset);
/* MBAR_TASK_TABLE is the first address of task table */
#ifndef MBAR_TASK_TABLE
#ifndef MBAR_TASK_TABLE
#define MBAR_TASK_TABLE 0xf0008000UL
#endif

198
c/src/lib/libbsp/powerpc/gen5200/bestcomm/dma_image.reloc.c
View File

@@ -1,17 +1,17 @@
/******************************************************************************
*
* Copyright (c) 2004 Freescale Semiconductor, Inc.
*
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
@@ -40,145 +40,145 @@ uint32 taskTable[] = {
0x00000238,
0x00000700, /* Task 0 Variable Table */
0x00000f27, /* Task 0 Function Descriptor Table & Flags */
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00001000, /* Task 0 context save space */
0x00000000,
0x00000000,
/* Task1(TASK_PCI_RX): Start of Entry -> 0xf0008020 */
0x0000023c, /* Task 0 Descriptor Table */
0x00000268,
0x00000780, /* Task 0 Variable Table */
0x00000027, /* No FDT */
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00001050, /* Task 0 context save space */
0x00000000,
0x00000000,
/* Task2(TASK_FEC_TX): Start of Entry -> 0xf0008040 */
0x0000026c, /* Task 0 Descriptor Table */
0x000002f8,
0x00000800, /* Task 0 Variable Table */
0x00000f27, /* Task 0 Function Descriptor Table & Flags */
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x000010a0, /* Task 0 context save space */
0x00000000,
0x00000000,
/* Task3(TASK_FEC_RX): Start of Entry -> 0xf0008060 */
0x000002fc, /* Task 0 Descriptor Table */
0x00000358,
0x00000880, /* Task 0 Variable Table */
0x00000f27, /* Task 0 Function Descriptor Table & Flags */
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x000010f0, /* Task 0 context save space */
0x00000000,
0x00000000,
/* Task4(TASK_LPC): Start of Entry -> 0xf0008080 */
0x0000035c, /* Task 0 Descriptor Table */
0x0000038c,
0x00000900, /* Task 0 Variable Table */
0x00000027, /* No FDT */
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00001140, /* Task 0 context save space */
0x00000000,
0x00000000,
/* Task5(TASK_ATA): Start of Entry -> 0xf00080a0 */
0x00000390, /* Task 0 Descriptor Table */
0x000003c4,
0x00000980, /* Task 0 Variable Table */
0x00000f27, /* Task 0 Function Descriptor Table & Flags */
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00001190, /* Task 0 context save space */
0x00000000,
0x00000000,
/* Task6(TASK_CRC16_DP_0): Start of Entry -> 0xf00080c0 */
0x000003c8, /* Task 0 Descriptor Table */
0x0000040c,
0x00000a00, /* Task 0 Variable Table */
0x00000f27, /* Task 0 Function Descriptor Table & Flags */
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x000011e0, /* Task 0 context save space */
0x00000000,
0x00000000,
/* Task7(TASK_CRC16_DP_1): Start of Entry -> 0xf00080e0 */
0x00000410, /* Task 0 Descriptor Table */
0x00000454,
0x00000a80, /* Task 0 Variable Table */
0x00000f27, /* Task 0 Function Descriptor Table & Flags */
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00001230, /* Task 0 context save space */
0x00000000,
0x00000000,
/* Task8(TASK_GEN_DP_0): Start of Entry -> 0xf0008100 */
0x00000458, /* Task 0 Descriptor Table */
0x00000488,
0x00000b00, /* Task 0 Variable Table */
0x00000027, /* No FDT */
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00001280, /* Task 0 context save space */
0x00000000,
0x00000000,
/* Task9(TASK_GEN_DP_1): Start of Entry -> 0xf0008120 */
0x0000048c, /* Task 0 Descriptor Table */
0x000004bc,
0x00000b80, /* Task 0 Variable Table */
0x00000027, /* No FDT */
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x000012d0, /* Task 0 context save space */
0x00000000,
0x00000000,
/* Task10(TASK_GEN_DP_2): Start of Entry -> 0xf0008140 */
0x000004c0, /* Task 0 Descriptor Table */
0x000004f0,
0x00000c00, /* Task 0 Variable Table */
0x00000027, /* No FDT */
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00001320, /* Task 0 context save space */
0x00000000,
0x00000000,
/* Task11(TASK_GEN_DP_3): Start of Entry -> 0xf0008160 */
0x000004f4, /* Task 0 Descriptor Table */
0x00000524,
0x00000c80, /* Task 0 Variable Table */
0x00000027, /* No FDT */
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00001370, /* Task 0 context save space */
0x00000000,
0x00000000,
/* Task12(TASK_GEN_TX_BD): Start of Entry -> 0xf0008180 */
0x00000528, /* Task 0 Descriptor Table */
0x00000560,
0x00000d00, /* Task 0 Variable Table */
0x00000f27, /* Task 0 Function Descriptor Table & Flags */
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x000013c0, /* Task 0 context save space */
0x00000000,
0x00000000,
/* Task13(TASK_GEN_RX_BD): Start of Entry -> 0xf00081a0 */
0x00000564, /* Task 0 Descriptor Table */
0x00000594,
0x00000d80, /* Task 0 Variable Table */
0x00000f27, /* Task 0 Function Descriptor Table & Flags */
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00001410, /* Task 0 context save space */
0x00000000,
0x00000000,
/* Task14(TASK_GEN_DP_BD_0): Start of Entry -> 0xf00081c0 */
0x00000598, /* Task 0 Descriptor Table */
0x000005cc,
0x00000e00, /* Task 0 Variable Table */
0x00000f27, /* Task 0 Function Descriptor Table & Flags */
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00001460, /* Task 0 context save space */
0x00000000,
0x00000000,
/* Task15(TASK_GEN_DP_BD_1): Start of Entry -> 0xf00081e0 */
0x000005d0, /* Task 0 Descriptor Table */
0x00000604,
0x00000e80, /* Task 0 Variable Table */
0x00000f27, /* Task 0 Function Descriptor Table & Flags */
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x000014b0, /* Task 0 context save space */
0x00000000,
0x00000000,
/* Task0(TASK_PCI_TX): Start of TDT -> 0xf0008200 */
0xc080601b, /* 0000(../LIB_incl/hdplx.sc:167): LCDEXT: idx0 = var1, idx1 = var0; ; idx0 += inc3, idx1 += inc3 */
@@ -1047,54 +1047,54 @@ uint32 taskTable[] = {
0x00000000, /* inc[7] */
/* Task0(TASK_PCI_TX): Start of FDT -> 0xf0008f00 */
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0xa0045670, /* load_acc(), EU# 3 */
0x80045670, /* unload_acc(), EU# 3 */
0x21800000, /* and(), EU# 3 */

8
c/src/lib/libbsp/powerpc/gen5200/bestcomm/include/mgt5200/mgt5200.h
View File

@@ -4,17 +4,17 @@
/******************************************************************************
*
* Copyright (c) 2004 Freescale Semiconductor, Inc.
*
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
@@ -24,7 +24,7 @@
* OTHER DEALINGS IN THE SOFTWARE.
*
******************************************************************************/
#define MBAR_CS 0x0000
#define MBAR_SDRAM 0x0100
#define MBAR_CDM 0x0200

12
c/src/lib/libbsp/powerpc/gen5200/bestcomm/include/mgt5200/sdma.h
View File

@@ -4,17 +4,17 @@
/******************************************************************************
*
* Copyright (c) 2004 Freescale Semiconductor, Inc.
*
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
@@ -34,10 +34,10 @@ typedef struct sdma_register_set {
volatile uint8 IntVect1; /* MBAR_SDMA + 0x10 sdPtd */
volatile uint8 IntVect2; /* MBAR_SDMA + 0x11 sdPtd */
volatile uint16 PtdCntrl; /* MBAR_SDMA + 0x12 sdPtd */
volatile uint32 IntPend; /* MBAR_SDMA + 0x14 sdPtd */
volatile uint32 IntMask; /* MBAR_SDMA + 0x18 sdPtd */
volatile uint32 TCR01; /* MBAR_SDMA + 0x1c sdPtd */
volatile uint32 TCR23; /* MBAR_SDMA + 0x20 sdPtd */
volatile uint32 TCR45; /* MBAR_SDMA + 0x24 sdPtd */
@@ -46,7 +46,7 @@ typedef struct sdma_register_set {
volatile uint32 TCRAB; /* MBAR_SDMA + 0x30 sdPtd */
volatile uint32 TCRCD; /* MBAR_SDMA + 0x34 sdPtd */
volatile uint32 TCREF; /* MBAR_SDMA + 0x38 sdPtd */
volatile uint8 IPR0; /* MBAR_SDMA + 0x3c sdPtd */
volatile uint8 IPR1; /* MBAR_SDMA + 0x3d sdPtd */
volatile uint8 IPR2; /* MBAR_SDMA + 0x3e sdPtd */

6
c/src/lib/libbsp/powerpc/gen5200/bestcomm/include/ppctypes.h
View File

@@ -4,17 +4,17 @@
/******************************************************************************
*
* Copyright (c) 2004 Freescale Semiconductor, Inc.
*
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL

8
c/src/lib/libbsp/powerpc/gen5200/bestcomm/load_task.c
View File

@@ -1,17 +1,17 @@
/******************************************************************************
*
* Copyright (c) 2004 Freescale Semiconductor, Inc.
*
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
@@ -81,6 +81,6 @@ void TasksLoadImage(sdma_regs *sdma)
tt->fdt = (sdma->taskBar & 0xFFFFFF00) + tt->fdt;
tt->context += sdma->taskBar;
}
SramOffsetGlobal = taskTableBytes;
}

8
c/src/lib/libbsp/powerpc/gen5200/bestcomm/task_api/bestcomm_api_mem.h
View File

@@ -4,17 +4,17 @@
/******************************************************************************
*
* Copyright (c) 2004 Freescale Semiconductor, Inc.
*
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
@@ -28,7 +28,7 @@
#include "../include/mgt5200/mgt5200.h"
/*
* An extern global variable is used here for the MBAR since it must
* An extern global variable is used here for the MBAR since it must
* be passed into the API for processes that use virtual memory.
*/
extern uint8 *MBarGlobal;

10
c/src/lib/libbsp/powerpc/gen5200/bestcomm/task_api/bestcomm_cntrl.h
View File

@@ -4,17 +4,17 @@
/******************************************************************************
*
* Copyright (c) 2004 Freescale Semiconductor, Inc.
*
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
@@ -26,7 +26,7 @@
******************************************************************************/
/*******************************************************************************
* Defines to control SmartDMA and its tasks. These defines are used for the
* Defines to control SmartDMA and its tasks. These defines are used for the
* task build process to minimize disconnects at the task/driver interface.
******************************************************************************/
@@ -49,7 +49,7 @@
#define SDMA_DRD_MASK_FLAGS 0x0C000000 /* BD_FLAGS flag bits */
#define SDMA_DRD_MASK_LENGTH 0x03FFFFFF /* BD_FLAGS length mask */
#define SDMA_BD_BIT_READY 30 /* Status BD ready bit */
#ifdef SAS_COMPILE
#ifdef SAS_COMPILE
#define SDMA_BD_MASK_READY constant(1<<SDMA_BD_BIT_READY)
#else
#define SDMA_BD_MASK_READY (1<<SDMA_BD_BIT_READY)

10
c/src/lib/libbsp/powerpc/gen5200/bestcomm/task_api/tasksetup_bdtable.h
View File

@@ -4,17 +4,17 @@
/******************************************************************************
*
* Copyright (c) 2004 Freescale Semiconductor, Inc.
*
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
@@ -65,7 +65,7 @@ typedef struct {
* cannot use this to track a task's BD pointer.
*/
uint16 currBDInUse; /* Current number of buffer descriptors assigned but*/
/* not released yet. */
/* not released yet. */
} TaskBDIdxTable_t;
typedef enum {
@@ -77,7 +77,7 @@ typedef enum {
* Allocates BD table if needed and updates the BD index table.
* Do we want to hide this from the C API since it operates on task API?
*/
void TaskSetup_BDTable(volatile uint32 *BasePtr,
void TaskSetup_BDTable(volatile uint32 *BasePtr,
volatile uint32 *LastPtr,
volatile uint32 *StartPtr,
int TaskNum, uint32 NumBD, uint16 MaxBD,

8
c/src/lib/libbsp/powerpc/gen5200/bestcomm/task_api/tasksetup_general.h
View File

@@ -1,17 +1,17 @@
/******************************************************************************
*
* Copyright (c) 2004 Freescale Semiconductor, Inc.
*
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
@@ -373,7 +373,7 @@ TaskId TASKSETUP_NAME(TASK_API *TaskAPI,
*(TaskAPI->DRD[i]) = (*(TaskAPI->DRD[i]) & DRD_INIT_MASK)
| (TaskSetupParams->Initiator << DRD_INIT_OFFSET);
}
if ((*(TaskAPI->DRD[i]) & DRD_EXT_FLAG) != 0)
{
ext = 1;

6
c/src/lib/libbsp/powerpc/gen5200/bestcomm/tasksetup_bdtable.c
View File

@@ -1,17 +1,17 @@
/******************************************************************************
*
* Copyright (c) 2004 Freescale Semiconductor, Inc.
*
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL

2
c/src/lib/libbsp/powerpc/gen5200/clock/clock.c
View File

@@ -147,7 +147,7 @@ void mpc5200_init_gpt(uint32_t gpt_no)
struct mpc5200_gpt *gpt = (struct mpc5200_gpt *)(&mpc5200.gpt[gpt_no]);
gpt->status = GPT_STATUS_RESET;
gpt->emsel = GPT_EMSEL_CE | GPT_EMSEL_ST_CONT | GPT_EMSEL_INTEN |
gpt->emsel = GPT_EMSEL_CE | GPT_EMSEL_ST_CONT | GPT_EMSEL_INTEN |
GPT_EMSEL_GPIO_OUT_HIGH | GPT_EMSEL_TIMER_MS_GPIO;
}

4
c/src/lib/libbsp/powerpc/gen5200/i2c/i2c.c
View File

@@ -72,7 +72,7 @@ i2c_transfer_wait_sema(i2c_bus_number bus, i2c_message *msg, int nmsg)
);
if (sc != RTEMS_SUCCESSFUL)
return I2C_RESOURCE_NOT_AVAILABLE;
sc = i2c_transfer(bus, nmsg, msg,
sc = i2c_transfer(bus, nmsg, msg,
i2c_transfer_sema_done_func, &sema);
if (sc != RTEMS_SUCCESSFUL)
{
@@ -107,7 +107,7 @@ i2c_transfer_wait_poll(i2c_bus_number bus, i2c_message *msg, int nmsg)
volatile bool poll_done_flag;
rtems_status_code sc;
poll_done_flag = false;
sc = i2c_transfer(bus, nmsg, msg,
sc = i2c_transfer(bus, nmsg, msg,
i2c_transfer_poll_done_func,(void *)&poll_done_flag);
if (sc != RTEMS_SUCCESSFUL)
return sc;

2
c/src/lib/libbsp/powerpc/gen5200/i2c/i2cdrv.c
View File

@@ -140,7 +140,7 @@ i2cdrv_unload(void)
i2cdrv_bus_clock_div_current = i2cdrv_bus_clock_div[qel->bus];
mpc5200mbus_select_clock_divider(&mbus[qel->bus], i2cdrv_bus_clock_div_current);
}
sc = mpc5200mbus_i2c_transfer(&mbus[qel->bus], qel->nmsg, qel->msg,
sc = mpc5200mbus_i2c_transfer(&mbus[qel->bus], qel->nmsg, qel->msg,
i2cdrv_done,qel);
if (sc != RTEMS_SUCCESSFUL)
{

68
c/src/lib/libbsp/powerpc/gen5200/i2c/mpc5200mbus.c
View File

@@ -195,7 +195,7 @@ mpc5200mbus_machine(mpc5200mbus *bus, i2c_event event)
uint8_t b;
switch (bus->state)
{
case STATE_UNINITIALIZED:
/* this should never happen. */
mpc5200mbus_machine_error(bus, event);
@@ -206,7 +206,7 @@ mpc5200mbus_machine(mpc5200mbus *bus, i2c_event event)
case EVENT_NEXTMSG: /* Start new message processing */
bus->cmsg++;
/* FALLTHRU */
case EVENT_TRANSFER: /* Initiate new transfer */
if (bus->cmsg - bus->msg >= bus->nmsg)
{
@@ -217,7 +217,7 @@ mpc5200mbus_machine(mpc5200mbus *bus, i2c_event event)
bus->done(bus->done_arg_ptr);
break;
}
/* Initiate START or REPEATED START condition on the bus */
if (event == EVENT_TRANSFER)
{
@@ -227,10 +227,10 @@ mpc5200mbus_machine(mpc5200mbus *bus, i2c_event event)
{
mpc5200mbus_rstart(bus);
}
bus->byte = 0;
mpc5200mbus_tx_mode(bus);
/* Initiate slave address sending */
if (bus->cmsg->flags & I2C_MSG_ADDR_10)
{
@@ -264,13 +264,13 @@ mpc5200mbus_machine(mpc5200mbus *bus, i2c_event event)
mpc5200mbus_send(bus, b);
}
break;
default:
mpc5200mbus_machine_error(bus, event);
break;
}
break;
case STATE_ADDR_7:
switch (event)
{
@@ -282,7 +282,7 @@ mpc5200mbus_machine(mpc5200mbus *bus, i2c_event event)
mpc5200mbus_send_ack(bus);
next_state(bus, STATE_RECEIVING);
break;
case EVENT_NACK:
mpc5200mbus_error(bus, I2C_NO_DEVICE);
next_state(bus, STATE_IDLE);
@@ -294,14 +294,14 @@ mpc5200mbus_machine(mpc5200mbus *bus, i2c_event event)
next_state(bus, STATE_IDLE);
mpc5200mbus_machine(bus, EVENT_NEXTMSG);
break;
default:
mpc5200mbus_machine_error(bus, event);
break;
}
break;
case STATE_ADDR_1_R:
case STATE_ADDR_1_R:
case STATE_ADDR_1_W:
switch (event)
{
@@ -325,25 +325,25 @@ mpc5200mbus_machine(mpc5200mbus *bus, i2c_event event)
}
break;
}
case EVENT_NACK:
mpc5200mbus_error(bus, I2C_NO_DEVICE);
next_state(bus, STATE_IDLE);
mpc5200mbus_machine(bus, EVENT_NEXTMSG);
break;
case EVENT_ARB_LOST:
mpc5200mbus_error(bus, I2C_ARBITRATION_LOST);
next_state(bus, STATE_IDLE);
mpc5200mbus_machine(bus, EVENT_NEXTMSG);
break;
default:
mpc5200mbus_machine_error(bus, event);
break;
}
break;
case STATE_SENDING:
switch (event)
{
@@ -359,7 +359,7 @@ mpc5200mbus_machine(mpc5200mbus *bus, i2c_event event)
next_state(bus, STATE_SENDING);
}
break;
case EVENT_NACK:
if (bus->byte == 0)
{
@@ -372,20 +372,20 @@ mpc5200mbus_machine(mpc5200mbus *bus, i2c_event event)
next_state(bus, STATE_IDLE);
mpc5200mbus_machine(bus, EVENT_NEXTMSG);
break;
case EVENT_ARB_LOST:
mpc5200mbus_error(bus, I2C_ARBITRATION_LOST);
next_state(bus, STATE_IDLE);
mpc5200mbus_machine(bus, EVENT_NEXTMSG);
break;
default:
mpc5200mbus_machine_error(bus, event);
break;
}
break;
case STATE_RECEIVING:
switch (event)
{
@@ -444,7 +444,7 @@ void mpc5200mbus_interrupt_handler(rtems_irq_hdl_param handle)
{
i2c_event event;
mpc5200mbus *bus = handle;
event = mpc5200mbus_get_event(bus);
/*
* clear interrupt bit
@@ -454,34 +454,34 @@ void mpc5200mbus_interrupt_handler(rtems_irq_hdl_param handle)
mpc5200mbus_machine(bus, event);
}
/*
/*
* mpc5200_mbus_irq_enable
* enable irq for mbus
*/
void mpc5200mbus_irq_enable(const rtems_irq_connect_data* ptr)
{
{
int minor = ((mpc5200mbus*)(ptr->handle))->bus_idx;
mpc5200.i2c_regs[minor].mcr |= MPC5200_I2C_MCR_MIEN;
}
/*
/*
* mpc5200_mbus_irq_disable
* enable irq for mbus
*/
void mpc5200mbus_irq_disable(const rtems_irq_connect_data* ptr)
{
{
int minor = ((mpc5200mbus*)(ptr->handle))->bus_idx;
mpc5200.i2c_regs[minor].mcr &= ~MPC5200_I2C_MCR_MIEN;
}
/*
/*
* mpc5200_mbus_isOn
* check, whether irq is enabled
* check, whether irq is enabled
*/
int mpc5200mbus_irq_isOn(const rtems_irq_connect_data* ptr)
{
{
int minor = ((mpc5200mbus*)(ptr->handle))->bus_idx;
return (0 != (mpc5200.i2c_regs[minor].mcr & MPC5200_I2C_MCR_MIEN));
@@ -527,7 +527,7 @@ mpc5200mbus_select_clock_divider(mpc5200mbus *bus, int divider)
int divider;
int mbc;
} dividers[] ={
{ 20, 0x20 }, { 22, 0x21 }, { 24, 0x22 }, { 26, 0x23 },
{ 20, 0x20 }, { 22, 0x21 }, { 24, 0x22 }, { 26, 0x23 },
{ 28, 0x00 }, { 30, 0x01 }, { 32, 0x25 }, { 34, 0x02 },
{ 36, 0x26 }, { 40, 0x03 }, { 44, 0x04 }, { 48, 0x05 },
{ 56, 0x06 }, { 64, 0x2a }, { 68, 0x07 }, { 72, 0x2B },
@@ -544,7 +544,7 @@ mpc5200mbus_select_clock_divider(mpc5200mbus *bus, int divider)
if (bus == NULL)
return RTEMS_INVALID_ADDRESS;
for (i = 0, mbc = -1; i < sizeof(dividers)/sizeof(dividers[0]); i++)
{
mbc = dividers[i].mbc;
@@ -578,13 +578,13 @@ mpc5200mbus_initialize(mpc5200mbus *i2c_bus)
if (i2c_bus->state != STATE_UNINITIALIZED) /* Check if already initialized */
return RTEMS_RESOURCE_IN_USE;
i2c_bus->state = STATE_IDLE;
i2c_bus->msg = NULL;
i2c_bus->cmsg = NULL;
i2c_bus->nmsg = 0;
i2c_bus->byte = 0;
/*
* install interrupt handler
*/
@@ -614,7 +614,7 @@ mpc5200mbus_initialize(mpc5200mbus *i2c_bus)
mpc5200.i2c_regs[i2c_bus->bus_idx].mcr |= MPC5200_I2C_MCR_MEN;
rtems_interrupt_enable(level);
return RTEMS_SUCCESSFUL;
}
@@ -639,7 +639,7 @@ mpc5200mbus_i2c_transfer(mpc5200mbus *bus, int nmsg, i2c_message *msg,
{
if (bus->state == STATE_UNINITIALIZED)
return RTEMS_NOT_CONFIGURED;
bus->done = done;
bus->done_arg_ptr = done_arg_ptr;
bus->cmsg = bus->msg = msg;
@@ -668,7 +668,7 @@ mpc5200mbus_i2c_done(mpc5200mbus *i2c_bus)
if (i2c_bus->state == STATE_UNINITIALIZED)
return RTEMS_NOT_CONFIGURED;
mpc5200.i2c_regs[i2c_bus->bus_idx].mcr = 0;
return sc;

80
c/src/lib/libbsp/powerpc/gen5200/ide/pcmcia_ide.c
View File

@@ -243,7 +243,7 @@ static void pcmcia_ide_recv_dmairq_hdl(rtems_irq_hdl_param unused)
bestcomm_glue_irq_disable(TASK_GEN_DP_BD_0);
pcmcia_ide_rxInterrupts++; /* Rx int has occurred */
if (pcmcia_ide_hdl_task != 0) {
rtems_event_send(pcmcia_ide_hdl_task,PCMCIA_IDE_INTERRUPT_EVENT);
}
@@ -258,7 +258,7 @@ static void pcmcia_ide_xmit_dmairq_hdl(rtems_irq_hdl_param unused)
bestcomm_glue_irq_disable(TASK_GEN_DP_BD_1);
pcmcia_ide_txInterrupts++; /* Tx int has occurred */
if (pcmcia_ide_hdl_task != 0) {
rtems_event_send(pcmcia_ide_hdl_task,PCMCIA_IDE_INTERRUPT_EVENT);
}
@@ -279,7 +279,7 @@ void mpc5200_pcmciaide_dma_init(int minor)
rxParam.NumBD = PCMCIA_IDE_DMA_RD_BD_CNT;
rxParam.Size.MaxBuf = PCMCIA_IDE_RD_SECTOR_SIZE;
rxParam.Initiator = INITIATOR_ALWAYS;
rxParam.StartAddrSrc =
rxParam.StartAddrSrc =
(uint32)mpc5200_ata_drive_regs[IDE_REGISTER_DATA_WORD];
rxParam.IncrSrc = 0;
rxParam.SzSrc = sizeof(uint16_t);
@@ -302,7 +302,7 @@ void mpc5200_pcmciaide_dma_init(int minor)
(uint32)mpc5200_ata_drive_regs[IDE_REGISTER_DATA_WORD];
txParam.IncrDst = 0;
txParam.SzDst = sizeof(uint16_t);
pcmcia_ide_txTaskId = TaskSetup( TASK_GEN_DP_BD_1, &txParam );
/*
* FIXME: Init BD rings
@@ -313,21 +313,21 @@ void mpc5200_pcmciaide_dma_init(int minor)
*/
/*
* connect interrupt handlers
*/
*/
bestcomm_glue_irq_install(TASK_GEN_DP_BD_1,pcmcia_ide_xmit_dmairq_hdl,NULL);
bestcomm_glue_irq_install(TASK_GEN_DP_BD_0,pcmcia_ide_recv_dmairq_hdl,NULL);
}
void mpc5200_pcmciaide_dma_blockop(bool is_write,
int minor,
uint16_t block_size,
int minor,
uint16_t block_size,
rtems_blkdev_sg_buffer *bufs,
uint32_t *cbuf,
uint32_t *cbuf,
uint32_t *pos)
{
/*
* Nameing:
* Nameing:
* - a block is one unit of data on disk (multiple sectors)
* - a buffer is a contignuous chunk of data in memory
* a block on disk may be filled with data from several buffers
@@ -360,16 +360,16 @@ void mpc5200_pcmciaide_dma_blockop(bool is_write,
*/
while ((rc == RTEMS_SUCCESSFUL) &&
(bufs_from_dma < bufs_total)) {
while ((rc == RTEMS_SUCCESSFUL) &&
(bufs_to_dma < bufs_total) &&
while ((rc == RTEMS_SUCCESSFUL) &&
(bufs_to_dma < bufs_total) &&
(bds_free > 0)) {
/*
* fill in BD, set interrupt if needed
*/
SDMA_CLEAR_IEVENT(&mpc5200.IntPend,(is_write
? TASK_GEN_DP_BD_1
: TASK_GEN_DP_BD_0));
: TASK_GEN_DP_BD_0));
if (is_write) {
TaskBDAssign(pcmcia_ide_txTaskId ,
(void *)bufs[bufs_to_dma].buffer,
@@ -394,7 +394,7 @@ void mpc5200_pcmciaide_dma_blockop(bool is_write,
bds_free --;
}
if (is_write) {
TaskStart( pcmcia_ide_txTaskId, TASK_AUTOSTART_DISABLE,
TaskStart( pcmcia_ide_txTaskId, TASK_AUTOSTART_DISABLE,
pcmcia_ide_txTaskId, TASK_INTERRUPT_DISABLE );
}
else {
@@ -407,12 +407,12 @@ void mpc5200_pcmciaide_dma_blockop(bool is_write,
* enable interrupts, wait for interrupt event
*/
rtems_task_ident(RTEMS_SELF,0,(rtems_id *)&pcmcia_ide_hdl_task);
bestcomm_glue_irq_enable((is_write
? TASK_GEN_DP_BD_1
bestcomm_glue_irq_enable((is_write
? TASK_GEN_DP_BD_1
: TASK_GEN_DP_BD_0));
rtems_event_receive(PCMCIA_IDE_INTERRUPT_EVENT,
RTEMS_WAIT | RTEMS_EVENT_ANY,
rtems_event_receive(PCMCIA_IDE_INTERRUPT_EVENT,
RTEMS_WAIT | RTEMS_EVENT_ANY,
RTEMS_NO_TIMEOUT, &events);
pcmcia_ide_hdl_task = 0;
@@ -429,13 +429,13 @@ void mpc5200_pcmciaide_dma_blockop(bool is_write,
}
do {
nxt_bd_idx = TaskBDRelease(is_write
? pcmcia_ide_txTaskId
nxt_bd_idx = TaskBDRelease(is_write
? pcmcia_ide_txTaskId
: pcmcia_ide_rxTaskId);
if ((nxt_bd_idx != TASK_ERR_BD_RING_EMPTY) &&
(nxt_bd_idx != TASK_ERR_BD_BUSY)) {
(*cbuf)++;
(*pos) += bufs[bufs_from_dma].length;
(*cbuf)++;
(*pos) += bufs[bufs_from_dma].length;
bufs_from_dma++;
}
} while ((nxt_bd_idx != TASK_ERR_BD_RING_EMPTY) &&
@@ -455,7 +455,7 @@ void mpc5200_pcmciaide_read_block(int minor, uint32_t block_size, rtems_blkdev_s
uint16_t *lbuf = (uint16_t*)((uint8_t*)(bufs[(*cbuf)].buffer)+(*pos));
uint32_t llength = bufs[(*cbuf)].length;
bool use_dma;
#if IDE_USE_STATISTICS
mpc5200_pcmciaide_read_block_call_cnt++;
#endif
@@ -477,7 +477,7 @@ void mpc5200_pcmciaide_read_block(int minor, uint32_t block_size, rtems_blkdev_s
* type of transfer mode
*/
while ((GET_UP_BYTE_OF_MPC5200_ATA_DRIVE_REG((volatile uint32_t)
(mpc5200.ata_dctr_dasr)) &
(mpc5200.ata_dctr_dasr)) &
IDE_REGISTER_STATUS_DRQ) == 0);
/*
* translate (part of) buffer list into DMA BDs
@@ -495,14 +495,14 @@ void mpc5200_pcmciaide_read_block(int minor, uint32_t block_size, rtems_blkdev_s
*lbuf++ = GET_UP_WORD_OF_MPC5200_ATA_DRIVE_REG(*(volatile uint32_t *)(ata_reg)); /* only 16 bit data port */
cnt += 2;
(*pos) += 2;
if((*pos) == llength) {
(*pos) = 0;
(*cbuf)++;
lbuf = bufs[(*cbuf)].buffer;
llength = bufs[(*cbuf)].length;
}
}
#else
@@ -512,12 +512,12 @@ void mpc5200_pcmciaide_read_block(int minor, uint32_t block_size, rtems_blkdev_s
*lbuf++ = *(volatile uint16_t *)(ata_reg); /* only 16 bit data port */
cnt += 2;
(*pos) += 2;
if((*pos) == llength) {
(*pos) = 0;
(*cbuf)++;
lbuf = bufs[(*cbuf)].buffer;
llength = bufs[(*cbuf)].length;
llength = bufs[(*cbuf)].length;
}
}
#endif
@@ -525,12 +525,12 @@ void mpc5200_pcmciaide_read_block(int minor, uint32_t block_size, rtems_blkdev_s
*lbuf++ = 0; /* fill buffer with dummy data */
cnt += 2;
(*pos) += 2;
if((*pos) == llength) {
(*pos) = 0;
(*cbuf)++;
lbuf = bufs[(*cbuf)].buffer;
llength = bufs[(*cbuf)].length;
llength = bufs[(*cbuf)].length;
}
}
}
@@ -570,7 +570,7 @@ void mpc5200_pcmciaide_write_block(int minor, uint32_t block_size,
* type of transfer mode
*/
while ((GET_UP_BYTE_OF_MPC5200_ATA_DRIVE_REG((volatile uint32_t)
(mpc5200.ata_dctr_dasr)) &
(mpc5200.ata_dctr_dasr)) &
IDE_REGISTER_STATUS_DRQ) == 0);
/*
* translate (part of) buffer list into DMA BDs
@@ -595,28 +595,28 @@ void mpc5200_pcmciaide_write_block(int minor, uint32_t block_size,
loop_max = (block_size - cnt);
}
for (loop_cnt = loop_max/2;loop_cnt > 0;loop_cnt--) {
*(volatile uint32_t *)(ata_reg) =
*(volatile uint32_t *)(ata_reg) =
SET_UP_WORD_OF_MPC5200_ATA_DRIVE_REG(*lbuf++); /* only 16 bit data port */
}
cnt += loop_max;
(*pos) += loop_max;
if((*pos) == llength) {
(*pos) = 0;
(*cbuf)++;
lbuf = bufs[(*cbuf)].buffer;
llength = bufs[(*cbuf)].length;
llength = bufs[(*cbuf)].length;
}
}
#else
while((GET_UP_BYTE_OF_MPC5200_ATA_DRIVE_REG((volatile uint32_t)(mpc5200.ata_dctr_dasr))
& IDE_REGISTER_STATUS_DRQ)
while((GET_UP_BYTE_OF_MPC5200_ATA_DRIVE_REG((volatile uint32_t)(mpc5200.ata_dctr_dasr))
& IDE_REGISTER_STATUS_DRQ)
&& (cnt < block_size)) {
*(volatile uint16_t *)(ata_reg) = *lbuf++; /* only 16 bit data port */
cnt += 2;
(*pos) += 2;
if((*pos) == llength) {
(*pos) = 0;
(*cbuf)++;
@@ -657,7 +657,7 @@ void mpc5200_pcmciaide_initialize(int minor)
#if IDE_USE_DMA
mpc5200_pcmciaide_dma_init(minor);
#endif
#endif
}

4
c/src/lib/libbsp/powerpc/gen5200/include/bsp.h
View File

@@ -25,7 +25,7 @@
#include <bspopts.h>
#include <libcpu/powerpc-utility.h>
#include <libcpu/powerpc-utility.h>
/*
* Some symbols defined in the linker command file.
@@ -109,7 +109,7 @@ LINKER_SYMBOL(MBAR);
/*
* Codename: IceCube
* Compatible Boards:
* Freescape MPC5200LITE
* Freescape MPC5200LITE
* Embedded Planet EP5200
*/

6
c/src/lib/libbsp/powerpc/gen5200/mscan/mscan-base.c
View File

@@ -162,7 +162,7 @@ bool mscan_set_bit_rate( mscan *m, unsigned can_bit_rate)
if (prescale_val > 64) {
/* Leave initialization mode */
mscan_initialization_mode_leave( m, &context);
return false;
}
@@ -454,7 +454,7 @@ uint8_t *mscan_id_acceptance_register( mscan *m, unsigned i)
&m->idar6,
&m->idar7
};
return idar [i];
}
@@ -476,7 +476,7 @@ uint8_t *mscan_id_mask_register( mscan *m, unsigned i)
&m->idmr6,
&m->idmr7
};
return idmr [i];
}

110
c/src/lib/libbsp/powerpc/gen5200/network_5200/network.c
View File

@@ -115,7 +115,7 @@ static TaskId txTaskId; /* SDMA TX task ID */
* The number of transmit buffer descriptors has to be quite large
* since a single frame often uses four or more buffer descriptors.
*/
#define RX_BUF_COUNT SDMA_BD_RX_NUM
#define RX_BUF_COUNT SDMA_BD_RX_NUM
#define TX_BUF_COUNT SDMA_BD_TX_NUM
#define TX_BD_PER_BUF 1
@@ -272,10 +272,10 @@ static void mpc5200_fec_rx_bd_init(struct mpc5200_enet_struct *sc) {
m->m_pkthdr.rcvif = ifp;
sc->rxMbuf[rxBdIndex] = m;
bdi = TaskBDAssign( rxTaskId,
bdi = TaskBDAssign( rxTaskId,
mtod(m, void *),
NULL,
ETHER_MAX_LEN,
NULL,
ETHER_MAX_LEN,
0 );
if (bdi != rxBdIndex) {
rtems_panic("network rx buffer indices out of sync");
@@ -526,7 +526,7 @@ static int mpc5200_fec_reset(struct mpc5200_enet_struct *sc) {
*/
mpc5200.rfifo_status &= FEC_FIFO_STAT_ERROR;
mpc5200.tfifo_status &= FEC_FIFO_STAT_ERROR;
/*
* reset the FIFOs
*/
@@ -535,17 +535,17 @@ static int mpc5200_fec_reset(struct mpc5200_enet_struct *sc) {
for (delay = 0;delay < 16*4;delay++) {};
mpc5200.reset_cntrl = 0x01000000;
/*
* Issue a reset command to the FEC chip
*/
mpc5200.ecntrl |= FEC_ECNTRL_RESET;
/*
* wait at least 16 clock cycles
*/
for (delay = 0;delay < 16*4;delay++) {};
return true;
}
@@ -564,7 +564,7 @@ static int mpc5200_fec_reset(struct mpc5200_enet_struct *sc) {
void mpc5200_fec_off(struct mpc5200_enet_struct *sc)
{
int counter = 0xffff;
#if defined(ETH_DEBUG)
unsigned short phyStatus, i;
@@ -619,7 +619,7 @@ void mpc5200_fec_off(struct mpc5200_enet_struct *sc)
*/
mpc5200.ecntrl &= ~(FEC_ECNTRL_OE | FEC_ECNTRL_EN);
/*
/*
* cleanup all buffers
*/
mpc5200_fec_rx_bd_cleanup(sc);
@@ -655,7 +655,7 @@ void mpc5200_fec_irq_handler(rtems_irq_hdl_param handle)
if (ievent & FEC_INTR_RFIFO_ERR) {
sc->rxOverrun++;
}
/*
/*
* fatal error ocurred?
*/
if (ievent & (FEC_INTR_XFIFO_ERR | FEC_INTR_RFIFO_ERR)) {
@@ -678,7 +678,7 @@ void mpc5200_smartcomm_rx_irq_handler(rtems_irq_hdl_param unused)
bestcomm_glue_irq_disable(FEC_RECV_TASK_NO);/*Disable receive ints*/
enet_driver[0].rxInterrupts++; /* Rx int has occurred */
rtems_event_send(enet_driver[0].rxDaemonTid, INTERRUPT_EVENT);
}
@@ -728,7 +728,7 @@ static void mpc5200_fec_retire_tbd(struct mpc5200_enet_struct *sc,
* Clear already transmitted BDs first. Will not work calling same
* from fecExceptionHandler(TFINT).
*/
while ((sc->txBdActiveCount > 0) &&
(force || (bdRing[sc->txBdTail].Status == 0x0))) {
if (sc->txMbuf[sc->txBdTail] != NULL) {
@@ -741,7 +741,7 @@ static void mpc5200_fec_retire_tbd(struct mpc5200_enet_struct *sc,
sc->txBdActiveCount--;
if(++sc->txBdTail >= sc->txBdCount) {
sc->txBdTail = 0;
}
}
}
}
@@ -762,7 +762,7 @@ static void mpc5200_fec_tx_bd_requeue(struct mpc5200_enet_struct *sc)
* Clear already transmitted BDs first. Will not work calling same
* from fecExceptionHandler(TFINT).
*/
while (sc->txBdActiveCount > 0) {
if (sc->txMbuf[sc->txBdHead] != NULL) {
/*
@@ -774,7 +774,7 @@ static void mpc5200_fec_tx_bd_requeue(struct mpc5200_enet_struct *sc)
sc->txBdActiveCount--;
if(--sc->txBdHead < 0) {
sc->txBdHead = sc->txBdCount-1;
}
}
}
}
#endif
@@ -811,12 +811,12 @@ static void mpc5200_fec_sendpacket(struct ifnet *ifp,struct mbuf *m) {
* Wait for buffer descriptor to become available.
*/
if((sc->txBdActiveCount + nAdded) == sc->txBdCount) {
/*
* Clear old events
*/
SDMA_CLEAR_IEVENT(&mpc5200.IntPend,FEC_XMIT_TASK_NO);
/*
* Wait for buffer descriptor to become available.
* Note that the buffer descriptors are checked
@@ -830,11 +830,11 @@ static void mpc5200_fec_sendpacket(struct ifnet *ifp,struct mbuf *m) {
* an interrupt.
*/
mpc5200_fec_retire_tbd(sc,false);
while((sc->txBdActiveCount + nAdded) == sc->txBdCount) {
bestcomm_glue_irq_enable(FEC_XMIT_TASK_NO);
rtems_bsdnet_event_receive(INTERRUPT_EVENT,
RTEMS_WAIT | RTEMS_EVENT_ANY,
rtems_bsdnet_event_receive(INTERRUPT_EVENT,
RTEMS_WAIT | RTEMS_EVENT_ANY,
RTEMS_NO_TIMEOUT, &events);
mpc5200_fec_retire_tbd(sc,false);
}
@@ -846,7 +846,7 @@ static void mpc5200_fec_sendpacket(struct ifnet *ifp,struct mbuf *m) {
*/
struct mbuf *n;
MFREE(m, n);
m = n;
m = n;
if(l != NULL) {
l->m_next = m;
}
@@ -866,7 +866,7 @@ static void mpc5200_fec_sendpacket(struct ifnet *ifp,struct mbuf *m) {
* FIXME: do not send interrupt after every frame
* doing this every quarter of BDs is much more efficent
*/
status = ((m->m_next == NULL)
status = ((m->m_next == NULL)
? TASK_BD_TFD | TASK_BD_INT
: 0);
/*
@@ -878,7 +878,7 @@ static void mpc5200_fec_sendpacket(struct ifnet *ifp,struct mbuf *m) {
}
else {
firstBd = thisBd;
}
}
data_ptr = mtod(m, void *);
data_len = (uint32)m->m_len;
@@ -904,7 +904,7 @@ static void mpc5200_fec_sendpacket(struct ifnet *ifp,struct mbuf *m) {
if(nAdded) {
firstBd->Status |= SDMA_BD_MASK_READY;
SDMA_TASK_ENABLE(SDMA_TCR, txTaskId);
sc->txBdActiveCount += nAdded;
sc->txBdActiveCount += nAdded;
}
break;
}
@@ -927,9 +927,9 @@ void mpc5200_fec_txDaemon(void *arg)
* Wait for packet
*/
bestcomm_glue_irq_enable(FEC_XMIT_TASK_NO);
rtems_bsdnet_event_receive(START_TRANSMIT_EVENT|INTERRUPT_EVENT,
RTEMS_EVENT_ANY | RTEMS_WAIT,
RTEMS_NO_TIMEOUT,
rtems_bsdnet_event_receive(START_TRANSMIT_EVENT|INTERRUPT_EVENT,
RTEMS_EVENT_ANY | RTEMS_WAIT,
RTEMS_NO_TIMEOUT,
&events);
/*
@@ -978,7 +978,7 @@ static void mpc5200_fec_rxDaemon(void *arg){
* Input packet handling loop
*/
rxBdIndex = 0;
for (;;) {
/*
* Clear old events
@@ -990,30 +990,30 @@ static void mpc5200_fec_rxDaemon(void *arg){
bd = bdRing + rxBdIndex;
status = bd->Status;
len = (uint16)GET_BD_LENGTH( bd );
/*
* Loop through BDs until we find an empty one. This indicates that
* the SmartDMA is still using it.
*/
while( !(status & SDMA_BD_MASK_READY) ) {
/*
* Remember the data pointer from this transfer.
*/
dptr = (void *)bd->DataPtr[0];
m = sc->rxMbuf[rxBdIndex];
m->m_len = m->m_pkthdr.len = (len
- sizeof(uint32_t)
m->m_len = m->m_pkthdr.len = (len
- sizeof(uint32_t)
- sizeof(struct ether_header));
eh = mtod(m, struct ether_header *);
m->m_data += sizeof(struct ether_header);
ether_input(ifp, eh, m);
/*
* Done w/ the BD. Clean it.
*/
sc->rxMbuf[rxBdIndex] = NULL;
/*
* Add a new buffer to the ring.
*/
@@ -1026,7 +1026,7 @@ static void mpc5200_fec_rxDaemon(void *arg){
bd->DataPtr[0] = (uint32)mtod(m, void *);
bd->Status = ( ( (uint32)SDMA_DRD_MASK_LENGTH & (uint32)size)
| ((uint32)SDMA_BD_MASK_READY));
/*
* advance to next BD
*/
@@ -1038,15 +1038,15 @@ static void mpc5200_fec_rxDaemon(void *arg){
*/
bd = bdRing + rxBdIndex;
status = bd->Status;
len = (uint16)GET_BD_LENGTH( bd );
len = (uint16)GET_BD_LENGTH( bd );
}
/*
* Unmask RXF (Full frame received) event
*/
bestcomm_glue_irq_enable(FEC_RECV_TASK_NO);
rtems_bsdnet_event_receive (INTERRUPT_EVENT | FATAL_INT_EVENT,
RTEMS_WAIT | RTEMS_EVENT_ANY,
rtems_bsdnet_event_receive (INTERRUPT_EVENT | FATAL_INT_EVENT,
RTEMS_WAIT | RTEMS_EVENT_ANY,
RTEMS_NO_TIMEOUT, &events);
if (events & FATAL_INT_EVENT) {
/*
@@ -1091,10 +1091,10 @@ static void mpc5200_fec_initialize_hardware(struct mpc5200_enet_struct *sc)
* Set FEC-Lite receive control register (R_CNTRL)
* frame length=1518, MII mode for 18-wire-transceiver
*/
mpc5200.r_cntrl = ((ETHER_MAX_LEN << FEC_RCNTRL_MAX_FL_SHIFT)
| FEC_RCNTRL_FCE
mpc5200.r_cntrl = ((ETHER_MAX_LEN << FEC_RCNTRL_MAX_FL_SHIFT)
| FEC_RCNTRL_FCE
| FEC_RCNTRL_MII_MODE);
/*
* Set FEC-Lite transmit control register (X_CNTRL)
* full-duplex, heartbeat disabled
@@ -1301,7 +1301,7 @@ static void mpc5200_sdma_task_setup(struct mpc5200_enet_struct *sc) {
rxParam.SzSrc = sizeof(uint32_t);
rxParam.StartAddrDst = (uint32)NULL;
rxParam.IncrDst = sizeof(uint32_t);
rxParam.SzDst = sizeof(uint32_t);
rxParam.SzDst = sizeof(uint32_t);
rxTaskId = TaskSetup(TASK_FEC_RX,&rxParam );
/*
@@ -1316,7 +1316,7 @@ static void mpc5200_sdma_task_setup(struct mpc5200_enet_struct *sc) {
txParam.StartAddrDst = (uint32)&(mpc5200.tfifo_data);
txParam.IncrDst = 0;
txParam.SzDst = sizeof(uint32_t);
txTaskId = TaskSetup( TASK_FEC_TX, &txParam );
}
@@ -1361,18 +1361,18 @@ static void mpc5200_fec_init(void *arg)
/*
* Allocate a set of mbuf pointers
*/
sc->rxMbuf =
sc->rxMbuf =
malloc(sc->rxBdCount * sizeof *sc->rxMbuf, M_MBUF, M_NOWAIT);
sc->txMbuf =
sc->txMbuf =
malloc(sc->txBdCount * sizeof *sc->txMbuf, M_MBUF, M_NOWAIT);
if(!sc->rxMbuf || !sc->txMbuf)
rtems_panic ("No memory for mbuf pointers");
bestcomm_glue_init();
mpc5200_sdma_task_setup(sc);
/*
* Set up interrupts
*/
@@ -1413,7 +1413,7 @@ static void mpc5200_fec_init(void *arg)
* Clear SmartDMA task interrupt pending bits.
*/
TaskIntClear( rxTaskId );
/*
* Enable the SmartDMA receive task.
*/
@@ -1452,7 +1452,7 @@ static void enet_stats (struct mpc5200_enet_struct *sc)
printf (" Bad CRC:%-8lu", sc->rxBadCRC);
printf (" Overrun:%-8lu", sc->rxOverrun);
printf (" Collision:%-8lu\n", sc->rxCollision);
printf (" Tx Interrupts:%-8lu", sc->txInterrupts);
printf (" Deferred:%-8lu", sc->txDeferred);
printf (" Late Collision:%-8lu\n", sc->txLateCollision);
@@ -1464,12 +1464,12 @@ static void enet_stats (struct mpc5200_enet_struct *sc)
/*
* restart the driver, reinit the fec
* this function is responsible to reinitialize the FEC in case a fatal
* this function is responsible to reinitialize the FEC in case a fatal
* error has ocurred. This is needed, wen a RxFIFO Overrun or a TxFIFO underrun
* has ocurred. In these cases, the FEC is automatically disabled, and
* both FIFOs must be reset and the BestComm tasks must be restarted
*
* Note: the daemon tasks will continue to run
* Note: the daemon tasks will continue to run
* (in fact this function will be called in the context of the rx daemon task)
*/
#define NEW_SDMA_SETUP
@@ -1530,7 +1530,7 @@ static void mpc5200_fec_restart(struct mpc5200_enet_struct *sc)
* Clear SmartDMA task interrupt pending bits.
*/
TaskIntClear( rxTaskId );
/*
* Enable the SmartDMA receive/transmit task.
*/
@@ -1587,7 +1587,7 @@ static int mpc5200_fec_ioctl (struct ifnet *ifp, ioctl_command_t command, caddr_
error = (command == SIOCADDMULTI)
? ether_addmulti(ifr, &sc->arpcom)
: ether_delmulti(ifr, &sc->arpcom);
if (error == ENETRESET) {
if (ifp->if_flags & IFF_RUNNING)
error = mpc5200_fec_setMultiFilter(ifp);

462
c/src/lib/libbsp/powerpc/gen5200/start/start.S
View File

@@ -104,7 +104,7 @@
.set SDRAMCS1, 0x38
.set BOOTSTR, 0x4C
.set BOOTSTP, 0x50
.set ADREN, 0x54
.set ADREN, 0x54
.set CSSR0, 0x58 /* Critical Interrupt SSR0 (603le only) */
.set CSSR1, 0x59 /* Critical Interrupt SSR1 (603le only) */
.set CFG, 0x20C
@@ -122,7 +122,7 @@
/* Register offsets of MPC5x00 GPIO registers needed */
.set GPIOPCR, 0xb00
.set GPIOWE, 0xc00
.set GPIOWE, 0xc00
.set GPIOWOD, 0xc04
.set GPIOWDD, 0xc08
.set GPIOWDO, 0xc0c
@@ -156,7 +156,7 @@
.extern boot_card
.section ".entry"
.section ".entry"
PUBLIC_VAR (start)
start:
/* 1st: initialization work (common for RAM/ROM startup) */
@@ -164,9 +164,9 @@ start:
SETBITS r30, r29, MSR_ME|MSR_RI
CLRBITS r30, r29, MSR_EE
mtmsr r30 /* Set RI/ME, Clr EE in MSR */
#if defined(HAS_UBOOT)
/* store pointer to UBoot bd_info board info structure */
/* store pointer to UBoot bd_info board info structure */
LWI r31,bsp_uboot_board_info_ptr
stw r3,0(r31)
#endif /* defined(HAS_UBOOT) */
@@ -176,8 +176,8 @@ start:
LWI r31, MBAR_RESET
LWI r29, MBAR
rlwinm r30, r29,16,16,31
stw r30, 0(r31) /* Set the MBAR */
#endif
stw r30, 0(r31) /* Set the MBAR */
#endif
LWI r31, MBAR /* set r31 to current MBAR */
/* init GPIOPCR */
@@ -188,70 +188,70 @@ start:
LWI r30, GPIOPCR_INITVAL
or r29,r29,r30
stw r29, GPIOPCR(r31)
/* further initialization work (common RAM/ROM startup) */
bl TLB_init /* Initialize TLBs */
/* further initialization work (common RAM/ROM startup) */
bl TLB_init /* Initialize TLBs */
bl FID_DCache /* Flush, inhibit and disable data cache */
bl IDUL_ICache /* Inhibit, disable and unlock instruction cache */
bl FPU_init /* Initialize FPU */
bl FPU_init /* Initialize FPU */
#if defined(NEED_LOW_LEVEL_INIT)
bl SPRG_init /* Initialize special purpose registers */
#endif
bl SPRG_init /* Initialize special purpose registers */
#endif
#if defined(NEED_LOW_LEVEL_INIT)
/* detect RAM/ROM startup (common for RAM/ROM startup) */
LWI r20, bsp_rom_start /* set the relocation offset */
LWI r30, CFG_VAL /* get CFG register content */
lwz r30, CFG(r31) /* set SDRAM single data rate / XLB_CLK=FVCO/4 / IPB_CLK=XLB_CLK/2 / PCICLK=IPB_CLK */
lwz r30, ADREN(r31) /* get content of ADREN */
TSTBITS r30, r29, ADREN_BOOT_EN
bne skip_ROM_start /* If BOOT_ROM is not enabled, skip further initialization */
/* do some board dependent configuration (unique for ROM startup) */
bl SPRG_brk_init /* Initialize special purpose onchip breakpoint registers */
/* do some board dependent configuration (unique for ROM startup) */
bl SPRG_brk_init /* Initialize special purpose onchip breakpoint registers */
LWI r30, CSCONTROL_VAL /* get CSCONTROL register content */
stw r30, CSCONTROL(r31) /* enable internal/external bus error and master for CS */
#ifdef BRS5L
LWI r30, CSBOOTROM_VAL
stw r30, CSBOOTROM(r31) /* Set CSBOOTROM */
#endif
/* FIXME: map BOOT ROM into final location with CS0 registers */
LWI r30, bsp_rom_start
rlwinm r30, r30,17,15,31
stw r30, CS0STR(r31) /* Set CS0STR */
stw r30, CS0STR(r31) /* Set CS0STR */
LWI r30, bsp_rom_end
rlwinm r30, r30,17,15,31
stw r30, CS0STP(r31) /* Set CS0STP */
lwz r30, ADREN(r31) /* get content of ADREN */
SETBITS r30, r29, ADREN_CS0_EN
SETBITS r30, r29, ADREN_CS0_EN
stw r30, ADREN(r31) /* enable CS0 mapping */
isync
/* jump to same code in final BOOT ROM location */
@@ -262,13 +262,13 @@ start:
add r30,r30,r29
mtctr r30
bctr
reloc_in_CS0:
reloc_in_CS0:
/* disable CSBOOT (or map it to CS0 range) */
lwz r30, ADREN(r31) /* get content of ADREN */
CLRBITS r30, r29, ADREN_BOOT_EN
CLRBITS r30, r29, ADREN_BOOT_EN
stw r30, ADREN(r31) /* disable BOOT mapping */
/* init SDRAM */
LWI r30, bsp_ram_start
ori r30, r30, 0x1a /* size code: bank is 128MByte */
@@ -278,96 +278,96 @@ reloc_in_CS0:
srawi r30, r30, 1
ori r30, r30, 0x1a /* size code: bank is 128MByte */
stw r30, SDRAMCS1(r31) /* Set SDRAMCS1 */
bl SDRAM_init /* Initialize SDRAM controller */
/* init arbiter and stuff... */
LWI r30, 0x8000a06e
stw r30, ARBCFG(r31) /* Set ARBCFG */
LWI r30, 0x000000ff
stw r30, ARBMPREN(r31) /* Set ARBMPREN */
LWI r30, 0x00001234
stw r30, ARBMPRIO(r31) /* Set ARBPRIO */
stw r30, ARBMPRIO(r31) /* Set ARBPRIO */
LWI r30, 0x0000001e
stw r30, ARBSNOOP(r31) /* Set ARBSNOOP */
stw r30, ARBSNOOP(r31) /* Set ARBSNOOP */
/* copy .text section from ROM to RAM location (unique for ROM startup) */
LA r30, bsp_section_text_start /* get start address of text section in RAM */
add r30, r20, r30 /* get start address of text section in ROM (add reloc offset) */
LA r29, bsp_section_text_start /* get start address of text section in RAM */
LA r28, bsp_section_text_size /* get size of RAM image */
bl copy_image /* copy text section from ROM to RAM location */
/* copy .data section from ROM to RAM location (unique for ROM startup) */
LA r30, bsp_section_data_start /* get start address of data section in RAM */
add r30, r20, r30 /* get start address of data section in ROM (add reloc offset) */
LA r29, bsp_section_data_start /* get start address of data section in RAM */
LA r28, bsp_section_data_size /* get size of RAM image */
bl copy_image /* copy initialized data section from ROM to RAM location */
LA r29, remap_rom /* get compile time address of label */
mtlr r29
blrl /* now further execution RAM */
remap_rom:
remap_rom:
/* remap BOOT ROM to CS0 (common for RAM/ROM startup) */
lwz r30, CSBOOTROM(r31) /* get content of CSBOOTROM */
CLRBITS r30, r29, CSCONF_CE
stw r30, CSBOOTROM(r31) /* disable BOOT CS */
CLRBITS r30, r29, CSCONF_CE
stw r30, CSBOOTROM(r31) /* disable BOOT CS */
lwz r30, ADREN(r31) /* get content of ADREN */
mr r29, r30 /* move content of r30 to r29 */
LWI r30, ADREN_BOOT_EN /* mask ADREN_BOOT_EN */
andc r29,r29,r30
andc r29,r29,r30
LWI r30, ADREN_CS0_EN /* unmask ADREN_CS0_EN */
or r29,r29,r30
or r29,r29,r30
stw r29,ADREN(r31) /* Simultaneous enable CS0 and disable BOOT address space */
lwz r30, CSBOOTROM(r31) /* get content of CSBOOTROM */
SETBITS r30, r29, CSCONF_CE
stw r30, CSBOOTROM(r31) /* disable BOOT CS */
SETBITS r30, r29, CSCONF_CE
stw r30, CSBOOTROM(r31) /* disable BOOT CS */
skip_ROM_start:
/* configure external DPRAM CS1 */
@@ -384,62 +384,62 @@ skip_ROM_start:
stw r30, CS1STP(r31)
lwz r30, ADREN(r31) /* get content of ADREN */
LWI r29, ADREN_CS1_EN /* unmask ADREN_CS1_EN */
or r30, r30,r29
or r30, r30,r29
stw r30, ADREN(r31) /* enable CS1 */
/* clear entire on chip SRAM (unique for ROM startup) */
lis r30, (MBAR+ONCHIP_SRAM_OFFSET)@h /* get start address of onchip SRAM */
ori r30, r30,(MBAR+ONCHIP_SRAM_OFFSET)@l
LWI r29, ONCHIP_SRAM_SIZE /* get size of onchip SRAM */
bl clr_mem /* Clear onchip SRAM */
#endif /* defined(BRS5L) */
/* clear .bss section (unique for ROM startup) */
LWI r30, bsp_section_bss_start /* get start address of bss section */
LWI r29, bsp_section_bss_size /* get size of bss section */
bl clr_mem /* Clear the bss section */
/* set stack pointer (common for RAM/ROM startup) */
LA r1, bsp_section_text_start
LA r1, bsp_section_text_start
addi r1, r1, -0x10 /* Set up stack pointer = beginning of text section - 0x10 */
bl __eabi /* Set up EABI and SYSV environment */
/* enable dynamic power management(common for RAM/ROM startup) */
bl PPC_HID0_rd /* Get the content of HID0 */
SETBITS r30, r29, HID0_DPM
SETBITS r30, r29, HID0_DPM
bl PPC_HID0_wr /* Set DPM in HID0 */
/* clear arguments and do further init. in C (common for RAM/ROM startup) */
/* Clear cmdline */
xor r3, r3, r3
bl SYM (boot_card) /* Call the first C routine */
#if defined(BRS5L)
twiddle:
twiddle:
b twiddle /* We don't expect to return from boot_card but if we do */
/* wait here for watchdog to kick us into hard reset */
SDRAM_init:
SDRAM_init:
#if defined (BRS5L)
/* set GPIO_WKUP7 pin low for 66MHz buffering */
/* or high for 133MHz registered buffering */
LWI r30, 0x80000000
lwz r29, GPIOWE(r31)
or r29,r29,r30 /* set bit 0 in r29/GPIOWE */
stw r29,GPIOWE(r31)
lwz r29, GPIOWOD(r31)
andc r29,r29,r30 /* clear bit 0 in r29/GPIOWOD */
stw r29,GPIOWOD(r31)
@@ -447,7 +447,7 @@ SDRAM_init:
lwz r29, GPIOWDO(r31)
andc r29,r29,r30 /* clear bit 0 in r29/GPIOWDO */
stw r29,GPIOWDO(r31)
lwz r29, GPIOWDD(r31)
or r29,r29,r30 /* set bit 0 in r29/GPIOWDD */
stw r29,GPIOWDD(r31)
@@ -459,66 +459,66 @@ SDRAM_init:
#endif
#if 0
LWI r30, 0xC2222600 /* Single Read2Read/Write delay=0xC, Single Write2Read/Prec. delay=0x2 */
stw r30, CFG1(r31) /* Read CAS latency=0x2, Active2Read delay=0x2, Prec.2active delay=0x2 */
LWI r30, 0xC2222600 /* Single Read2Read/Write delay=0xC, Single Write2Read/Prec. delay=0x2 */
stw r30, CFG1(r31) /* Read CAS latency=0x2, Active2Read delay=0x2, Prec.2active delay=0x2 */
/* Refr.2No-Read delay=0x06, Write latency=0x0 */
#else
/* See Erratum 342/339 in MPC5200_Errata_L25R_3_June.pdf: */
/* set 5 delays to their maximum to support two banks */
LWI r30, 0xCC222600 /* Single Read2Read/Write delay=0xC, Single Write2Read/Prec. delay=0x2 */
stw r30, CFG1(r31) /* Read CAS latency=0x2, Active2Read delay=0x2, Prec.2active delay=0x2 */
LWI r30, 0xCC222600 /* Single Read2Read/Write delay=0xC, Single Write2Read/Prec. delay=0x2 */
stw r30, CFG1(r31) /* Read CAS latency=0x2, Active2Read delay=0x2, Prec.2active delay=0x2 */
/* Refr.2No-Read delay=0x06, Write latency=0x0 */
#endif
LWI r30, 0xCCC70004 /* Burst2Read Prec.delay=0x8, Burst Write delay=0x8 */
#endif
LWI r30, 0xCCC70004 /* Burst2Read Prec.delay=0x8, Burst Write delay=0x8 */
stw r30, CFG2(r31) /* Burst Read2Write delay=0xB, Burst length=0x7, Read Tap=0x4 */
#ifdef BRS5L
LWI r30, 0xD1470000 /* Mode Set enabled, Clock enabled, Auto refresh enabled, Mem. data drv */
stw r30, CTRL(r31) /* Refresh counter=0xFFFF */
#else
LWI r30, 0xD04F0000 /* Mode Set enabled, Clock enabled, Auto refresh enabled, Mem. data drv */
stw r30, CTRL(r31) /* Refresh counter=0xFFFF */
#endif
lwz r30, CTRL(r31)
#endif
lwz r30, CTRL(r31)
SETBITS r30, r29, CTRL_PRECHARGE /* send two times precharge */
stw r30, CTRL(r31)
stw r30, CTRL(r31)
lwz r30, CTRL(r31)
SETBITS r30, r29, CTRL_REFRESH /* send two times refresh */
stw r30, CTRL(r31)
stw r30, CTRL(r31)
LWI r30, 0x008D0000 /* Op.Mode=0x0, Read CAS latency=0x2, Burst length=0x3, Write strobe puls */
stw r30, MOD(r31)
lwz r30, CTRL(r31) /* Clock enabled, Auto refresh enabled, Mem. data drv. Refresh counter=0xFFFF */
stw r30, CTRL(r31)
LWI r30, 0x008D0000 /* Op.Mode=0x0, Read CAS latency=0x2, Burst length=0x3, Write strobe puls */
stw r30, MOD(r31)
lwz r30, CTRL(r31) /* Clock enabled, Auto refresh enabled, Mem. data drv. Refresh counter=0xFFFF */
CLRBITS r30, r29, CTRL_BA1
stw r30, CTRL(r31)
blr
@@ -526,21 +526,21 @@ copy_image:
mr r27, r28
srwi r28, r28, 2
mtctr r28
slwi r28, r28, 2
sub r27, r27, r28 /* maybe some residual bytes */
copy_image_word:
lswi r28, r30, 0x04
stswi r28, r29, 0x04 /* do word copy ROM -> RAM */
addi r30, r30, 0x04 /* increment source pointer */
addi r29, r29, 0x04 /* increment destination pointer */
bdnz copy_image_word /* decrement ctr and branch if not 0 */
cmpwi r27, 0x00 /* copy image finished ? */
@@ -548,24 +548,24 @@ copy_image_word:
mtctr r27 /* reload counter for residual bytes */
copy_image_byte:
lswi r28, r30, 0x01
stswi r28, r29, 0x01 /* do byte copy ROM -> RAM */
addi r30, r30, 0x01 /* increment source pointer */
addi r29, r29, 0x01 /* increment destination pointer */
bdnz copy_image_byte /* decrement ctr and branch if not 0 */
copy_image_end:
blr
#endif /* defined(BRS5L) */
FID_DCache:
mflr r26
bl PPC_HID0_rd
TSTBITS r30, r29, HID0_DCE
mflr r26
bl PPC_HID0_rd
TSTBITS r30, r29, HID0_DCE
bne FID_DCache_exit /* If data cache is switched of, skip further actions */
li r29, PPC_D_CACHE /* 16 Kb data cache on 603e */
@@ -573,9 +573,9 @@ FID_DCache:
FID_DCache_loop_1:
lwz r27, 0(r28) /* Load data at address */
addi r28, r28, PPC_CACHE_ALIGNMENT /* increment cache line address */
subi r29, r29, PPC_CACHE_ALIGNMENT /* increment loop counter */
subi r29, r29, PPC_CACHE_ALIGNMENT /* increment loop counter */
cmpwi r29, 0x0
bne FID_DCache_loop_1 /* Loop until cache size is reached */
@@ -583,17 +583,17 @@ FID_DCache_loop_1:
LWI r28, bsp_section_text_start /* Reload base address (begin of RAM) */
xor r27, r27, r27
FID_DCache_loop_2:
dcbf r27, r28 /* Flush and invalidate cache */
addi r28, r28, PPC_CACHE_ALIGNMENT /* increment cache line address */
subi r29, r29, PPC_CACHE_ALIGNMENT /* increment loop counter */
subi r29, r29, PPC_CACHE_ALIGNMENT /* increment loop counter */
cmpwi r29, 0x0
bne FID_DCache_loop_2 /* Loop around until cache size is reached */
bl PPC_HID0_rd /* Read HID0 */
bl PPC_HID0_rd /* Read HID0 */
CLRBITS r30, r29, HID0_DCE
bl PPC_HID0_wr /* Clear DCE */
bl PPC_HID0_wr /* Clear DCE */
FID_DCache_exit:
mtlr r26
@@ -601,33 +601,33 @@ FID_DCache_exit:
IDUL_ICache:
mflr r26
bl PPC_HID0_rd
bl PPC_HID0_rd
TSTBITS r30, r29, HID0_ICE
bne IDUL_ICache_exit /* If instruction cache is switched of, skip further actions */
CLRBITS r30, r29, HID0_ICE
CLRBITS r30, r29, HID0_ICE
bl PPC_HID0_wr /* Disable ICE bit */
SETBITS r30, r29, HID0_ICFI
SETBITS r30, r29, HID0_ICFI
bl PPC_HID0_wr /* Invalidate instruction cache */
CLRBITS r30, r29, HID0_ICFI
CLRBITS r30, r29, HID0_ICFI
bl PPC_HID0_wr /* Disable cache invalidate */
CLRBITS r30, r29, HID0_ILOCK
bl PPC_HID0_wr /* Disable instruction cache lock */
CLRBITS r30, r29, HID0_ILOCK
bl PPC_HID0_wr /* Disable instruction cache lock */
IDUL_ICache_exit:
mtlr r26
blr
TLB_init: /* Initialize translation lookaside buffers (TLBs) */
xor r30, r30, r30
xor r29, r29, r29
TLB_init_loop:
xor r29, r29, r29
TLB_init_loop:
tlbie r29
tlbsync
addi r29, r29, 0x1000
@@ -638,16 +638,16 @@ TLB_init_loop:
FPU_init:
mfmsr r30 /* get content of MSR */
SETBITS r30, r29, MSR_FP
mtmsr r30 /* enable FPU and FPU exceptions */
#if 0
#if 0
LA r29, bsp_ram_start
stw r29, 0x0(r29)
#endif
#endif
lfd f0, 0(r29)
fmr f1, f0
fmr f2, f0
@@ -680,8 +680,8 @@ FPU_init:
fmr f29, f0
fmr f30, f0
fmr f31, f0
mtfsfi 0, 0 /* initialize bit positons in FPSCR */
mtfsfi 1, 0
mtfsfi 2, 0
@@ -690,12 +690,12 @@ FPU_init:
mtfsfi 5, 0
mtfsfi 6, 0
mtfsfi 7, 0
blr
SPRG_init: /* initialize registers */
xor r30, r30, r30
mtspr XER, r30
mtspr CTR, r30
mtspr DSISR, r30
@@ -709,7 +709,7 @@ SPRG_init: /* initialize registers */
mtspr SPRG0, r30
mtspr SPRG1, r30
mtspr SPRG2, r30
mtspr SPRG3, r30
mtspr SPRG3, r30
mtspr SPRG4, r30
mtspr SPRG5, r30
mtspr SPRG6, r30
@@ -771,74 +771,74 @@ SPRG_init: /* initialize registers */
mtsr SR13, r30
mtsr SR14, r30
mtsr SR15, r30
blr
SPRG_brk_init:
xor r30, r30, r30
mtspr DABR2, r30
mtspr DBCR, r30
mtspr IBCR, r30
mtspr IABR, r30
mtspr HID2, r30
mtspr DABR, r30
mtspr IABR2, r30
mtspr IABR2, r30
blr
PPC_HID0_rd: /* get HID0 content to r30 */
mfspr r30, HID0
blr
PPC_HID0_wr: /* put r30 content to HID0 */
mtspr HID0, r30
blr
clr_mem:
mr r28, r29
mr r28, r29
srwi r29, r29, 2
mtctr r29 /* set ctr reg */
slwi r29, r29, 2
sub r28, r28, r29 /* maybe some residual bytes */
xor r29, r29, r29
xor r29, r29, r29
clr_mem_word:
stswi r29, r30, 0x04 /* store r29 (word) to r30 memory location */
addi r30, r30, 0x04 /* increment r30 */
bdnz clr_mem_word /* dec counter and loop */
cmpwi r28, 0x00 /* clear mem. finished ? */
beq clr_mem_end;
mtctr r28 /* reload counter for residual bytes */
clr_mem_byte:
stswi r29, r30, 0x01 /* store r29 (byte) to r30 memory location */
addi r30, r30, 0x01 /* update r30 */
bdnz clr_mem_byte /* dec counter and loop */
clr_mem_end:
blr /* return */

2
c/src/lib/libbsp/powerpc/gen5200/startup/bspreset.c
View File

@@ -21,7 +21,7 @@ void bsp_reset( void )
BSP_IRQ_Benchmarking_Report();
}
#endif
/*
* Now reset the CPU
*/

2
c/src/lib/libbsp/powerpc/gen5200/startup/bspstart.c
View File

@@ -144,7 +144,7 @@ void bsp_start(void)
#if defined(HAS_UBOOT)
bsp_uboot_board_info = *bsp_uboot_board_info_ptr;
#endif
#endif
#if defined(HAS_UBOOT) && defined(SHOW_MORE_INIT_SETTINGS)
{

22
c/src/lib/libbsp/powerpc/gen5200/startup/cpuinit.c
View File

@@ -98,18 +98,18 @@ static void calc_dbat_regvals(
while ((end_addr & block_mask) != (base_addr & block_mask)) {
block_mask <<= 1;
}
bat_ptr->batu.bepi = base_addr >> (32 - 15);
bat_ptr->batu.bepi = base_addr >> (32 - 15);
bat_ptr->batu.bl = ~(block_mask >> (28 - 11));
bat_ptr->batu.vs = 1;
bat_ptr->batu.vp = 1;
bat_ptr->batl.brpn = base_addr >> (32 - 15);
bat_ptr->batl.w = flg_w;
bat_ptr->batl.i = flg_i;
bat_ptr->batl.m = flg_m;
bat_ptr->batl.g = flg_g;
bat_ptr->batl.pp = flg_bpp;
bat_ptr->batl.brpn = base_addr >> (32 - 15);
bat_ptr->batl.w = flg_w;
bat_ptr->batl.i = flg_i;
bat_ptr->batl.m = flg_m;
bat_ptr->batl.g = flg_g;
bat_ptr->batl.pp = flg_bpp;
}
#if defined (BRS5L)
@@ -170,7 +170,7 @@ void cpu_init_bsp(void)
{
BAT dbat;
uint32_t start = 0;
/*
* Program BAT0 for RAM
*/
@@ -272,7 +272,7 @@ void cpu_init(void)
/* Update MSR */
ppc_set_machine_state_register( msr);
/*
/*
* Enable data cache.
*
* NOTE: TRACE32 now supports data cache for MGT5x00.

10
c/src/lib/libbsp/powerpc/gen5200/tod/pcf8563.c
View File

@@ -30,7 +30,7 @@
* RTC I2C device address.
*
* Based on a ds1307 driver from:
*
*
* Copyright (C) 2000 OKTET Ltd., St.-Petersburg, Russia
* Author: Victor V. Vengerov <vvv@oktet.ru>
*
@@ -74,7 +74,7 @@ pcf8563_initialize(int minor)
/* Read SECONDS register */
try = 0;
do {
status = i2c_wbrd(bus, addr, PCF8563_CONTROL1_ADR,
status = i2c_wbrd(bus, addr, PCF8563_CONTROL1_ADR,
&ctrl1, sizeof(ctrl1));
try++;
} while ((status != I2C_SUCCESSFUL) && (try < 15));
@@ -134,7 +134,7 @@ pcf8563_get_time(int minor, rtems_time_of_day *time)
v1 = info[PCF8563_YEAR_ADR-PCF8563_SECOND_ADR];
v2 = From_BCD(v1);
if ((info[PCF8563_MONTH_ADR-PCF8563_SECOND_ADR]
if ((info[PCF8563_MONTH_ADR-PCF8563_SECOND_ADR]
& PCF8563_MONTH_CENTURY) == 0) {
time->year = 1900 + v2;
}
@@ -198,10 +198,10 @@ pcf8563_set_time(int minor, const rtems_time_of_day *time)
info[1 + PCF8563_MINUTE_ADR-PCF8563_SECOND_ADR] = To_BCD(time->minute);
info[1 + PCF8563_SECOND_ADR-PCF8563_SECOND_ADR] = To_BCD(time->second);
/* Do not set day of week */
info[1 + PCF8563_DAY_OF_WEEK_ADR-PCF8563_SECOND_ADR] = 1;
info[1 + PCF8563_DAY_OF_WEEK_ADR-PCF8563_SECOND_ADR] = 1;
/*
* add century info
* add century info
*/
if (time->year >= 2000) {
info[1 + PCF8563_MONTH_ADR -PCF8563_SECOND_ADR] |= PCF8563_MONTH_CENTURY;