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Whitespace removal.

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This commit is contained in:
Ralf Corsepius
2009-11-29 14:59:41 +00:00
parent 32b8506b24
commit d4b4664b99
51 changed files with 758 additions and 758 deletions
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22
c/src/lib/libbsp/m68k/av5282/console/console.c
View File

@@ -27,7 +27,7 @@ static int IntUartInterruptWrite (int minor, const char *buf, int len);
static void
_BSP_null_char( char c )
{
{
int level;
if (c == '\n')
@@ -155,7 +155,7 @@ IntUartSet(int minor, int baud, int databits, int parity, int stopbits, int hwfl
Description : This provides the hardware-dependent portion of tcsetattr().
value and sets it. At the moment this just sets the baud rate.
Note: The highest baudrate is 115200 as this stays within
Note: The highest baudrate is 115200 as this stays within
an error of +/- 5% at 25MHz processor clock
***************************************************************************/
static int
@@ -337,7 +337,7 @@ IntUartInitialize(void)
info->stopbits = -1;
info->hwflow = -1;
info->iomode = TERMIOS_POLLED;
MCF5282_UART_UACR(chan) = 0;
MCF5282_UART_UIMR(chan) = 0;
if ( info->iomode != TERMIOS_POLLED )
@@ -385,9 +385,9 @@ IntUartInitialize(void)
/***************************************************************************
Function : IntUartInterruptWrite
Description : This writes a single character to the appropriate uart
Description : This writes a single character to the appropriate uart
channel. This is either called during an interrupt or in the user's task
to initiate a transmit sequence. Calling this routine enables Tx
to initiate a transmit sequence. Calling this routine enables Tx
interrupts.
***************************************************************************/
static int
@@ -494,7 +494,7 @@ IntUartTaskRead(int minor)
/* copy data into local buffer from rx buffer */
while ( ( index < count ) && ( index < RX_BUFFER_SIZE ) )
{
/* copy data byte */
/* copy data byte */
buffer[index] = info->rx_buffer[info->rx_out];
index++;
@@ -521,7 +521,7 @@ IntUartTaskRead(int minor)
/***************************************************************************
Function : IntUartPollRead
Description : This reads a character from the internal uart. It returns
Description : This reads a character from the internal uart. It returns
to the caller without blocking if not character is waiting.
***************************************************************************/
static int
@@ -537,8 +537,8 @@ IntUartPollRead (int minor)
/***************************************************************************
Function : IntUartPollWrite
Description : This writes out each character in the buffer to the
appropriate internal uart channel waiting till each one is sucessfully
Description : This writes out each character in the buffer to the
appropriate internal uart channel waiting till each one is sucessfully
transmitted.
***************************************************************************/
static int
@@ -575,7 +575,7 @@ rtems_device_driver console_initialize(
/* set io modes for the different channels and initialize device */
IntUartInfo[minor].iomode = TERMIOS_IRQ_DRIVEN;
IntUartInitialize();
IntUartInitialize();
/* Register the console port */
status = rtems_io_register_name ("/dev/console", major, CONSOLE_PORT);
@@ -608,7 +608,7 @@ rtems_device_driver console_initialize(
/***************************************************************************
Function : console_open
Description : This actually opens the device depending on the minor
Description : This actually opens the device depending on the minor
number set during initialisation. The device specific access routines are
passed to termios when the devices is opened depending on whether it is
polled or not.

2
c/src/lib/libbsp/m68k/av5282/include/bsp.h
View File

@@ -1,7 +1,7 @@
/*
* av5282 BSP header file
*/
#ifndef __SBav5282_BSP_H
#define __SBav5282_BSP_H

28
c/src/lib/libbsp/m68k/av5282/network/network.c
View File

@@ -115,7 +115,7 @@ static rtems_isr
mcf5282_fec_rx_interrupt_handler( rtems_vector_number v )
{
MCF5282_FEC_EIR = MCF5282_FEC_EIR_RXF;
MCF5282_FEC_EIMR &= ~MCF5282_FEC_EIMR_RXF;
MCF5282_FEC_EIMR &= ~MCF5282_FEC_EIMR_RXF;
enet_driver[0].rxInterrupts++;
rtems_event_send(enet_driver[0].rxDaemonTid, RX_INTERRUPT_EVENT);
}
@@ -124,7 +124,7 @@ static rtems_isr
mcf5282_fec_tx_interrupt_handler( rtems_vector_number v )
{
MCF5282_FEC_EIR = MCF5282_FEC_EIR_TXF;
MCF5282_FEC_EIMR &= ~MCF5282_FEC_EIMR_TXF;
MCF5282_FEC_EIMR &= ~MCF5282_FEC_EIMR_TXF;
enet_driver[0].txInterrupts++;
rtems_event_send(enet_driver[0].txDaemonTid, TX_INTERRUPT_EVENT);
}
@@ -264,7 +264,7 @@ mcf5282_fec_initialize_hardware(struct mcf5282_enet_struct *sc)
* Full duplex
* No loopback
*/
MCF5282_FEC_RCR = MCF5282_FEC_RCR_MAX_FL(MAX_MTU_SIZE) |
MCF5282_FEC_RCR = MCF5282_FEC_RCR_MAX_FL(MAX_MTU_SIZE) |
MCF5282_FEC_RCR_MII_MODE;
/*
@@ -334,7 +334,7 @@ mcf5282_fec_initialize_hardware(struct mcf5282_enet_struct *sc)
MCF5282_INTC0_ICR27 = MCF5282_INTC_ICR_IL(FEC_IRQ_LEVEL) |
MCF5282_INTC_ICR_IP(FEC_IRQ_RX_PRIORITY);
MCF5282_INTC0_IMRL &= ~(MCF5282_INTC_IMRL_INT27 | MCF5282_INTC_IMRL_MASKALL);
status = rtems_interrupt_catch(mcf5282_mii_interrupt_handler, MII_VECTOR, &old_handler);
if (status != RTEMS_SUCCESSFUL)
rtems_panic ("Can't attach MCF5282 FEC MII interrupt handler: %s\n",
@@ -504,9 +504,9 @@ fec_sendpacket(struct ifnet *ifp, struct mbuf *m)
*/
nAdded = 0;
firstTxBd = sc->txBdBase + sc->txBdHead;
while(m != NULL) {
/*
/*
* Wait for buffer descriptor to become available
*/
if ((sc->txBdActiveCount + nAdded) == sc->txBdCount) {
@@ -514,7 +514,7 @@ fec_sendpacket(struct ifnet *ifp, struct mbuf *m)
* Clear old events.
*/
MCF5282_FEC_EIR = MCF5282_FEC_EIR_TXF;
/*
* Wait for buffer descriptor to become available.
* Check for buffer descriptors before waiting for the event.
@@ -525,9 +525,9 @@ fec_sendpacket(struct ifnet *ifp, struct mbuf *m)
while ((sc->txBdActiveCount + nAdded) == sc->txBdCount) {
rtems_event_set events;
int level;
rtems_interrupt_disable(level);
MCF5282_FEC_EIMR |= MCF5282_FEC_EIMR_TXF;
MCF5282_FEC_EIMR |= MCF5282_FEC_EIMR_TXF;
rtems_interrupt_enable(level);
sc->txRawWait++;
rtems_bsdnet_event_receive(TX_INTERRUPT_EVENT,
@@ -537,13 +537,13 @@ fec_sendpacket(struct ifnet *ifp, struct mbuf *m)
fec_retire_tx_bd(sc);
}
}
/*
* Don't set the READY flag on the first fragment
* until the whole packet has been readied.
*/
status = nAdded ? MCF5282_FEC_TxBD_R : 0;
/*
* The IP fragmentation routine in ip_output
* can produce fragments with zero length.
@@ -622,9 +622,9 @@ fec_txDaemon(void *arg)
/*
* Wait for packet
*/
rtems_bsdnet_event_receive(START_TRANSMIT_EVENT,
RTEMS_EVENT_ANY | RTEMS_WAIT,
RTEMS_NO_TIMEOUT,
rtems_bsdnet_event_receive(START_TRANSMIT_EVENT,
RTEMS_EVENT_ANY | RTEMS_WAIT,
RTEMS_NO_TIMEOUT,
&events);
/*

20
c/src/lib/libbsp/m68k/av5282/start/start.S
View File

@@ -24,10 +24,10 @@
BEGIN_CODE
#define INITIAL_STACK __SRAMBASE+SRAM_SIZE-4
PUBLIC (INTERRUPT_VECTOR)
SYM(INTERRUPT_VECTOR):
.long INITIAL_STACK | 0: Initial 'SSP'
.long INITIAL_STACK | 0: Initial 'SSP'
.long start | 1: Initial PC
.long SYM(_uhoh) | 2: Bus error
.long SYM(_uhoh) | 3: Address error
@@ -290,9 +290,9 @@ SYM(INTERRUPT_VECTOR):
*/
.align 4
PUBLIC (_uhoh)
SYM(_uhoh):
SYM(_uhoh):
nop | Leave spot for breakpoint
stop #0x2700 | Stop with interrupts disabled
stop #0x2700 | Stop with interrupts disabled
bra.w SYM(_uhoh) | Stuck forever
.align 4
@@ -325,7 +325,7 @@ SYM(start):
*/
move.l #__IPSBAR+1,d0 | Enable the MCF5282 internal peripherals
move.l d0,DEFAULT_IPSBAR
/*
* Remainder of the startup code is handled by C code
*/
@@ -334,7 +334,7 @@ SYM(start):
/***************************************************************************
Function : CopyDataClearBSSAndStart
Description : Copy DATA segment, Copy SRAM segment, clear BSS segment,
Description : Copy DATA segment, Copy SRAM segment, clear BSS segment,
start C program. Assume that DATA and BSS sizes are multiples of 4.
***************************************************************************/
.align 4
@@ -342,7 +342,7 @@ SYM(start):
PUBLIC (CopyDataClearBSSAndStart)
SYM(CopyDataClearBSSAndStart):
lea SYM(_data_dest_start),a0 | Get start of DATA in RAM
lea SYM(_data_src_start),a2 | Get start of DATA in ROM
lea SYM(_data_src_start),a2 | Get start of DATA in ROM
cmpl a0,a2 | Are they the same?
beq.s NODATACOPY | Yes, no copy necessary
lea SYM(_data_dest_end),a1 | Get end of DATA in RAM
@@ -353,7 +353,7 @@ DATACOPYLOOPTEST:
cmpl a1,a0 | Done?
bcs.s DATACOPYLOOP | No, skip
NODATACOPY:
/* Now, clear BSS */
lea _clear_start,a0 | Get start of BSS
lea _clear_end,a1 | Get end of BSS
@@ -377,8 +377,8 @@ MULTI_TASK_EXIT:
nop
nop
trap #14
bra MULTI_TASK_EXIT
bra MULTI_TASK_EXIT
END_CODE
.align 2

4
c/src/lib/libbsp/m68k/av5282/startup/bspstart.c
View File

@@ -17,13 +17,13 @@
* found in the file LICENSE in this distribution or at
*
* http://www.rtems.com/license/LICENSE.
*
*
* $Id$
*/
#include <bsp.h>
#include <string.h>
/*
* Cacheable areas
*/

12
c/src/lib/libbsp/m68k/av5282/startup/init5282.c
View File

@@ -2,7 +2,7 @@
* This is where the real hardware setup is done. A minimal stack
* has been provided by the start.S code. No normal C or RTEMS
* functions can be called from here.
*
*
* This routine is pretty simple for the uC5282 because all the hard
* work has been done by the bootstrap dBUG code.
*/
@@ -24,7 +24,7 @@ void Init5282 (void)
{
int x;
int temp = 0;
/*Setup the GPIO Registers */
MCF5282_GPIO_PBCDPAR = 0x80;
MCF5282_GPIO_PEPAR = 0x5100;
@@ -35,7 +35,7 @@ void Init5282 (void)
MCF5282_QADC_DDRQB = 0x07;
MCF5282_GPTA_GPTDDR = 0x0C;
MCF5282_GPTA_GPTPORT = 0x4;
/*Setup the Chip Selects so CS0 is flash */
MCF5282_CS0_CSAR =(0xff800000 & 0xffff0000)>>16;
MCF5282_CS0_CSMR = 0x007f0001;
@@ -54,11 +54,11 @@ void Init5282 (void)
temp +=1;
}
/* set ip ( bit 3 ) in dacr */
MCF5282_SDRAMC_DACR0 |= (0x00000008) ;
MCF5282_SDRAMC_DACR0 |= (0x00000008) ;
/* init precharge */
*((short *)MM_SDRAM_BASE) = 0;
/* set RE in dacr */
MCF5282_SDRAMC_DACR0 |= (0x00008000);
MCF5282_SDRAMC_DACR0 |= (0x00008000);
/* wait */
for(x=0; x<20000; x++)
{
@@ -72,7 +72,7 @@ void Init5282 (void)
temp +=1;
}
*((unsigned long*)MM_SDRAM_BASE)=0x12345678;
/* Copy the interrupt vector table to address 0x0 in SDRAM */
{
uint32_t *inttab = (uint32_t *)&INTERRUPT_VECTOR;

4
c/src/lib/libbsp/m68k/csb360/console/console-io.c
View File

@@ -54,13 +54,13 @@ void console_outbyte_polled(
while ((uart->ucsr & MCF5272_USR_TXRDY) == 0) {
continue;
}
uart->udata = ch;
for (i = 0; i < 1000; i++) g_cnt++;
}
/*
* console_inbyte_nonblocking
* console_inbyte_nonblocking
*
* This routine polls for a character.
*/

180
c/src/lib/libbsp/m68k/csb360/network/network.c
View File

@@ -7,7 +7,7 @@
* Right now, we only do 10 Mbps, even with the FEC. The function
* rtems_enet_driver_attach determines which one to use. Currently,
* only one may be used at a time.
*
*
* Based on the MC68360 network driver by
* W. Eric Norum
* Saskatchewan Accelerator Laboratory
@@ -133,7 +133,7 @@ struct mcf5272_enet_struct {
bd_t *txBdBase;
rtems_id rxDaemonTid;
rtems_id txDaemonTid;
/*
* Statistics
*/
@@ -146,7 +146,7 @@ struct mcf5272_enet_struct {
unsigned long rxBadCRC;
unsigned long rxOverrun;
unsigned long rxTruncated;
unsigned long txInterrupts;
unsigned long txDeferred;
unsigned long txHeartbeat;
@@ -162,30 +162,30 @@ static struct mcf5272_enet_struct enet_driver[NIFACES];
void dump_enet_regs(void)
{
printf("**************************************************************\n");
printf("ecr: 0x%08x eir: 0x%08x eimr: 0x%08x ivsr: 0x%08x\n\r",
g_enet_regs->ecr, g_enet_regs->eir,
g_enet_regs->eimr, g_enet_regs->ivsr);
printf("rdar: 0x%08x tdar: 0x%08x mmfr: 0x%08x mscr: 0x%08x\n\r",
g_enet_regs->rdar, g_enet_regs->tdar,
g_enet_regs->mmfr, g_enet_regs->mscr);
printf("frbr: 0x%08x frsr: 0x%08x tfwr: 0x%08x tfsr: 0x%08x\n\r",
g_enet_regs->frbr, g_enet_regs->frsr,
g_enet_regs->tfwr, g_enet_regs->tfsr);
printf("rcr: 0x%08x mflr: 0x%08x tcr: 0x%08x malr: 0x%08x\n\r",
printf("ecr: 0x%08x eir: 0x%08x eimr: 0x%08x ivsr: 0x%08x\n\r",
g_enet_regs->ecr, g_enet_regs->eir,
g_enet_regs->eimr, g_enet_regs->ivsr);
printf("rdar: 0x%08x tdar: 0x%08x mmfr: 0x%08x mscr: 0x%08x\n\r",
g_enet_regs->rdar, g_enet_regs->tdar,
g_enet_regs->mmfr, g_enet_regs->mscr);
printf("frbr: 0x%08x frsr: 0x%08x tfwr: 0x%08x tfsr: 0x%08x\n\r",
g_enet_regs->frbr, g_enet_regs->frsr,
g_enet_regs->tfwr, g_enet_regs->tfsr);
printf("rcr: 0x%08x mflr: 0x%08x tcr: 0x%08x malr: 0x%08x\n\r",
g_enet_regs->rcr, g_enet_regs->mflr,
g_enet_regs->tcr, g_enet_regs->malr);
printf("maur: 0x%08x htur: 0x%08x htlr: 0x%08x erdsr: 0x%08x\n\r",
g_enet_regs->maur, g_enet_regs->htur,
g_enet_regs->htlr, g_enet_regs->erdsr);
printf("etdsr: 0x%08x emrbr: 0x%08x\n\r",
g_enet_regs->etdsr, g_enet_regs->emrbr);
g_enet_regs->tcr, g_enet_regs->malr);
printf("maur: 0x%08x htur: 0x%08x htlr: 0x%08x erdsr: 0x%08x\n\r",
g_enet_regs->maur, g_enet_regs->htur,
g_enet_regs->htlr, g_enet_regs->erdsr);
printf("etdsr: 0x%08x emrbr: 0x%08x\n\r",
g_enet_regs->etdsr, g_enet_regs->emrbr);
}
/*#define cp printk("%s:%d\n\r", __FUNCTION__, __LINE__) */
#define cp
#define cp
#define mcf5272_bd_allocate(_n_) malloc((_n_) * sizeof(bd_t), 0, M_NOWAIT)
@@ -236,7 +236,7 @@ mcf5272_enet_initialize_hardware (struct mcf5272_enet_struct *sc)
* Issue reset to FEC
*/
g_enet_regs->ecr=0x1;
/*
* Set the TX and RX fifo sizes. For now, we'll split it evenly
*/
@@ -244,11 +244,11 @@ mcf5272_enet_initialize_hardware (struct mcf5272_enet_struct *sc)
g_enet_regs->r_fstart = ((g_enet_regs->r_bound & 0x3ff) >> 2) & 0x3ff;
g_enet_regs->x_fstart = 0;
*/
/* Copy mac address to device */
hwaddr = sc->arpcom.ac_enaddr;
g_enet_regs->malr = (hwaddr[0] << 24 |
hwaddr[1] << 16 |
hwaddr[2] << 8 |
@@ -261,23 +261,23 @@ mcf5272_enet_initialize_hardware (struct mcf5272_enet_struct *sc)
*/
g_enet_regs->htlr = 0;
g_enet_regs->htur = 0;
/*
* Set up receive buffer size
*/
g_enet_regs->emrbr = 0x5f0; /* set to 1520 */
/*
* Allocate mbuf pointers
*/
sc->rxMbuf = malloc (sc->rxBdCount * sizeof *sc->rxMbuf,
sc->rxMbuf = malloc (sc->rxBdCount * sizeof *sc->rxMbuf,
M_MBUF, M_NOWAIT);
sc->txMbuf = malloc (sc->txBdCount * sizeof *sc->txMbuf,
sc->txMbuf = malloc (sc->txBdCount * sizeof *sc->txMbuf,
M_MBUF, M_NOWAIT);
if (!sc->rxMbuf || !sc->txMbuf) {
rtems_panic ("No memory for mbuf pointers");
}
/*
* Set receiver and transmitter buffer descriptor bases
*/
@@ -285,7 +285,7 @@ mcf5272_enet_initialize_hardware (struct mcf5272_enet_struct *sc)
sc->txBdBase = mcf5272_bd_allocate(sc->txBdCount);
g_enet_regs->erdsr = (int)sc->rxBdBase;
g_enet_regs->etdsr = (int)sc->txBdBase;
/*
* Set up Receive Control Register:
* Not promiscuous mode
@@ -294,27 +294,27 @@ mcf5272_enet_initialize_hardware (struct mcf5272_enet_struct *sc)
* No loopback
*/
g_enet_regs->rcr = 0x00000004;
/*
* Set up Transmit Control Register:
* Full duplex
* No heartbeat
*/
g_enet_regs->tcr = 0x00000004;
/*
* Set MII speed to 2.5 MHz for 25 Mhz system clock
* Set MII speed to 2.5 MHz for 25 Mhz system clock
*/
g_enet_regs->mscr = 0x0a;
g_enet_regs->mmfr = 0x58021000;
/*
* Set up receive buffer descriptors
*/
for (i = 0 ; i < sc->rxBdCount ; i++) {
(sc->rxBdBase + i)->status = 0;
}
/*
* Set up transmit buffer descriptors
*/
@@ -325,11 +325,11 @@ mcf5272_enet_initialize_hardware (struct mcf5272_enet_struct *sc)
sc->txBdHead = sc->txBdTail = 0;
sc->txBdActiveCount = 0;
/*
* Mask all FEC interrupts and clear events
*/
g_enet_regs->eimr = (MCF5272_ENET_EIR_TXF |
g_enet_regs->eimr = (MCF5272_ENET_EIR_TXF |
MCF5272_ENET_EIR_RXF);
g_enet_regs->eir = ~0;
@@ -341,12 +341,12 @@ mcf5272_enet_initialize_hardware (struct mcf5272_enet_struct *sc)
/* Configure ethernet interrupts */
icr = g_intctrl_regs->icr3;
icr = icr & ~((MCF5272_ICR3_ERX_MASK | MCF5272_ICR3_ERX_PI) |
icr = icr & ~((MCF5272_ICR3_ERX_MASK | MCF5272_ICR3_ERX_PI) |
(MCF5272_ICR3_ETX_MASK | MCF5272_ICR3_ETX_PI));
icr |= ((MCF5272_ICR3_ERX_IPL(BSP_INTLVL_ERX) | MCF5272_ICR3_ERX_PI)|
(MCF5272_ICR3_ETX_IPL(BSP_INTLVL_ETX) | MCF5272_ICR3_ETX_PI));
g_intctrl_regs->icr3 = icr;
}
@@ -366,7 +366,7 @@ mcf5272_enet_retire_tx_bd (struct mcf5272_enet_struct *sc)
int i;
int nRetired;
struct mbuf *m, *n;
i = sc->txBdTail;
nRetired = 0;
while ((sc->txBdActiveCount != 0) &&
@@ -436,7 +436,7 @@ mcf5272_enet_rxDaemon (void *arg)
uint16_t status;
bd_t *rxBd;
int rxBdIndex;
/*
* Allocate space for incoming packets and start reception
*/
@@ -454,14 +454,14 @@ mcf5272_enet_rxDaemon (void *arg)
break;
}
}
/*
* Input packet handling loop
*/
rxBdIndex = 0;
for (;;) {
rxBd = sc->rxBdBase + rxBdIndex;
/*
* Wait for packet if there's not one ready
*/
@@ -470,7 +470,7 @@ mcf5272_enet_rxDaemon (void *arg)
* Clear old events
*/
g_enet_regs->eir = MCF5272_ENET_EIR_RXF;
/*
* Wait for packet
* Note that the buffer descriptor is checked
@@ -480,12 +480,12 @@ mcf5272_enet_rxDaemon (void *arg)
*/
while ((status = rxBd->status) & MCF5272_BD_EMPTY) {
rtems_event_set events;
/*
* Unmask RXF (Full frame received) event
*/
g_enet_regs->eir |= MCF5272_ENET_EIR_RXF;
rtems_bsdnet_event_receive (INTERRUPT_EVENT,
RTEMS_WAIT|RTEMS_EVENT_ANY,
RTEMS_NO_TIMEOUT,
@@ -494,7 +494,7 @@ mcf5272_enet_rxDaemon (void *arg)
}
}
cp;
/*
* Check that packet is valid
*/
@@ -504,7 +504,7 @@ mcf5272_enet_rxDaemon (void *arg)
* FIXME: Packet filtering hook could be done here.
*/
struct ether_header *eh;
m = sc->rxMbuf[rxBdIndex];
m->m_len = m->m_pkthdr.len = (rxBd->length -
sizeof(uint32_t) -
@@ -512,7 +512,7 @@ mcf5272_enet_rxDaemon (void *arg)
eh = mtod (m, struct ether_header *);
m->m_data += sizeof(struct ether_header);
ether_input (ifp, eh, m);
/*
* Allocate a new mbuf
*/
@@ -571,12 +571,12 @@ mcf5272_enet_sendpacket (struct ifnet *ifp, struct mbuf *m)
uint16_t status;
int nAdded;
cp;
/*
* Free up buffer descriptors
*/
mcf5272_enet_retire_tx_bd (sc);
/*
* Set up the transmit buffer descriptors.
* No need to pad out short packets since the
@@ -596,7 +596,7 @@ mcf5272_enet_sendpacket (struct ifnet *ifp, struct mbuf *m)
* Clear old events
*/
g_enet_regs->eir = MCF5272_ENET_EIR_TXF;
/*
* Wait for buffer descriptor to become available.
* Note that the buffer descriptors are checked
@@ -612,7 +612,7 @@ mcf5272_enet_sendpacket (struct ifnet *ifp, struct mbuf *m)
mcf5272_enet_retire_tx_bd (sc);
while ((sc->txBdActiveCount + nAdded) == sc->txBdCount) {
rtems_event_set events;
cp;
/*
* Unmask TXB (buffer transmitted) and
@@ -627,14 +627,14 @@ mcf5272_enet_sendpacket (struct ifnet *ifp, struct mbuf *m)
mcf5272_enet_retire_tx_bd (sc);
}
}
/*
* Don't set the READY flag till the
* whole packet has been readied.
*/
status = nAdded ? MCF5272_BD_READY : 0;
cp;
/*
* FIXME: Why not deal with empty mbufs at at higher level?
* The IP fragmentation routine in ip_output
@@ -650,7 +650,7 @@ mcf5272_enet_sendpacket (struct ifnet *ifp, struct mbuf *m)
*/
txBd->buffer = mtod (m, void *);
txBd->length = m->m_len;
sc->txMbuf[sc->txBdHead] = m;
nAdded++;
if (++sc->txBdHead == sc->txBdCount) {
@@ -673,7 +673,7 @@ mcf5272_enet_sendpacket (struct ifnet *ifp, struct mbuf *m)
l->m_next = m;
*/
}
/*
* Set the transmit buffer status.
* Break out of the loop if this mbuf is the last in the frame.
@@ -709,15 +709,15 @@ mcf5272_enet_txDaemon (void *arg)
struct ifnet *ifp = &sc->arpcom.ac_if;
struct mbuf *m;
rtems_event_set events;
cp;
for (;;) {
/*
* Wait for packet
*/
rtems_bsdnet_event_receive (START_TRANSMIT_EVENT,
RTEMS_EVENT_ANY | RTEMS_WAIT,
RTEMS_NO_TIMEOUT,
rtems_bsdnet_event_receive (START_TRANSMIT_EVENT,
RTEMS_EVENT_ANY | RTEMS_WAIT,
RTEMS_NO_TIMEOUT,
&events);
cp;
/*
@@ -746,7 +746,7 @@ static void
mcf5272_enet_start (struct ifnet *ifp)
{
struct mcf5272_enet_struct *sc = ifp->if_softc;
cp;
rtems_event_send (sc->txDaemonTid, START_TRANSMIT_EVENT);
cp;
@@ -759,28 +759,28 @@ mcf5272_enet_init (void *arg)
{
struct mcf5272_enet_struct *sc = arg;
struct ifnet *ifp = &sc->arpcom.ac_if;
if (sc->txDaemonTid == 0) {
/*
* Set up SCC hardware
*/
mcf5272_enet_initialize_hardware (sc);
/*
* Start driver tasks
*/
sc->txDaemonTid = rtems_bsdnet_newproc("SCtx",
4096,
mcf5272_enet_txDaemon,
sc->txDaemonTid = rtems_bsdnet_newproc("SCtx",
4096,
mcf5272_enet_txDaemon,
sc);
sc->rxDaemonTid = rtems_bsdnet_newproc("SCrx",
4096,
mcf5272_enet_rxDaemon,
sc->rxDaemonTid = rtems_bsdnet_newproc("SCrx",
4096,
mcf5272_enet_rxDaemon,
sc);
}
/*
* Set flags appropriately
*/
@@ -789,12 +789,12 @@ mcf5272_enet_init (void *arg)
} else {
g_enet_regs->rcr &= ~0x8;
}
/*
* Tell the world that we're running.
*/
ifp->if_flags |= IFF_RUNNING;
/*
* Enable receiver and transmitter
*/
@@ -806,9 +806,9 @@ static void
mcf5272_enet_stop (struct mcf5272_enet_struct *sc)
{
struct ifnet *ifp = &sc->arpcom.ac_if;
ifp->if_flags &= ~IFF_RUNNING;
/*
* Shut down receiver and transmitter
*/
@@ -832,7 +832,7 @@ enet_stats (struct mcf5272_enet_struct *sc)
printf (" Overrun:%-8lu", sc->rxOverrun);
printf (" Truncated:%-8lu\n", sc->rxTruncated);
/* printf (" Discarded:%-8lu\n", (unsigned long)mcf5272.scc1p.un.ethernet.disfc); */
printf (" Tx Interrupts:%-8lu", sc->txInterrupts);
printf (" Deferred:%-8lu", sc->txDeferred);
printf (" Missed Hearbeat:%-8lu\n", sc->txHeartbeat);
@@ -852,37 +852,37 @@ mcf5272_enet_ioctl (struct ifnet *ifp, int command, caddr_t data)
{
struct mcf5272_enet_struct *sc = ifp->if_softc;
int error = 0;
switch (command) {
case SIOCGIFADDR:
case SIOCSIFADDR:
ether_ioctl (ifp, command, data);
break;
case SIOCSIFFLAGS:
switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) {
case IFF_RUNNING:
mcf5272_enet_stop (sc);
break;
case IFF_UP:
mcf5272_enet_init (sc);
break;
case IFF_UP | IFF_RUNNING:
mcf5272_enet_stop (sc);
mcf5272_enet_init (sc);
break;
default:
break;
}
break;
case SIO_RTEMS_SHOW_STATS:
enet_stats (sc);
break;
/*
* FIXME: All sorts of multicast commands need to be added here!
*/
@@ -902,7 +902,7 @@ rtems_enet_driver_attach (struct rtems_bsdnet_ifconfig *config)
int mtu;
int unitNumber;
char *unitName;
/*
* Parse driver name
*/
@@ -910,7 +910,7 @@ rtems_enet_driver_attach (struct rtems_bsdnet_ifconfig *config)
if (unitNumber < 0){
return 0;
}
/*
* Is driver free?
*/
@@ -925,7 +925,7 @@ rtems_enet_driver_attach (struct rtems_bsdnet_ifconfig *config)
printf ("Driver already in use.\n");
return 0;
}
/*
* Process options
*/
@@ -954,7 +954,7 @@ rtems_enet_driver_attach (struct rtems_bsdnet_ifconfig *config)
sc->txBdCount = TX_BUF_COUNT * TX_BD_PER_BUF;
}
sc->acceptBroadcast = !config->ignore_broadcast;
/*
* Set up network interface values
*/
@@ -970,7 +970,7 @@ rtems_enet_driver_attach (struct rtems_bsdnet_ifconfig *config)
if (ifp->if_snd.ifq_maxlen == 0) {
ifp->if_snd.ifq_maxlen = ifqmaxlen;
}
/*
* Attach the interface
*/

8
c/src/lib/libbsp/m68k/csb360/start/start.S
View File

@@ -12,7 +12,7 @@
* Based on start.S from mcf520elite BSP:
* Copyright (C) 2000 OKTET Ltd., St.-Petersburg, Russia
* Author: Victor V. Vengerov <vvv@oktet.ru>
*
*
* Based on work:
* David Fiddes, D.J@fiddes.surfaid.org
* http://www.calm.hw.ac.uk/davidf/coldfire/
@@ -317,7 +317,7 @@ SYM(start):
move.l #(INITIAL_STACK),sp | Set up stack again (may be we are
| going here from monitor or with
| BDM interface assistance)
/*
* Remainder of the startup code is handled by C code
*/
@@ -355,7 +355,7 @@ SYM(start_csb360):
jsr SYM(boot_card) | Call C boot_card function to startup RTEMS
# Wait forever
_stop:
nop
@@ -389,7 +389,7 @@ _avec2_int:
_avec3_int:
nop
jmp _unexp_int
jmp _unexp_int
_avec4_int:
nop

12
c/src/lib/libbsp/m68k/csb360/startup/init5272.c
View File

@@ -24,7 +24,7 @@
* found in the file LICENSE in this distribution or at
*
* http://www.rtems.com/license/LICENSE.
*
*
* $Id$
*/
@@ -107,12 +107,12 @@ init5272(void)
/* Set RAM Base Address register */
m68k_set_srambar((BSP_RAMBAR & MCF5272_RAMBAR_BA) | MCF5272_RAMBAR_V);
/* Set System Control Register:
* Enet has highest priority, 16384 bus cycles before timeout
*/
g_sim_regs->scr = (MCF5272_SCR_HWR_16384);
/* System Protection Register:
* Enable Hardware watchdog timer.
*/
@@ -136,8 +136,8 @@ init5272(void)
}
}
m68k_set_vbr(BSP_RAMBAR);
/*
* Setup ACRs so that if cache turned on, periphal accesses
* are not messed up. (Non-cacheable, serialized)
@@ -158,7 +158,7 @@ init5272(void)
/* Enable the caches */
m68k_set_cacr(MCF5272_CACR_CENB |
MCF5272_CACR_DCM); /* Default is not cached */
/*
* Copy data, clear BSS, switch stacks and call boot_card()
*/

4
c/src/lib/libbsp/m68k/gen68360/include/bsp.h
View File

@@ -92,14 +92,14 @@ m68k_isr_entry set_vector(
* definitions for PGH360 board
*/
#if defined(PGH360)
/*
/*
* logical SPI addresses of SPI slaves available
*/
#define PGH360_SPI_ADDR_EEPROM 0
#define PGH360_SPI_ADDR_DISP4_DATA 1
#define PGH360_SPI_ADDR_DISP4_CTRL 2
/*
/*
* Port B bit locations of SPI slave selects
*/
#define PGH360_PB_SPI_DISP4_RS_MSK (1<<15)

88
c/src/lib/libbsp/m68k/gen68360/spi/m360_spi.c
View File

@@ -28,7 +28,7 @@
#undef DEBUG
static m360_spi_softc_t *m360_spi_softc_ptr;
/*
* this is a dummy receive buffer for sequences,
* this is a dummy receive buffer for sequences,
* where only send data are available
*/
uint8_t m360_spi_dummy_rxbuf[2];
@@ -139,7 +139,7 @@ static int m360_spi_wait
/*
* allow interrupts, when receiver is not empty
*/
m360.spim = (M360_SPIE_TXE | M360_SPIE_TXB |
m360.spim = (M360_SPIE_TXE | M360_SPIE_TXB |
M360_SPIE_BSY | M360_SPIE_MME);
rc = rtems_semaphore_obtain(softc_ptr->irq_sema_id,
@@ -165,7 +165,7 @@ static int m360_spi_wait
}
act_status = m360.spie;
if ((act_status & (M360_SPIE_TXE | M360_SPIE_TXB |
if ((act_status & (M360_SPIE_TXE | M360_SPIE_TXB |
M360_SPIE_BSY | M360_SPIE_MME))!= M360_SPIE_TXB) {
#if defined(DEBUG)
printk("... exit with RTEMS_IO_ERROR,"
@@ -199,14 +199,14 @@ static rtems_isr m360_spi_irq_handler
\*=========================================================================*/
{
m360_spi_softc_t *softc_ptr = m360_spi_softc_ptr;
/*
* disable interrupt mask
* disable interrupt mask
*/
m360.spim = 0;
if (softc_ptr->initialized) {
rtems_semaphore_release(softc_ptr->irq_sema_id);
}
}
}
/*=========================================================================*\
@@ -239,7 +239,7 @@ static void m360_spi_install_irq_handler
*/
rc = rtems_semaphore_create(rtems_build_name('s','p','i','s'),
0,
RTEMS_FIFO
RTEMS_FIFO
| RTEMS_SIMPLE_BINARY_SEMAPHORE,
0,
&softc_ptr->irq_sema_id);
@@ -286,7 +286,7 @@ static void m360_spi_install_irq_handler
}
}
}
/*=========================================================================*\
| Function: |
\*-------------------------------------------------------------------------*/
@@ -307,7 +307,7 @@ rtems_status_code m360_spi_init
{
m360_spi_softc_t *softc_ptr = &(((m360_spi_desc_t *)(bh))->softc);
rtems_status_code rc = RTEMS_SUCCESSFUL;
#if defined(DEBUG)
printk("m360_spi_init called... ");
#endif
@@ -317,7 +317,7 @@ rtems_status_code m360_spi_init
/*
* FIXME: set default mode in SPMODE
*/
/*
* allocate BDs (1x RX, 1x TX)
*/
@@ -337,7 +337,7 @@ rtems_status_code m360_spi_init
m360.spip.rfcr = M360_RFCR_MOT | M360_RFCR_DMA_SPACE;
m360.spip.tfcr = M360_RFCR_MOT | M360_RFCR_DMA_SPACE;
m360.spip.mrblr = 2;
/*
* issue "InitRxTx" Command to CP
*/
@@ -354,23 +354,23 @@ rtems_status_code m360_spi_init
* set up ports
* LINE PAR DIR DAT
* -----------------------
* MOSI 1 1 x
* MOSI 1 1 x
* MISO 1 1 x
* CLK 1 1 x
*/
/* set Port B Pin Assignment Register... */
m360.pbpar =
m360.pbpar =
m360.pbpar
| M360_PB_SPI_MISO_MSK
| M360_PB_SPI_MOSI_MSK
| M360_PB_SPI_MISO_MSK
| M360_PB_SPI_MOSI_MSK
| M360_PB_SPI_CLK_MSK;
/* set Port B Data Direction Register... */
m360.pbdir =
m360.pbdir
| M360_PB_SPI_MISO_MSK
| M360_PB_SPI_MOSI_MSK
m360.pbdir =
m360.pbdir
| M360_PB_SPI_MISO_MSK
| M360_PB_SPI_MOSI_MSK
| M360_PB_SPI_CLK_MSK;
}
/*
@@ -426,7 +426,7 @@ static int m360_spi_read_write_bytes
m360.spip.mrblr = sizeof(m360_spi_dummy_rxbuf);
softc_ptr->rx_bd->buffer = m360_spi_dummy_rxbuf;
softc_ptr->rx_bd->length = 0;
softc_ptr->rx_bd->status = (M360_BD_EMPTY | M360_BD_WRAP |
softc_ptr->rx_bd->status = (M360_BD_EMPTY | M360_BD_WRAP |
M360_BD_CONTINUOUS);
}
else {
@@ -446,7 +446,7 @@ static int m360_spi_read_write_bytes
*/
softc_ptr->tx_bd->buffer = m360_spi_dummy_rxbuf;
softc_ptr->tx_bd->length = len;
softc_ptr->tx_bd->status = (M360_BD_READY | M360_BD_WRAP |
softc_ptr->tx_bd->status = (M360_BD_READY | M360_BD_WRAP |
M360_BD_CONTINUOUS);
}
else {
@@ -566,7 +566,7 @@ rtems_status_code m360_spi_set_tfr_mode
spimode |= M360_SPMODE_CP;
}
}
if (rc == RTEMS_SUCCESSFUL) {
/*
* disable SPI
@@ -605,12 +605,12 @@ int m360_spi_ioctl
switch(cmd) {
case RTEMS_LIBI2C_IOCTL_SET_TFRMODE:
ret_val =
ret_val =
-m360_spi_set_tfr_mode(bh,
(const rtems_libi2c_tfr_mode_t *)arg);
break;
case RTEMS_LIBI2C_IOCTL_READ_WRITE:
ret_val =
ret_val =
m360_spi_read_write_bytes(bh,
((rtems_libi2c_read_write_t *)arg)->rd_buf,
((rtems_libi2c_read_write_t *)arg)->wr_buf,
@@ -655,20 +655,20 @@ static rtems_status_code bsp_spi_sel_addr
* GPIO1[24] is SPI_A0
* GPIO1[25] is SPI_A1
* GPIO1[26] is SPI_A2
* set pins to address
* set pins to address
*/
switch(addr) {
case PGH360_SPI_ADDR_EEPROM:
m360.pbdat &= ~PGH360_PB_SPI_EEP_CE_MSK;
break;
case PGH360_SPI_ADDR_DISP4_DATA:
m360.pbdat = (m360.pbdat
& ~(PGH360_PB_SPI_DISP4_CE_MSK |
m360.pbdat = (m360.pbdat
& ~(PGH360_PB_SPI_DISP4_CE_MSK |
PGH360_PB_SPI_DISP4_RS_MSK));
break;
case PGH360_SPI_ADDR_DISP4_CTRL:
m360.pbdat = (m360.pbdat
& ~(PGH360_PB_SPI_DISP4_CE_MSK)
m360.pbdat = (m360.pbdat
& ~(PGH360_PB_SPI_DISP4_CE_MSK)
| PGH360_PB_SPI_DISP4_RS_MSK);
break;
default:
@@ -721,7 +721,7 @@ static rtems_status_code bsp_spi_send_stop
printk("bsp_spi_send_stop called... ");
#endif
#if defined(PGH360)
m360.pbdat = (m360.pbdat
m360.pbdat = (m360.pbdat
| PGH360_PB_SPI_DISP4_CE_MSK
| PGH360_PB_SPI_EEP_CE_MSK);
#endif
@@ -788,7 +788,7 @@ rtems_status_code bsp_register_spi
/*
* init port pins used to address/select SPI devices
*/
#if defined(PGH360)
/*
@@ -799,24 +799,24 @@ rtems_status_code bsp_register_spi
* DISP4_CS 0 1 act-high
* DISP4_RS 0 1 active
*/
/* set Port B Pin Assignment Register... */
m360.pbpar =
(m360.pbpar
& ~(PGH360_PB_SPI_EEP_CE_MSK
m360.pbpar =
(m360.pbpar
& ~(PGH360_PB_SPI_EEP_CE_MSK
| PGH360_PB_SPI_DISP4_CE_MSK
| PGH360_PB_SPI_DISP4_RS_MSK));
/* set Port B Data Direction Register... */
m360.pbdir =
m360.pbdir
| PGH360_PB_SPI_EEP_CE_MSK
m360.pbdir =
m360.pbdir
| PGH360_PB_SPI_EEP_CE_MSK
| PGH360_PB_SPI_DISP4_CE_MSK
| PGH360_PB_SPI_DISP4_RS_MSK;
/* set Port B Data Register to inactive CE state */
m360.pbdat =
m360.pbdat
m360.pbdat =
m360.pbdat
| PGH360_PB_SPI_DISP4_CE_MSK
| PGH360_PB_SPI_DISP4_RS_MSK;
#endif

2
c/src/lib/libbsp/m68k/gen68360/spi/m360_spi.h
View File

@@ -36,7 +36,7 @@ typedef struct m360_spi_softc {
} m360_spi_softc_t ;
typedef struct {
rtems_libi2c_bus_t bus_desc;
rtems_libi2c_bus_t bus_desc;
m360_spi_softc_t softc;
} m360_spi_desc_t;

4
c/src/lib/libbsp/m68k/gen68360/startup/init68360.c
View File

@@ -465,7 +465,7 @@ void _Init68360 (void)
ram_end = &ramtest_end;
code_loc = (void *)ramtest_exec;
if ((ram_base < ram_end) &&
!((ram_base <= code_loc) && (code_loc < ram_end))) {
!((ram_base <= code_loc) && (code_loc < ram_end))) {
ramtest_exec(ram_base,ram_end);
}
}
@@ -477,7 +477,7 @@ void _Init68360 (void)
for (i = 0; i < 256; ++i)
M68Kvec[i] = vbr[i];
m68k_set_vbr (M68Kvec);
/*
* Step 14: More system initialization
* SDCR (Serial DMA configuration register)

166
c/src/lib/libbsp/m68k/genmcf548x/network/network.c
View File

@@ -67,7 +67,7 @@
#define FEC_WATCHDOG_TIMEOUT 5 /* check media every 5 seconds */
/*
* buffer descriptor handling
* buffer descriptor handling
*/
#define SET_BD_STATUS(bd, stat) { \
@@ -115,7 +115,7 @@ extern char _SysSramBase[];
* The number of transmit buffer descriptors has to be quite large
* since a single frame often uses four or more buffer descriptors.
*/
#define RX_BUF_COUNT DMA_BD_RX_NUM
#define RX_BUF_COUNT DMA_BD_RX_NUM
#define TX_BUF_COUNT DMA_BD_TX_NUM
#define TX_BD_PER_BUF 1
@@ -217,7 +217,7 @@ struct mcf548x_enet_struct {
int txDmaChan; /* dma task */
rtems_id rxDaemonTid;
rtems_id txDaemonTid;
/*
* MDIO/Phy info
*/
@@ -274,15 +274,15 @@ static void mcf548x_fec_rx_bd_init(struct mcf548x_enet_struct *sc) {
m->m_pkthdr.rcvif = ifp;
sc->rxMbuf[rxBdIndex] = m;
rtems_cache_invalidate_multiple_data_lines(mtod(m,const void *),
rtems_cache_invalidate_multiple_data_lines(mtod(m,const void *),
ETHER_MAX_LEN);
SET_BD_BUFFER(sc->rxBd+rxBdIndex,mtod(m, void *));
SET_BD_LENGTH(sc->rxBd+rxBdIndex,ETHER_MAX_LEN);
SET_BD_LENGTH(sc->rxBd+rxBdIndex,ETHER_MAX_LEN);
SET_BD_STATUS(sc->rxBd+rxBdIndex,
MCF548X_FEC_RBD_EMPTY
MCF548X_FEC_RBD_EMPTY
| MCF548X_FEC_RBD_INT
| ((rxBdIndex == sc->rxBdCount-1)
? MCF548X_FEC_RBD_WRAP
| ((rxBdIndex == sc->rxBdCount-1)
? MCF548X_FEC_RBD_WRAP
: 0));
}
}
@@ -401,11 +401,11 @@ static void mcf548x_eth_addr_filter_set(struct mcf548x_enet_struct *sc) {
/*
* Set physical address
*/
MCF548X_FEC_PALR(chan) = ((mac[0] << 24) +
(mac[1] << 16) +
(mac[2] << 8) +
MCF548X_FEC_PALR(chan) = ((mac[0] << 24) +
(mac[1] << 16) +
(mac[2] << 8) +
mac[3]);
MCF548X_FEC_PAUR(chan) = ((mac[4] << 24)
MCF548X_FEC_PAUR(chan) = ((mac[4] << 24)
+ (mac[5] << 16)) + 0x8808;
}
@@ -437,10 +437,10 @@ int mcf548x_eth_mii_read(
* reading from any PHY's register is done by properly
* programming the FEC's MII data register.
*/
MCF548X_FEC_MMFR(chan) = (MCF548X_FEC_MMFR_ST_01 |
MCF548X_FEC_MMFR_OP_READ |
MCF548X_FEC_MMFR_TA_10 |
MCF548X_FEC_MMFR_PA(phyAddr) |
MCF548X_FEC_MMFR(chan) = (MCF548X_FEC_MMFR_ST_01 |
MCF548X_FEC_MMFR_OP_READ |
MCF548X_FEC_MMFR_TA_10 |
MCF548X_FEC_MMFR_PA(phyAddr) |
MCF548X_FEC_MMFR_RA(regAddr));
/*
@@ -494,11 +494,11 @@ static int mcf548x_eth_mii_write(
int chan = sc->phy_chan;
int timeout = 0xffff;
MCF548X_FEC_MMFR(chan) = (MCF548X_FEC_MMFR_ST_01 |
MCF548X_FEC_MMFR_OP_WRITE |
MCF548X_FEC_MMFR_TA_10 |
MCF548X_FEC_MMFR_PA(phyAddr) |
MCF548X_FEC_MMFR_RA(regAddr) |
MCF548X_FEC_MMFR(chan) = (MCF548X_FEC_MMFR_ST_01 |
MCF548X_FEC_MMFR_OP_WRITE |
MCF548X_FEC_MMFR_TA_10 |
MCF548X_FEC_MMFR_PA(phyAddr) |
MCF548X_FEC_MMFR_RA(regAddr) |
MCF548X_FEC_MMFR_DATA(data));
/*
@@ -546,7 +546,7 @@ static int mcf548x_fec_reset(struct mcf548x_enet_struct *sc) {
*/
MCF548X_FEC_FECRFSR(chan) = ~0;
MCF548X_FEC_FECTFSR(chan) = ~0;
/*
* reset the FIFOs
*/
@@ -555,17 +555,17 @@ static int mcf548x_fec_reset(struct mcf548x_enet_struct *sc) {
for (delay = 0;delay < 16*4;delay++) {};
MCF548X_FEC_FRST(chan) = 0x01000000;
/*
* Issue a reset command to the FEC chip
*/
MCF548X_FEC_ECR(chan) |= MCF548X_FEC_ECR_RESET;
/*
* wait at least 16 clock cycles
*/
for (delay = 0;delay < 16*4;delay++) {};
return true;
}
@@ -585,7 +585,7 @@ void mcf548x_fec_off(struct mcf548x_enet_struct *sc)
{
int counter = 0xffff;
int chan = sc->chan;
#if defined(ETH_DEBUG)
uint32_t phyStatus;
@@ -647,7 +647,7 @@ void mcf548x_fec_off(struct mcf548x_enet_struct *sc)
*/
MCF548X_FEC_ECR(chan) &= ~(MCF548X_FEC_ECR_ETHER_EN);
/*
/*
* cleanup all buffers
*/
mcf548x_fec_rx_bd_cleanup(sc);
@@ -686,7 +686,7 @@ void mcf548x_fec_irq_handler(rtems_vector_number vector)
if (ievent & MCF548X_FEC_EIR_RFERR) {
sc->rxOverrun++;
}
/*
/*
* fatal error ocurred?
*/
if (ievent & (MCF548X_FEC_EIR_RFERR | MCF548X_FEC_EIR_XFERR)) {
@@ -704,8 +704,8 @@ void mcf548x_mcdma_rx_irq_handler(void * param)
/* Frame received? */
if(MCDMA_GET_PENDING(sc->rxDmaChan)) {
MCDMA_CLR_PENDING(sc->rxDmaChan);
mcdma_glue_irq_disable(sc->rxDmaChan);/*Disable receive ints*/
mcdma_glue_irq_disable(sc->rxDmaChan);/*Disable receive ints*/
sc->rxInterrupts++; /* Rx int has occurred */
rtems_event_send(sc->rxDaemonTid, INTERRUPT_EVENT);
}
@@ -722,12 +722,12 @@ void mcf548x_mcdma_tx_irq_handler(void * param)
if(MCDMA_GET_PENDING(sc->txDmaChan)) {
MCDMA_CLR_PENDING(sc->txDmaChan);
mcdma_glue_irq_disable(sc->txDmaChan);/*Disable tx ints*/
sc->txInterrupts++; /* Tx int has occurred */
rtems_event_send(sc->txDaemonTid, INTERRUPT_EVENT);
rtems_event_send(sc->txDaemonTid, INTERRUPT_EVENT);
}
}
@@ -753,9 +753,9 @@ static void mcf548x_fec_retire_tbd(struct mcf548x_enet_struct *sc,
* Clear already transmitted BDs first. Will not work calling same
* from fecExceptionHandler(TFINT).
*/
while ((sc->txBdActiveCount > 0) &&
(force ||
(force ||
((MCF548X_FEC_TBD_READY & GET_BD_STATUS(sc->txBd+sc->txBdTail))
== 0x0))) {
if (sc->txMbuf[sc->txBdTail] != NULL) {
@@ -768,7 +768,7 @@ static void mcf548x_fec_retire_tbd(struct mcf548x_enet_struct *sc,
sc->txBdActiveCount--;
if(++sc->txBdTail >= sc->txBdCount) {
sc->txBdTail = 0;
}
}
}
}
@@ -804,11 +804,11 @@ static void mcf548x_fec_sendpacket(struct ifnet *ifp,struct mbuf *m) {
* Wait for buffer descriptor to become available.
*/
if((sc->txBdActiveCount + nAdded) == sc->txBdCount) {
/*
* Clear old events
*/
MCDMA_CLR_PENDING(sc->txDmaChan);
MCDMA_CLR_PENDING(sc->txDmaChan);
/*
* Wait for buffer descriptor to become available.
* Note that the buffer descriptors are checked
@@ -822,11 +822,11 @@ static void mcf548x_fec_sendpacket(struct ifnet *ifp,struct mbuf *m) {
* an interrupt.
*/
mcf548x_fec_retire_tbd(sc,false);
while((sc->txBdActiveCount + nAdded) == sc->txBdCount) {
mcdma_glue_irq_enable(sc->txDmaChan);
rtems_bsdnet_event_receive(INTERRUPT_EVENT,
RTEMS_WAIT | RTEMS_EVENT_ANY,
rtems_bsdnet_event_receive(INTERRUPT_EVENT,
RTEMS_WAIT | RTEMS_EVENT_ANY,
RTEMS_NO_TIMEOUT, &events);
mcf548x_fec_retire_tbd(sc,false);
}
@@ -838,7 +838,7 @@ static void mcf548x_fec_sendpacket(struct ifnet *ifp,struct mbuf *m) {
*/
struct mbuf *n;
MFREE(m, n);
m = n;
m = n;
if(l != NULL) {
l->m_next = m;
}
@@ -847,7 +847,7 @@ static void mcf548x_fec_sendpacket(struct ifnet *ifp,struct mbuf *m) {
/*
* Flush the buffer for this descriptor
*/
rtems_cache_flush_multiple_data_lines((const void *)mtod(m, void *),
rtems_cache_flush_multiple_data_lines((const void *)mtod(m, void *),
m->m_len);
/*
* Fill in the buffer descriptor,
@@ -859,12 +859,12 @@ static void mcf548x_fec_sendpacket(struct ifnet *ifp,struct mbuf *m) {
* FIXME: do not send interrupt after every frame
* doing this every quarter of BDs is much more efficent
*/
status = (((m->m_next == NULL)
status = (((m->m_next == NULL)
? MCF548X_FEC_TBD_LAST | MCF548X_FEC_TBD_INT
: 0)
| ((sc->txBdHead == sc->txBdCount-1)
? MCF548X_FEC_TBD_WRAP
:0 ));
:0 ));
/*
* Don't set the READY flag till the
* whole packet has been readied.
@@ -874,7 +874,7 @@ static void mcf548x_fec_sendpacket(struct ifnet *ifp,struct mbuf *m) {
}
else {
firstBd = thisBd;
}
}
data_ptr = mtod(m, void *);
data_len = m->m_len;
@@ -898,10 +898,10 @@ static void mcf548x_fec_sendpacket(struct ifnet *ifp,struct mbuf *m) {
*/
if(m == NULL) {
if(nAdded) {
SET_BD_STATUS(firstBd,
SET_BD_STATUS(firstBd,
GET_BD_STATUS(firstBd) | MCF548X_FEC_TBD_READY);
MCD_continDma(sc->txDmaChan);
sc->txBdActiveCount += nAdded;
sc->txBdActiveCount += nAdded;
}
break;
}
@@ -924,9 +924,9 @@ void mcf548x_fec_txDaemon(void *arg)
* Wait for packet
*/
mcdma_glue_irq_enable(sc->txDmaChan);
rtems_bsdnet_event_receive(START_TRANSMIT_EVENT|INTERRUPT_EVENT,
RTEMS_EVENT_ANY | RTEMS_WAIT,
RTEMS_NO_TIMEOUT,
rtems_bsdnet_event_receive(START_TRANSMIT_EVENT|INTERRUPT_EVENT,
RTEMS_EVENT_ANY | RTEMS_WAIT,
RTEMS_NO_TIMEOUT,
&events);
/*
@@ -974,7 +974,7 @@ static void mcf548x_fec_rxDaemon(void *arg){
* Input packet handling loop
*/
rxBdIndex = 0;
for (;;) {
/*
* Clear old events
@@ -986,30 +986,30 @@ static void mcf548x_fec_rxDaemon(void *arg){
bd = sc->rxBd + rxBdIndex;
status = GET_BD_STATUS( bd );
len = GET_BD_LENGTH( bd );
/*
* Loop through BDs until we find an empty one. This indicates that
* the DMA is still using it.
*/
while( !(status & MCF548X_FEC_RBD_EMPTY) ) {
/*
* Remember the data pointer from this transfer.
*/
dptr = GET_BD_BUFFER(bd);
m = sc->rxMbuf[rxBdIndex];
m->m_len = m->m_pkthdr.len = (len
- sizeof(uint32_t)
m->m_len = m->m_pkthdr.len = (len
- sizeof(uint32_t)
- sizeof(struct ether_header));
eh = mtod(m, struct ether_header *);
m->m_data += sizeof(struct ether_header);
ether_input(ifp, eh, m);
/*
* Done w/ the BD. Clean it.
*/
sc->rxMbuf[rxBdIndex] = NULL;
/*
* Add a new buffer to the ring.
*/
@@ -1019,9 +1019,9 @@ static void mcf548x_fec_rxDaemon(void *arg){
size = ETHER_MAX_LEN;
sc->rxMbuf[rxBdIndex] = m;
rtems_cache_invalidate_multiple_data_lines(mtod(m,const void *),
rtems_cache_invalidate_multiple_data_lines(mtod(m,const void *),
size);
SET_BD_BUFFER(bd,mtod(m, void *));
SET_BD_LENGTH(bd,size);
SET_BD_STATUS(bd,
@@ -1031,7 +1031,7 @@ static void mcf548x_fec_rxDaemon(void *arg){
? MCF548X_FEC_RBD_WRAP
: 0)
);
/*
* advance to next BD
*/
@@ -1049,9 +1049,9 @@ static void mcf548x_fec_rxDaemon(void *arg){
* Unmask RXF (Full frame received) event
*/
mcdma_glue_irq_enable(sc->rxDmaChan);
rtems_bsdnet_event_receive (INTERRUPT_EVENT | FATAL_INT_EVENT,
RTEMS_WAIT | RTEMS_EVENT_ANY,
rtems_bsdnet_event_receive (INTERRUPT_EVENT | FATAL_INT_EVENT,
RTEMS_WAIT | RTEMS_EVENT_ANY,
RTEMS_NO_TIMEOUT, &events);
if (events & FATAL_INT_EVENT) {
/*
@@ -1100,7 +1100,7 @@ static void mcf548x_fec_initialize_hardware(struct mcf548x_enet_struct *sc)
MCF548X_FEC_RCR(chan) = (MCF548X_FEC_RCR_MAX_FL(ETHER_MAX_LEN)
| MCF548X_FEC_RCR_FCE
| MCF548X_FEC_RCR_MII_MODE);
/*
* Set FEC-Lite transmit control register (X_CNTRL)
* full-duplex, heartbeat disabled
@@ -1183,7 +1183,7 @@ static void mcf548x_fec_startDMA(struct mcf548x_enet_struct *sc)
/*
* Enable the SmartDMA receive task.
*/
mcdma_rc = MCD_startDma
mcdma_rc = MCD_startDma
(sc->rxDmaChan, /* the channel on which to run the DMA */
(void *)sc->rxBd, /* the address to move data from, or buffer-descriptor addr */
0, /* the amount to increment the source address per transfer */
@@ -1207,7 +1207,7 @@ static void mcf548x_fec_startDMA(struct mcf548x_enet_struct *sc)
if (mcdma_rc != MCD_OK) {
rtems_panic("FEC: cannot start rx DMA");
}
mcdma_rc = MCD_startDma
mcdma_rc = MCD_startDma
(sc->txDmaChan, /* the channel on which to run the DMA */
(void *)sc->txBd, /* the address to move data from, or buffer-descriptor addr */
0, /* the amount to increment the source address per transfer */
@@ -1250,7 +1250,7 @@ static void mcf548x_fec_init(void *arg)
*/
sc->rxBd = SRAM_RXBD_BASE(_SysSramBase,chan);
sc->txBd = SRAM_TXBD_BASE(_SysSramBase,chan);
if(!sc->rxBd || !sc->txBd)
rtems_panic ("No memory for BDs");
/*
@@ -1261,11 +1261,11 @@ static void mcf548x_fec_init(void *arg)
/*
* Allocate a set of mbuf pointers
*/
sc->rxMbuf =
sc->rxMbuf =
malloc(sc->rxBdCount * sizeof *sc->rxMbuf, M_MBUF, M_NOWAIT);
sc->txMbuf =
sc->txMbuf =
malloc(sc->txBdCount * sizeof *sc->txMbuf, M_MBUF, M_NOWAIT);
if(!sc->rxMbuf || !sc->txMbuf)
rtems_panic ("No memory for mbuf pointers");
@@ -1289,7 +1289,7 @@ static void mcf548x_fec_init(void *arg)
rtems_panic ("Can't attach MFC54xx FEX interrupt handler\n");
}
MCF548X_INTC_ICRn(MCF548X_FEC_IRQ_VECTOR(chan) % 64) =
MCF548X_INTC_ICRn(MCF548X_FEC_IRQ_VECTOR(chan) % 64) =
MCF548X_INTC_ICRn_IL(FEC_IRQ_LEVEL) |
MCF548X_INTC_ICRn_IP(FEC_IRQ_PRIORITY);
@@ -1308,16 +1308,16 @@ static void mcf548x_fec_init(void *arg)
*/
txTaskName[3] = '0'+chan;
rxTaskName[3] = '0'+chan;
sc->txDaemonTid = rtems_bsdnet_newproc(txTaskName, 4096,
sc->txDaemonTid = rtems_bsdnet_newproc(txTaskName, 4096,
mcf548x_fec_txDaemon, sc);
sc->rxDaemonTid = rtems_bsdnet_newproc(rxTaskName, 4096,
sc->rxDaemonTid = rtems_bsdnet_newproc(rxTaskName, 4096,
mcf548x_fec_rxDaemon, sc);
/*
* Clear SmartDMA task interrupt pending bits.
*/
MCDMA_CLR_PENDING(sc->rxDmaChan );
MCDMA_CLR_PENDING(sc->txDmaChan );
/*
* start the DMA channels
*/
@@ -1359,7 +1359,7 @@ static void enet_stats (struct mcf548x_enet_struct *sc)
printf (" Bad CRC:%-8lu", sc->rxBadCRC);
printf (" Overrun:%-8lu", sc->rxOverrun);
printf (" Collision:%-8lu\n", sc->rxCollision);
printf (" Tx Interrupts:%-8lu", sc->txInterrupts);
printf (" Deferred:%-8lu", sc->txDeferred);
printf (" Late Collision:%-8lu\n", sc->txLateCollision);
@@ -1371,12 +1371,12 @@ static void enet_stats (struct mcf548x_enet_struct *sc)
/*
* restart the driver, reinit the fec
* this function is responsible to reinitialize the FEC in case a fatal
* this function is responsible to reinitialize the FEC in case a fatal
* error has ocurred. This is needed, wen a RxFIFO Overrun or a TxFIFO underrun
* has ocurred. In these cases, the FEC is automatically disabled, and
* both FIFOs must be reset and the BestComm tasks must be restarted
*
* Note: the daemon tasks will continue to run
* Note: the daemon tasks will continue to run
* (in fact this function will be called in the context of the rx daemon task)
*/
#define NEW_DMA_SETUP
@@ -1430,7 +1430,7 @@ static void mcf548x_fec_restart(struct mcf548x_enet_struct *sc)
* Clear SmartDMA task interrupt pending bits.
*/
MCDMA_CLR_PENDING( sc->rxDmaChan );
/*
* start the DMA channels again
*/
@@ -1491,7 +1491,7 @@ static int mcf548x_fec_ioctl (struct ifnet *ifp, ioctl_command_t command, caddr_
error = (command == SIOCADDMULTI)
? ether_addmulti(ifr, &sc->arpcom)
: ether_delmulti(ifr, &sc->arpcom);
if (error == ENETRESET) {
if (ifp->if_flags & IFF_RUNNING)
error = mcf548x_fec_setMultiFilter(ifp);
@@ -1613,7 +1613,7 @@ int mcf548x_fec_mode_adapt(struct ifnet *ifp)
}
else {
MCF548X_FEC_TCR(chan) |= MCF548X_FEC_TCR_FDEN;
}
}
/*
* store current media state for future compares
*/
@@ -1629,7 +1629,7 @@ int mcf548x_fec_mode_adapt(struct ifnet *ifp)
static void mcf548x_fec_watchdog( struct ifnet *ifp)
{
mcf548x_fec_mode_adapt(ifp);
ifp->if_timer = FEC_WATCHDOG_TIMEOUT;
ifp->if_timer = FEC_WATCHDOG_TIMEOUT;
}
/*

52
c/src/lib/libbsp/m68k/genmcf548x/start/start.S
View File

@@ -55,7 +55,7 @@
.extern _CoreSramBase0
.extern _CoreSramBase1
.extern _CoreSramSize1
.extern mcf548x_init
.extern mcf548x_init
.extern boot_card
.extern _SpInit
@@ -64,7 +64,7 @@
\*===============================================================*/
.global interrupt_vector_table
.global spurious_int_count
.global spurious_int_count
.global start
@@ -339,13 +339,13 @@ PUBLIC (start)
SYM(start):
move.w #0x3700,sr /* disable interrupts */
jmp start_init
/*===============================================================*\
| Sspurious interrupt counter |
\*===============================================================*/
.align 4
.data /* begin of data section */
PUBLIC (spurious_int_count)
PUBLIC (spurious_int_count)
SYM(spurious_int_count):
.long 0 /* spurious interrupt counter */
@@ -353,14 +353,14 @@ SYM(spurious_int_count):
| Function: Default exception handler |
+-----------------------------------------------------------------+
| - stop and disable all interrupts |
| - loop forever |
| - loop forever |
\*===============================================================*/
.text /* start of text section */
.align 4
PUBLIC (asm_default_interrupt)
SYM(asm_default_interrupt):
nop
stop #0x3700 /* stop */
nop
stop #0x3700 /* stop */
bra.w asm_default_interrupt /* loop forever */
/*===============================================================*\
@@ -372,49 +372,49 @@ SYM(asm_default_interrupt):
PUBLIC (asm_spurious_interrupt)
SYM(asm_spurious_interrupt):
add.l #1,spurious_int_count
rte
rte
/*===============================================================*\
| Function: start_init |
+-----------------------------------------------------------------+
| - Disable all intterupts |
| - Disable all intterupts |
| - Setup the internal SRAM |
| - Initialize mcf548x peripherals |
| - Set initial stack pointer |
| - Boot RTEMS
| - Boot RTEMS
\*===============================================================*/
.align 4
PUBLIC (start_init)
SYM(start_init):
move.l #0x01040100,d0 /* invalidate instruction/data/branch cache, disable all caches */
movec d0,cacr
move.l #_CoreSramBase0,d0 /* initialize RAMBAR0 */
add.l #0x21,d0 /* for code & data */
movec d0,rambar0
move.l #_CoreSramBase1,d0 /* initialize RAMBAR1 */
add.l #0x21,d0 /* for code & data */
movec d0,rambar1 /* movec d0,RAMBAR1 */
move.l #__MBAR,d0 /* initialize MBAR */
movec d0,mbar
move.l #_CoreSramBase1,d0 /* set sp to end of Core SRAM temporarily */
add.l #_CoreSramSize1,d0
move.l d0,sp
move.l #0,d0 /* initialize frame pointer */
movea.l d0,a6
movea.l d0,a6
jsr mcf548x_init /* Initialize mcf548x peripherals */
move.l #_SpInit,sp /* relocate sp */
move.l #_SpInit,sp /* relocate sp */
clrl d0 /* clear d0 */
movel d0,a7@- /* command line == 0 */
jsr boot_card /* boot rtems */
movel a7@+,d0
@@ -422,10 +422,10 @@ SYM(start_init):
exit_multitasking:
nop
nop
halt
bra exit_multitasking
halt
bra exit_multitasking
.end /* end of start.S module */
.end /* end of start.S module */

2
c/src/lib/libbsp/m68k/idp/timer/timer.c
View File

@@ -1,4 +1,4 @@
/*
/*
* Code Modified for the MC68230 by Doug McBride, Colorado Space Grant College
*
* COPYRIGHT (c) 1989-1999.

4
c/src/lib/libbsp/m68k/mcf5206elite/i2c/i2c.c
View File

@@ -72,7 +72,7 @@ i2c_transfer_wait_sema(i2c_bus_number bus, i2c_message *msg, int nmsg)
);
if (sc != RTEMS_SUCCESSFUL)
return I2C_RESOURCE_NOT_AVAILABLE;
sc = i2c_transfer(bus, nmsg, msg,
sc = i2c_transfer(bus, nmsg, msg,
i2c_transfer_sema_done_func, &sema);
if (sc != RTEMS_SUCCESSFUL)
{
@@ -107,7 +107,7 @@ i2c_transfer_wait_poll(i2c_bus_number bus, i2c_message *msg, int nmsg)
volatile bool poll_done_flag;
rtems_status_code sc;
poll_done_flag = false;
sc = i2c_transfer(bus, nmsg, msg,
sc = i2c_transfer(bus, nmsg, msg,
i2c_transfer_poll_done_func,(void *)&poll_done_flag);
if (sc != RTEMS_SUCCESSFUL)
return sc;

2
c/src/lib/libbsp/m68k/mcf5206elite/i2c/i2cdrv.c
View File

@@ -119,7 +119,7 @@ i2cdrv_unload(void)
i2cdrv_bus_clock_div_current = i2cdrv_bus_clock_div[qel->bus];
mcfmbus_select_clock_divider(&mbus, i2cdrv_bus_clock_div_current);
}
sc = mcfmbus_i2c_transfer(&mbus, qel->nmsg, qel->msg,
sc = mcfmbus_i2c_transfer(&mbus, qel->nmsg, qel->msg,
i2cdrv_done,qel);
if (sc != RTEMS_SUCCESSFUL)
{

14
c/src/lib/libbsp/m68k/mcf52235/console/console.c
View File

@@ -135,7 +135,7 @@ IntUartSet(int minor, int baud, int databits, int parity, int stopbits,
Description : This provides the hardware-dependent portion of tcsetattr().
value and sets it. At the moment this just sets the baud rate.
Note: The highest baudrate is 115200 as this stays within
Note: The highest baudrate is 115200 as this stays within
an error of +/- 5% at 25MHz processor clock
***************************************************************************/
static int IntUartSetAttributes(int minor, const struct termios *t)
@@ -334,9 +334,9 @@ static void IntUartInitialize(void)
/***************************************************************************
Function : IntUartInterruptWrite
Description : This writes a single character to the appropriate uart
Description : This writes a single character to the appropriate uart
channel. This is either called during an interrupt or in the user's task
to initiate a transmit sequence. Calling this routine enables Tx
to initiate a transmit sequence. Calling this routine enables Tx
interrupts.
***************************************************************************/
static int IntUartInterruptWrite(int minor, const char *buf, int len)
@@ -454,7 +454,7 @@ static int IntUartTaskRead(int minor)
/***************************************************************************
Function : IntUartPollRead
Description : This reads a character from the internal uart. It returns
Description : This reads a character from the internal uart. It returns
to the caller without blocking if not character is waiting.
***************************************************************************/
static int IntUartPollRead(int minor)
@@ -468,8 +468,8 @@ static int IntUartPollRead(int minor)
/***************************************************************************
Function : IntUartPollWrite
Description : This writes out each character in the buffer to the
appropriate internal uart channel waiting till each one is sucessfully
Description : This writes out each character in the buffer to the
appropriate internal uart channel waiting till each one is sucessfully
transmitted.
***************************************************************************/
static int IntUartPollWrite(int minor, const char *buf, int len)
@@ -530,7 +530,7 @@ rtems_device_driver console_initialize(rtems_device_major_number major,
/***************************************************************************
Function : console_open
Description : This actually opens the device depending on the minor
Description : This actually opens the device depending on the minor
number set during initialisation. The device specific access routines are
passed to termios when the devices is opened depending on whether it is
polled or not.

6
c/src/lib/libbsp/m68k/mcf52235/include/bsp.h
View File

@@ -1,7 +1,7 @@
/*
* mcf52235 BSP header file
*/
#ifndef _BSP_H
#define _BSP_H
@@ -22,9 +22,9 @@ extern "C" {
/***************************************************************************/
/** Hardware data structure headers **/
#include <mcf5223x/mcf5223x.h>
/* Declare base address of peripherals area */
#define __IPSBAR ((vuint8 *) 0x40000000)
#define __IPSBAR ((vuint8 *) 0x40000000)
/***************************************************************************/
/** Network driver configuration **/

26
c/src/lib/libbsp/m68k/mcf52235/start/start.S
View File

@@ -22,7 +22,7 @@
.extern _StackInit
BEGIN_CODE
PUBLIC (_INTERRUPT_VECTOR)
SYM(_INTERRUPT_VECTOR):
@@ -313,12 +313,12 @@ _cfm_msec: .long 0x00000000
*/
.align 4
PUBLIC (_uhoh)
SYM(_uhoh):
SYM(_uhoh):
nop | Leave spot for breakpoint
stop #0x2700 | Stop with interrupts disabled
stop #0x2700 | Stop with interrupts disabled
bra.w SYM(_uhoh) | Stuck forever
/*
/*
* Spurious Interrupt Handler
*/
.align 4
@@ -327,18 +327,18 @@ SYM(_spuriousInterrupt):
addql #1, SYM(_M68kSpuriousInterruptCount)
rte
/*
/*
* Write VBR Register
*/
.align 4
PUBLIC (_wr_vbr)
SYM(_wr_vbr):
move.l 4(sp), d0
movec d0, vbr
movec d0, vbr
nop
rts
rts
/*
/*
* Board startup
* Disable watchdog, interrupts
* Enable sram
@@ -359,7 +359,7 @@ SYM(start):
add.l #0x21, d0
movec d0, %rambar
/* Locate Stack Pointer */
/* Locate Stack Pointer */
move.l #_StackInit, sp
/* Initialize FLASHBAR */
@@ -371,7 +371,7 @@ SYM(start):
_continue_startup:
/* Locate Stack Pointer */
/* Locate Stack Pointer */
move.l #_StackInit, sp
/* Save off intial D0 and D1 to RAM */
@@ -385,8 +385,8 @@ _continue_startup:
jmp SYM(Init52235)
_change_flashbar:
/*
* The following sequence is used to set FLASHBAR. Since we may
/*
* The following sequence is used to set FLASHBAR. Since we may
* be executing from Flash, we must put the routine into SRAM for
* execution and then jump back to Flash using the new address.
*
@@ -402,7 +402,7 @@ _change_flashbar:
* This routine is not necessary if the default Flash address
* (0x00000000) is used.
*
* If running in SRAM, change_flashbar should not be executed
* If running in SRAM, change_flashbar should not be executed
*/
move.l #RamBase, a0

2
c/src/lib/libbsp/m68k/mcf52235/startup/bspgetcpuclockspeed.c
View File

@@ -5,7 +5,7 @@
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*
*
* $Id$
*/

200
c/src/lib/libbsp/m68k/mcf52235/startup/cfinit.c
View File

@@ -1,15 +1,15 @@
/*********************************************************************
* Initialisation Code for ColdFire MCF52235 Processor *
**********************************************************************
Generated by ColdFire Initialisation Utility 2.10.8
Fri May 23 14:39:00 2008
MicroAPL Ltd makes no warranties in respect of the suitability
of this code for any particular purpose, and accepts
no liability for any loss arising out of its use. The person or
persons making use of this file must make the final evaluation
as to its suitability and correctness for a particular application.
Generated by ColdFire Initialisation Utility 2.10.8
Fri May 23 14:39:00 2008
MicroAPL Ltd makes no warranties in respect of the suitability
of this code for any particular purpose, and accepts
no liability for any loss arising out of its use. The person or
persons making use of this file must make the final evaluation
as to its suitability and correctness for a particular application.
*/
/* Processor/internal bus clocked at 60.00 MHz */
@@ -112,11 +112,11 @@ static void disable_watchdog_timer(void)
**********************************************************************/
static void init_clock_config(void)
{
/* Clock source is 25.0000 MHz external crystal
Clock mode: Normal PLL mode
Processor/Bus clock frequency = 60.00 MHz
Loss of clock detection disabled
Reset on loss of lock disabled
/* Clock source is 25.0000 MHz external crystal
Clock mode: Normal PLL mode
Processor/Bus clock frequency = 60.00 MHz
Loss of clock detection disabled
Reset on loss of lock disabled
*/
/* Divide 25.0000 MHz clock to get 5.00 MHz PLL input clock */
@@ -137,10 +137,10 @@ static void init_clock_config(void)
**********************************************************************/
static void init_ipsbar(void)
{
/* Base address of internal peripherals (IPSBAR) = 0x40000000
/* Base address of internal peripherals (IPSBAR) = 0x40000000
Note: Processor powers up with IPS base address = 0x40000000
Write to IPS base + 0x00000000 to set new value
Note: Processor powers up with IPS base address = 0x40000000
Write to IPS base + 0x00000000 to set new value
*/
*(vuint32 *) 0x40000000 = (vuint32) __IPSBAR + 1; /* +1 for Enable */
}
@@ -150,27 +150,27 @@ static void init_ipsbar(void)
**********************************************************************/
static void init_flash_controller(void)
{
/* Internal Flash module enabled, address = $00000000
Flash state machine clock = 197.37 kHz
All access types except CPU space/interrupt acknowledge cycle allowed
Flash is Write-Protected
All interrupts disabled
/* Internal Flash module enabled, address = $00000000
Flash state machine clock = 197.37 kHz
All access types except CPU space/interrupt acknowledge cycle allowed
Flash is Write-Protected
All interrupts disabled
*/
MCF_CFM_CFMCLKD = MCF_CFM_CFMCLKD_PRDIV8 | MCF_CFM_CFMCLKD_DIV(0x12);
MCF_CFM_CFMMCR = 0;
/* WARNING: Setting FLASHBAR[6]=1 in order to turn off address speculation
This is a workaround for a hardware problem whereby a speculative
access to the Flash occuring at the same time as an SRAM access
can return corrupt data.
/* WARNING: Setting FLASHBAR[6]=1 in order to turn off address speculation
This is a workaround for a hardware problem whereby a speculative
access to the Flash occuring at the same time as an SRAM access
can return corrupt data.
This workaround can result in a 4% - 9% performance penalty. Other workarounds
are possible for certain applications.
This workaround can result in a 4% - 9% performance penalty. Other workarounds
are possible for certain applications.
For example, if you know that you will not be using the top 32 KB of the Flash
you can place the SRAM base address at 0x20038000
For example, if you know that you will not be using the top 32 KB of the Flash
you can place the SRAM base address at 0x20038000
See Device Errata for further details
See Device Errata for further details
*/
asm("move.l #0x00000161,%d0");
asm("movec %d0,%FLASHBAR");
@@ -211,13 +211,13 @@ static void init_flexcan(void)
**********************************************************************/
static void init_bus_config(void)
{
/* Use round robin arbitration scheme
Assigned priorities (highest first):
Ethernet
DMA Controller
ColdFire Core
DMA bandwidth control disabled
Park on last active bus master
/* Use round robin arbitration scheme
Assigned priorities (highest first):
Ethernet
DMA Controller
ColdFire Core
DMA bandwidth control disabled
Park on last active bus master
*/
MCF_SCM_MPARK = MCF_SCM_MPARK_M3PRTY(0x3) |
MCF_SCM_MPARK_M2PRTY(0x2) | (0x1 << 16);
@@ -228,9 +228,9 @@ static void init_bus_config(void)
**********************************************************************/
static void init_sram(void)
{
/* Internal SRAM module enabled, address = $20000000
DMA access to SRAM block disabled
All access types (supervisor and user) allowed
/* Internal SRAM module enabled, address = $20000000
DMA access to SRAM block disabled
All access types (supervisor and user) allowed
*/
asm("move.l #0x20000001,%d0");
asm("movec %d0,%RAMBAR");
@@ -241,8 +241,8 @@ static void init_sram(void)
**********************************************************************/
static void init_power_management(void)
{
/* On executing STOP instruction, processor enters RUN mode
Mode is exited when an interrupt of level 1 or higher is received
/* On executing STOP instruction, processor enters RUN mode
Mode is exited when an interrupt of level 1 or higher is received
*/
MCF_PMM_LPICR = MCF_PMM_LPICR_ENBSTOP;
MCF_PMM_LPCR = MCF_PMM_LPCR_LPMD_RUN;
@@ -279,12 +279,12 @@ static void init_dma_timers(void)
**********************************************************************/
static void init_gp_timer(void)
{
/*
GPT disabled (GPTASCR1[GPTEN] = 0)
Channel 0 configured as GPIO input
Channel 1 configured as GPIO input
Channel 2 configured as GPIO input
Channel 3 configured as GPIO input
/*
GPT disabled (GPTASCR1[GPTEN] = 0)
Channel 0 configured as GPIO input
Channel 1 configured as GPIO input
Channel 2 configured as GPIO input
Channel 3 configured as GPIO input
*/
MCF_GPT_GPTSCR1 = 0;
MCF_GPT_GPTDDR = 0;
@@ -325,14 +325,14 @@ static void init_watchdog_timer(void)
**********************************************************************/
static void init_interrupt_controller(void)
{
/* Configured interrupt sources in order of priority...
Level 7: External interrupt /IRQ7, (initially masked)
Level 6: External interrupt /IRQ6, (initially masked)
Level 5: External interrupt /IRQ5, (initially masked)
Level 4: External interrupt /IRQ4, (initially masked)
Level 3: External interrupt /IRQ3, (initially masked)
Level 2: External interrupt /IRQ2, (initially masked)
Level 1: External interrupt /IRQ1, (initially masked)
/* Configured interrupt sources in order of priority...
Level 7: External interrupt /IRQ7, (initially masked)
Level 6: External interrupt /IRQ6, (initially masked)
Level 5: External interrupt /IRQ5, (initially masked)
Level 4: External interrupt /IRQ4, (initially masked)
Level 3: External interrupt /IRQ3, (initially masked)
Level 2: External interrupt /IRQ2, (initially masked)
Level 1: External interrupt /IRQ1, (initially masked)
*/
MCF_INTC0_ICR1 = 0;
MCF_INTC0_ICR2 = 0;
@@ -426,8 +426,8 @@ static void init_interrupt_controller(void)
**********************************************************************/
static void init_pin_assignments(void)
{
/* Pin assignments for port NQ
Pins NQ7-NQ1 : EdgePort GPIO/IRQ
/* Pin assignments for port NQ
Pins NQ7-NQ1 : EdgePort GPIO/IRQ
*/
MCF_GPIO_DDRNQ = 0;
MCF_GPIO_PNQPAR = MCF_GPIO_PNQPAR_PNQPAR7(0x1) |
@@ -437,8 +437,8 @@ static void init_pin_assignments(void)
MCF_GPIO_PNQPAR_PNQPAR3(0x1) |
MCF_GPIO_PNQPAR_PNQPAR2(0x1) | MCF_GPIO_PNQPAR_PNQPAR1(0x1);
/* Pin assignments for port GP
Pins PG7-PG0 : EdgePort GPIO/IRQ
/* Pin assignments for port GP
Pins PG7-PG0 : EdgePort GPIO/IRQ
*/
MCF_GPIO_DDRGP = 0;
MCF_GPIO_PGPPAR = MCF_GPIO_PGPPAR_PGPPAR7 |
@@ -449,16 +449,16 @@ static void init_pin_assignments(void)
MCF_GPIO_PGPPAR_PGPPAR2 |
MCF_GPIO_PGPPAR_PGPPAR1 | MCF_GPIO_PGPPAR_PGPPAR0;
/* Pin assignments for port DD
Pin DD7 : DDATA[3]
Pin DD6 : DDATA[2]
Pin DD5 : DDATA[1]
Pin DD4 : DDATA[0]
Pin DD3 : PST[3]
Pin DD2 : PST[2]
Pin DD1 : PST[1]
Pin DD0 : PST[0]
CCON[PSTEN] = 1 to enable PST/DDATA function
/* Pin assignments for port DD
Pin DD7 : DDATA[3]
Pin DD6 : DDATA[2]
Pin DD5 : DDATA[1]
Pin DD4 : DDATA[0]
Pin DD3 : PST[3]
Pin DD2 : PST[2]
Pin DD1 : PST[1]
Pin DD0 : PST[0]
CCON[PSTEN] = 1 to enable PST/DDATA function
*/
MCF_GPIO_DDRDD = 0;
MCF_GPIO_PDDPAR = MCF_GPIO_PDDPAR_PDDPAR7 |
@@ -470,75 +470,75 @@ static void init_pin_assignments(void)
MCF_GPIO_PDDPAR_PDDPAR1 | MCF_GPIO_PDDPAR_PDDPAR0;
MCF_CIM_CCON = 0x0021;
/* Pin assignments for port AN
Pins are all GPIO inputs
/* Pin assignments for port AN
Pins are all GPIO inputs
*/
MCF_GPIO_DDRAN = 0;
MCF_GPIO_PANPAR = 0;
/* Pin assignments for port AS
Pins are all GPIO inputs
/* Pin assignments for port AS
Pins are all GPIO inputs
*/
MCF_GPIO_DDRAS = 0;
MCF_GPIO_PASPAR = 0;
/* Pin assignments for port LD
Pins are all GPIO inputs
/* Pin assignments for port LD
Pins are all GPIO inputs
*/
MCF_GPIO_DDRLD = 0;
MCF_GPIO_PLDPAR = 0;
/* Pin assignments for port QS
Pins are all GPIO inputs
/* Pin assignments for port QS
Pins are all GPIO inputs
*/
MCF_GPIO_DDRQS = 0;
MCF_GPIO_PQSPAR = 0;
/* Pin assignments for port TA
Pins are all GPIO inputs
/* Pin assignments for port TA
Pins are all GPIO inputs
*/
MCF_GPIO_DDRTA = 0;
MCF_GPIO_PTAPAR = 0;
/* Pin assignments for port TC
Pins are all GPIO inputs
/* Pin assignments for port TC
Pins are all GPIO inputs
*/
MCF_GPIO_DDRTC = 0;
MCF_GPIO_PTCPAR = 0;
/* Pin assignments for port TD
Pins are all GPIO inputs
/* Pin assignments for port TD
Pins are all GPIO inputs
*/
MCF_GPIO_DDRTD = 0;
MCF_GPIO_PTDPAR = 0;
/* Pin assignments for port UA
Pin UA3 : UART 0 clear-to-send, UCTS0
Pin UA2 : UART 0 request-to-send, URTS0
Pin UA1 : UART 0 receive data, URXD0
Pin UA0 : UART 0 transmit data, UTXD0
/* Pin assignments for port UA
Pin UA3 : UART 0 clear-to-send, UCTS0
Pin UA2 : UART 0 request-to-send, URTS0
Pin UA1 : UART 0 receive data, URXD0
Pin UA0 : UART 0 transmit data, UTXD0
*/
MCF_GPIO_DDRUA = 0;
MCF_GPIO_PUAPAR = MCF_GPIO_PUAPAR_PUAPAR3(0x1) |
MCF_GPIO_PUAPAR_PUAPAR2(0x1) |
MCF_GPIO_PUAPAR_PUAPAR1(0x1) | MCF_GPIO_PUAPAR_PUAPAR0(0x1);
/* Pin assignments for port UB
Pin UB3 : UART 1 clear-to-send, UCTS1
Pin UB2 : UART 1 request-to-send, URTS1
Pin UB1 : UART 1 receive data, URXD1
Pin UB0 : UART 1 transmit data, UTXD1
/* Pin assignments for port UB
Pin UB3 : UART 1 clear-to-send, UCTS1
Pin UB2 : UART 1 request-to-send, URTS1
Pin UB1 : UART 1 receive data, URXD1
Pin UB0 : UART 1 transmit data, UTXD1
*/
MCF_GPIO_DDRUB = 0;
MCF_GPIO_PUBPAR = MCF_GPIO_PUBPAR_PUBPAR3(0x1) |
MCF_GPIO_PUBPAR_PUBPAR2(0x1) |
MCF_GPIO_PUBPAR_PUBPAR1(0x1) | MCF_GPIO_PUBPAR_PUBPAR0(0x1);
/* Pin assignments for port UC
Pin UC3 : UART 2 clear-to-send, UCTS2
Pin UC2 : UART 2 request-to-send, URTS2
Pin UC1 : UART 2 receive data, URXD2
Pin UC0 : UART 2 transmit data, UTXD2
/* Pin assignments for port UC
Pin UC3 : UART 2 clear-to-send, UCTS2
Pin UC2 : UART 2 request-to-send, URTS2
Pin UC1 : UART 2 receive data, URXD2
Pin UC0 : UART 2 transmit data, UTXD2
*/
MCF_GPIO_DDRUC = 0;
MCF_GPIO_PUCPAR = MCF_GPIO_PUCPAR_PUCPAR3 |

14
c/src/lib/libbsp/m68k/mcf52235/startup/init52235.c
View File

@@ -30,13 +30,13 @@ void Init52235(void)
register uint32_t *dp, *sp;
register uint8_t *dbp, *sbp;
/*
/*
* Initialize the hardware
*/
init_main();
/*
* Copy the vector table to RAM
/*
* Copy the vector table to RAM
*/
if (_VBR != _INTERRUPT_VECTOR) {
@@ -49,8 +49,8 @@ void Init52235(void)
_wr_vbr((uint32_t) _VBR);
/*
* Move initialized data from ROM to RAM.
/*
* Move initialized data from ROM to RAM.
*/
if (_data_src_start != _data_dest_start) {
dbp = (uint8_t *) _data_dest_start;
@@ -60,8 +60,8 @@ void Init52235(void)
*dbp++ = *sbp++;
}
/*
* Zero uninitialized data
/*
* Zero uninitialized data
*/
if (_clear_start != _clear_end) {

20
c/src/lib/libbsp/m68k/mcf5235/console/console.c
View File

@@ -27,7 +27,7 @@ static int IntUartInterruptWrite (int minor, const char *buf, int len);
static void
_BSP_null_char( char c )
{
{
int level;
if (c == '\n')
@@ -155,7 +155,7 @@ IntUartSet(int minor, int baud, int databits, int parity, int stopbits, int hwfl
Description : This provides the hardware-dependent portion of tcsetattr().
value and sets it. At the moment this just sets the baud rate.
Note: The highest baudrate is 115200 as this stays within
Note: The highest baudrate is 115200 as this stays within
an error of +/- 5% at 25MHz processor clock
***************************************************************************/
static int
@@ -385,9 +385,9 @@ IntUartInitialize(void)
/***************************************************************************
Function : IntUartInterruptWrite
Description : This writes a single character to the appropriate uart
Description : This writes a single character to the appropriate uart
channel. This is either called during an interrupt or in the user's task
to initiate a transmit sequence. Calling this routine enables Tx
to initiate a transmit sequence. Calling this routine enables Tx
interrupts.
***************************************************************************/
static int
@@ -494,7 +494,7 @@ IntUartTaskRead(int minor)
/* copy data into local buffer from rx buffer */
while ( ( index < count ) && ( index < RX_BUFFER_SIZE ) )
{
/* copy data byte */
/* copy data byte */
buffer[index] = info->rx_buffer[info->rx_out];
index++;
@@ -521,7 +521,7 @@ IntUartTaskRead(int minor)
/***************************************************************************
Function : IntUartPollRead
Description : This reads a character from the internal uart. It returns
Description : This reads a character from the internal uart. It returns
to the caller without blocking if not character is waiting.
***************************************************************************/
static int
@@ -537,8 +537,8 @@ IntUartPollRead (int minor)
/***************************************************************************
Function : IntUartPollWrite
Description : This writes out each character in the buffer to the
appropriate internal uart channel waiting till each one is sucessfully
Description : This writes out each character in the buffer to the
appropriate internal uart channel waiting till each one is sucessfully
transmitted.
***************************************************************************/
static int
@@ -575,7 +575,7 @@ rtems_device_driver console_initialize(
/* set io modes for the different channels and initialize device */
IntUartInfo[minor].iomode = TERMIOS_IRQ_DRIVEN;
IntUartInitialize();
IntUartInitialize();
/* Register the console port */
status = rtems_io_register_name ("/dev/console", major, CONSOLE_PORT);
@@ -608,7 +608,7 @@ rtems_device_driver console_initialize(
/***************************************************************************
Function : console_open
Description : This actually opens the device depending on the minor
Description : This actually opens the device depending on the minor
number set during initialisation. The device specific access routines are
passed to termios when the devices is opened depending on whether it is
polled or not.

2
c/src/lib/libbsp/m68k/mcf5235/include/bsp.h
View File

@@ -1,7 +1,7 @@
/*
* mcf5235 BSP header file
*/
#ifndef _BSP_H
#define _BSP_H

28
c/src/lib/libbsp/m68k/mcf5235/network/network.c
View File

@@ -107,7 +107,7 @@ static rtems_isr
mcf5235_fec_rx_interrupt_handler( rtems_vector_number v )
{
MCF5235_FEC_EIR = MCF5235_FEC_EIR_RXF;
MCF5235_FEC_EIMR &= ~MCF5235_FEC_EIMR_RXF;
MCF5235_FEC_EIMR &= ~MCF5235_FEC_EIMR_RXF;
enet_driver[0].rxInterrupts++;
rtems_event_send(enet_driver[0].rxDaemonTid, RX_INTERRUPT_EVENT);
}
@@ -116,7 +116,7 @@ static rtems_isr
mcf5235_fec_tx_interrupt_handler( rtems_vector_number v )
{
MCF5235_FEC_EIR = MCF5235_FEC_EIR_TXF;
MCF5235_FEC_EIMR &= ~MCF5235_FEC_EIMR_TXF;
MCF5235_FEC_EIMR &= ~MCF5235_FEC_EIMR_TXF;
enet_driver[0].txInterrupts++;
rtems_event_send(enet_driver[0].txDaemonTid, TX_INTERRUPT_EVENT);
}
@@ -240,7 +240,7 @@ mcf5235_fec_initialize_hardware(struct mcf5235_enet_struct *sc)
* Full duplex
* No loopback
*/
MCF5235_FEC_RCR = MCF5235_FEC_RCR_MAX_FL(MAX_MTU_SIZE) |
MCF5235_FEC_RCR = MCF5235_FEC_RCR_MAX_FL(MAX_MTU_SIZE) |
MCF5235_FEC_RCR_MII_MODE;
/*
@@ -321,13 +321,13 @@ fec_get_mac_address(volatile struct mcf5235_enet_struct *sc, unsigned char* hwad
hwaddr[1] = (addr >> 16) & 0xff;
hwaddr[2] = (addr >> 8) & 0xff;
hwaddr[3] = (addr >> 0) & 0xff;
addr = MCF5235_FEC_PAUR;
hwaddr[4] = (addr >> 24) & 0xff;
hwaddr[5] = (addr >> 16) & 0xff;
}
/*
* Soak up buffer descriptors that have been sent.
@@ -485,9 +485,9 @@ fec_sendpacket(struct ifnet *ifp, struct mbuf *m)
*/
nAdded = 0;
firstTxBd = sc->txBdBase + sc->txBdHead;
for (;;) {
/*
/*
* Wait for buffer descriptor to become available
*/
if ((sc->txBdActiveCount + nAdded) == sc->txBdCount) {
@@ -508,7 +508,7 @@ fec_sendpacket(struct ifnet *ifp, struct mbuf *m)
int level;
rtems_interrupt_disable(level);
MCF5235_FEC_EIMR |= MCF5235_FEC_EIMR_TXF;
MCF5235_FEC_EIMR |= MCF5235_FEC_EIMR_TXF;
rtems_interrupt_enable(level);
sc->txRawWait++;
rtems_bsdnet_event_receive(TX_INTERRUPT_EVENT,
@@ -518,13 +518,13 @@ fec_sendpacket(struct ifnet *ifp, struct mbuf *m)
fec_retire_tx_bd(sc);
}
}
/*
* Don't set the READY flag on the first fragment
* until the whole packet has been readied.
*/
status = nAdded ? MCF5235_FEC_TxBD_R : 0;
/*
* The IP fragmentation routine in ip_output
* can produce fragments with zero length.
@@ -595,9 +595,9 @@ fec_txDaemon(void *arg)
/*
* Wait for packet
*/
rtems_bsdnet_event_receive(START_TRANSMIT_EVENT,
RTEMS_EVENT_ANY | RTEMS_WAIT,
RTEMS_NO_TIMEOUT,
rtems_bsdnet_event_receive(START_TRANSMIT_EVENT,
RTEMS_EVENT_ANY | RTEMS_WAIT,
RTEMS_NO_TIMEOUT,
&events);
/*

22
c/src/lib/libbsp/m68k/mcf5235/start/start.S
View File

@@ -24,10 +24,10 @@
BEGIN_CODE
#define INITIAL_STACK __SRAMBASE+SRAM_SIZE-4
PUBLIC (INTERRUPT_VECTOR)
SYM(INTERRUPT_VECTOR):
.long INITIAL_STACK | 0: Initial 'SSP'
.long INITIAL_STACK | 0: Initial 'SSP'
.long start | 1: Initial PC
.long SYM(_uhoh) | 2: Bus error
.long SYM(_uhoh) | 3: Address error
@@ -290,9 +290,9 @@ SYM(INTERRUPT_VECTOR):
*/
.align 4
PUBLIC (_uhoh)
SYM(_uhoh):
SYM(_uhoh):
nop | Leave spot for breakpoint
stop #0x2700 | Stop with interrupts disabled
stop #0x2700 | Stop with interrupts disabled
bra.w SYM(_uhoh) | Stuck forever
.align 4
@@ -318,12 +318,12 @@ SYM(start):
move.l #__SRAMBASE+1,d0 | Enable the MCF5235 internal SRAM
movec d0,%rambar | ...so we have a stack
move.l #0x20000201, d0
move.l #0x20000201, d0
move.l d0,(0x40000008) | set up 2nd RAMBAR to make 2nd port avail to FEC
move.l #__IPSBAR+1,d0 | Enable the MCF5235 internal peripherals
move.l d0,DEFAULT_IPSBAR
/*
* Remainder of the startup code is handled by C code
*/
@@ -332,7 +332,7 @@ SYM(start):
/***************************************************************************
Function : CopyDataClearBSSAndStart
Description : Copy DATA segment, Copy SRAM segment, clear BSS segment,
Description : Copy DATA segment, Copy SRAM segment, clear BSS segment,
start C program. Assume that DATA and BSS sizes are multiples of 4.
***************************************************************************/
.align 4
@@ -340,7 +340,7 @@ SYM(start):
PUBLIC (CopyDataClearBSSAndStart)
SYM(CopyDataClearBSSAndStart):
lea SYM(_data_dest_start),a0 | Get start of DATA in RAM
lea SYM(_data_src_start),a2 | Get start of DATA in ROM
lea SYM(_data_src_start),a2 | Get start of DATA in ROM
cmpl a0,a2 | Are they the same?
beq.s NODATACOPY | Yes, no copy necessary
lea SYM(_data_dest_end),a1 | Get end of DATA in RAM
@@ -351,7 +351,7 @@ DATACOPYLOOPTEST:
cmpl a1,a0 | Done?
bcs.s DATACOPYLOOP | No, skip
NODATACOPY:
/* Now, clear BSS */
lea _clear_start,a0 | Get start of BSS
lea _clear_end,a1 | Get end of BSS
@@ -375,8 +375,8 @@ MULTI_TASK_EXIT:
nop
nop
trap #14
bra MULTI_TASK_EXIT
bra MULTI_TASK_EXIT
END_CODE
.align 2

4
c/src/lib/libbsp/m68k/mcf5235/startup/bspgetcpuclockspeed.c
View File

@@ -6,12 +6,12 @@
* found in the file LICENSE in this distribution or at
*
* http://www.rtems.com/license/LICENSE.
*
*
* $Id$
*/
#include <bsp.h>
extern char _CPUClockSpeed[];
uint32_t get_CPU_clock_speed(void)

4
c/src/lib/libbsp/m68k/mcf5235/startup/bspstart.c
View File

@@ -6,12 +6,12 @@
* found in the file LICENSE in this distribution or at
*
* http://www.rtems.com/license/LICENSE.
*
*
* $Id$
*/
#include <bsp.h>
/*
* Read/write copy of common cache
* Split I/D cache

20
c/src/lib/libbsp/m68k/mcf5235/startup/init5235.c
View File

@@ -2,7 +2,7 @@
* This is where the real hardware setup is done. A minimal stack
* has been provided by the start.S code. No normal C or RTEMS
* functions can be called from here.
*
*
* This routine is pretty simple for the uC5235 because all the hard
* work has been done by the bootstrap dBUG code.
*/
@@ -21,8 +21,8 @@
* if it is set to 1 then we want to boot our own code from flash and we
* do need to initialize the SDRAM.
*/
extern uint32_t MCF5235_BSP_START_FROM_FLASH;
void Init5235 (void)
@@ -31,16 +31,16 @@ void Init5235 (void)
int x;
volatile int temp = 0;
int *address_of_MCF5235_BSP_START_FROM_FLASH;
/*Setup the GPIO Registers */
MCF5235_GPIO_UART=0x3FFF;
MCF5235_GPIO_PAR_AD=0xE1;
/*Setup the Chip Selects so CS0 is flash */
MCF5235_CS_CSAR0 =(0xFFE00000 & 0xffff0000)>>16;
MCF5235_CS_CSMR0 = 0x001f0001;
MCF5235_CS_CSCR0 = 0x1980;
address_of_MCF5235_BSP_START_FROM_FLASH = (int *) & MCF5235_BSP_START_FROM_FLASH;
if ( (int)address_of_MCF5235_BSP_START_FROM_FLASH == 1) {
/*Setup the SDRAM */
@@ -56,11 +56,11 @@ void Init5235 (void)
temp +=1;
}
/* set ip ( bit 3 ) in dacr */
MCF5235_SDRAMC_DACR0 |= (0x00000008) ;
MCF5235_SDRAMC_DACR0 |= (0x00000008) ;
/* init precharge */
*((unsigned long *)MM_SDRAM_BASE) = 0xDEADBEEF;
/* set RE in dacr */
MCF5235_SDRAMC_DACR0 |= (0x00008000);
MCF5235_SDRAMC_DACR0 |= (0x00008000);
/* wait */
for(x=0; x<20000; x++)
{
@@ -70,12 +70,12 @@ void Init5235 (void)
MCF5235_SDRAMC_DACR0 |= (0x00000040);
*((short *)MM_SDRAM_BASE) = 0;
for(x=0; x<60000; x++)
{
{
temp +=1;
}
*((unsigned long*)MM_SDRAM_BASE)=0x12345678;
} /* we have finished setting up the sdram */
/* Copy the interrupt vector table to address 0x0 in SDRAM */
{
extern void INTERRUPT_VECTOR(void);

2
c/src/lib/libbsp/m68k/mcf5329/clock/clock.c
View File

@@ -81,7 +81,7 @@ static void Clock_driver_support_initialize_hardware(void)
s_nanoScale = 1000000000 / (clk >> preScaleCode);
MCF_INTC1_ICR46 = MCF_INTC_ICR_IL(PIT3_IRQ_LEVEL);
rtems_interrupt_disable(level);
MCF_INTC1_IMRH &= ~MCF_INTC_IMRH_INT_MASK46;
MCF_PIT3_PCSR &= ~MCF_PIT_PCSR_EN;

14
c/src/lib/libbsp/m68k/mcf5329/console/console.c
View File

@@ -152,7 +152,7 @@ IntUartSet(int minor, int baud, int databits, int parity, int stopbits,
Description : This provides the hardware-dependent portion of tcsetattr().
value and sets it. At the moment this just sets the baud rate.
Note: The highest baudrate is 115200 as this stays within
Note: The highest baudrate is 115200 as this stays within
an error of +/- 5% at 25MHz processor clock
***************************************************************************/
static int IntUartSetAttributes(int minor, const struct termios *t)
@@ -348,9 +348,9 @@ static void IntUartInitialize(void)
/***************************************************************************
Function : IntUartInterruptWrite
Description : This writes a single character to the appropriate uart
Description : This writes a single character to the appropriate uart
channel. This is either called during an interrupt or in the user's task
to initiate a transmit sequence. Calling this routine enables Tx
to initiate a transmit sequence. Calling this routine enables Tx
interrupts.
***************************************************************************/
static int IntUartInterruptWrite(int minor, const char *buf, int len)
@@ -468,7 +468,7 @@ static int IntUartTaskRead(int minor)
/***************************************************************************
Function : IntUartPollRead
Description : This reads a character from the internal uart. It returns
Description : This reads a character from the internal uart. It returns
to the caller without blocking if not character is waiting.
***************************************************************************/
static int IntUartPollRead(int minor)
@@ -482,8 +482,8 @@ static int IntUartPollRead(int minor)
/***************************************************************************
Function : IntUartPollWrite
Description : This writes out each character in the buffer to the
appropriate internal uart channel waiting till each one is sucessfully
Description : This writes out each character in the buffer to the
appropriate internal uart channel waiting till each one is sucessfully
transmitted.
***************************************************************************/
static int IntUartPollWrite(int minor, const char *buf, int len)
@@ -544,7 +544,7 @@ rtems_device_driver console_initialize(rtems_device_major_number major,
/***************************************************************************
Function : console_open
Description : This actually opens the device depending on the minor
Description : This actually opens the device depending on the minor
number set during initialisation. The device specific access routines are
passed to termios when the devices is opened depending on whether it is
polled or not.

6
c/src/lib/libbsp/m68k/mcf5329/include/bsp.h
View File

@@ -1,7 +1,7 @@
/*
* mcf52235 BSP header file
*/
#ifndef _BSP_H
#define _BSP_H
@@ -23,8 +23,8 @@ extern "C" {
typedef volatile unsigned char vuint8;
typedef volatile unsigned short vuint16;
typedef volatile unsigned long vuint32;
typedef volatile unsigned long vuint32;
/***************************************************************************/
/** Network driver configuration **/
struct rtems_bsdnet_ifconfig;

6
c/src/lib/libbsp/m68k/mcf5329/network/network.c
View File

@@ -473,7 +473,7 @@ static void fec_sendpacket(struct ifnet *ifp, struct mbuf *m)
firstTxBd = sc->txBdBase + sc->txBdHead;
for (;;) {
/*
/*
* Wait for buffer descriptor to become available
*/
if ((sc->txBdActiveCount + nAdded) == sc->txBdCount) {
@@ -539,9 +539,9 @@ static void fec_sendpacket(struct ifnet *ifp, struct mbuf *m)
txBd->buffer = p;
txBd->length = m->m_len;
rtems_cache_flush_multiple_data_lines(txBd->buffer, txBd->length);
sc->txMbuf[sc->txBdHead] = m;
nAdded++;
if (++sc->txBdHead == sc->txBdCount) {

20
c/src/lib/libbsp/m68k/mcf5329/start/start.S
View File

@@ -22,7 +22,7 @@
.extern _StackInit
BEGIN_CODE
PUBLIC (_INTERRUPT_VECTOR)
SYM(_INTERRUPT_VECTOR):
@@ -298,12 +298,12 @@ SYM(_INTERRUPT_VECTOR):
*/
.align 4
PUBLIC (_uhoh)
SYM(_uhoh):
SYM(_uhoh):
nop | Leave spot for breakpoint
stop #0x2700 | Stop with interrupts disabled
stop #0x2700 | Stop with interrupts disabled
bra.w SYM(_uhoh) | Stuck forever
/*
/*
* Spurious Interrupt Handler
*/
.align 4
@@ -312,18 +312,18 @@ SYM(_spuriousInterrupt):
addql #1, SYM(_M68kSpuriousInterruptCount)
rte
/*
/*
* Write VBR Register
*/
.align 4
PUBLIC (_wr_vbr)
SYM(_wr_vbr):
move.l 4(sp), d0
movec d0, vbr
movec d0, vbr
nop
rts
rts
/*
/*
* Board startup
* Disable watchdog, interrupts
* Enable sram
@@ -344,11 +344,11 @@ SYM(start):
add.l #0x221,d0
movec d0,%rambar
/* Save off intial D0 and D1 to RAM */
/* Save off intial D0 and D1 to RAM */
move.l d6, SYM(_d0_reset)
move.l d7, SYM(_d1_reset)
/* Locate Stack Pointer */
/* Locate Stack Pointer */
move.l #_StackInit,sp
/*

2
c/src/lib/libbsp/m68k/mcf5329/startup/bspstart.c
View File

@@ -16,7 +16,7 @@
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*
*
* $Id$
*/

274
c/src/lib/libbsp/m68k/mcf5329/startup/cfinit.c
View File

@@ -2,22 +2,22 @@
/*********************************************************************
* Initialisation Code for ColdFire MCF5329 Processor *
**********************************************************************
Generated by ColdFire Initialisation Utility 2.10.8
Wed Jul 02 14:26:25 2008
MicroAPL Ltd makes no warranties in respect of the suitability
of this code for any particular purpose, and accepts
no liability for any loss arising out of its use. The person or
persons making use of this file must make the final evaluation
as to its suitability and correctness for a particular application.
Generated by ColdFire Initialisation Utility 2.10.8
Wed Jul 02 14:26:25 2008
MicroAPL Ltd makes no warranties in respect of the suitability
of this code for any particular purpose, and accepts
no liability for any loss arising out of its use. The person or
persons making use of this file must make the final evaluation
as to its suitability and correctness for a particular application.
$Id$
*/
/* External reference frequency is 16.0000 MHz
Internal bus clock frequency = 80.00 MHz
Processor core frequency = 240.00 MHz
/* External reference frequency is 16.0000 MHz
Internal bus clock frequency = 80.00 MHz
Processor core frequency = 240.00 MHz
*/
#include <bsp.h>
@@ -49,7 +49,7 @@ static void init_real_time_clock(void);
static void init_watchdog_timers(void);
static void init_edma(void);
static void init_pin_assignments(void);
extern void init_sdram_controller(void)
extern void init_sdram_controller(void)
__attribute__ ((section(".ram_code")));
static void init_interrupt_controller(void);
@@ -127,22 +127,22 @@ static void disable_cache(void)
**********************************************************************/
void init_clock_config(void)
{
/* Clock module uses normal PLL mode with 16.0000 MHz external reference
Bus clock frequency = 80.00 MHz
Processor clock frequency = 3 x bus clock = 240.00 MHz
Dithering disabled
/* Clock module uses normal PLL mode with 16.0000 MHz external reference
Bus clock frequency = 80.00 MHz
Processor clock frequency = 3 x bus clock = 240.00 MHz
Dithering disabled
*/
/* Check to see if the SDRAM has already been initialized
by a run control tool. If it has, put SDRAM into self-refresh mode before
initializing the PLL
/* Check to see if the SDRAM has already been initialized
by a run control tool. If it has, put SDRAM into self-refresh mode before
initializing the PLL
*/
if (MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF)
MCF_SDRAMC_SDCR &= ~MCF_SDRAMC_SDCR_CKE;
/* Temporarily switch to LIMP mode
NOTE: Ensure that this code is not executing from SDRAM, since the
SDRAM Controller is disabled in LIMP mode
/* Temporarily switch to LIMP mode
NOTE: Ensure that this code is not executing from SDRAM, since the
SDRAM Controller is disabled in LIMP mode
*/
MCF_CCM_CDR = (MCF_CCM_CDR & 0xf0ff) | MCF_CCM_CDR_LPDIV(0x2);
MCF_CCM_MISCCR |= MCF_CCM_MISCCR_LIMP;
@@ -157,11 +157,11 @@ void init_clock_config(void)
MCF_CCM_MISCCR &= ~MCF_CCM_MISCCR_LIMP;
while ((MCF_CCM_MISCCR & MCF_CCM_MISCCR_PLL_LOCK) == 0) ;
/* From the Device Errata:
/* From the Device Errata:
"After exiting LIMP mode, the value of 0x40000000 should be written
to address 0xFC0B8080 before attempting to initialize the SDRAMC
or exit the SDRAM from self-refresh mode."
"After exiting LIMP mode, the value of 0x40000000 should be written
to address 0xFC0B8080 before attempting to initialize the SDRAMC
or exit the SDRAM from self-refresh mode."
*/
*(vuint32 *) 0xfc0b8080 = 0x40000000;
@@ -175,8 +175,8 @@ void init_clock_config(void)
**********************************************************************/
static void init_cache(void)
{
/* ACR0: Cache accesses to 32 MB memory region at address $40000000
CACR: Don't cache accesses to the rest of memory
/* ACR0: Cache accesses to 32 MB memory region at address $40000000
CACR: Don't cache accesses to the rest of memory
*/
/*
* Cache is enabled in bspstart.c
@@ -184,7 +184,7 @@ static void init_cache(void)
#if 0
asm("move.l #0xa0000600,%d0");
asm("movec %d0,%CACR");
#endif
#endif
asm("move.l #0x4001c020,%d0");
asm("movec %d0,%ACR0");
asm("move.l #0x00000000,%d0");
@@ -196,32 +196,32 @@ static void init_cache(void)
**********************************************************************/
static void init_crossbar(void)
{
/* XBS settings for FlexBus/SDRAM Controller slave:
Fixed priority (Core, LCD, eDMA, FEC, USB Host, USB OTG), park on ColdFire Core
/* XBS settings for FlexBus/SDRAM Controller slave:
Fixed priority (Core, LCD, eDMA, FEC, USB Host, USB OTG), park on ColdFire Core
*/
MCF_XBS_PRS1 = MCF_XBS_PRS_M6(0x5) |
MCF_XBS_PRS_M5(0x4) |
MCF_XBS_PRS_M4(0x1) | MCF_XBS_PRS_M2(0x3) | MCF_XBS_PRS_M1(0x2);
MCF_XBS_CRS1 = 0;
/* XBS settings for SRAM Backdoor slave:
Fixed priority (Core, eDMA, FEC, LCD, USB Host, USB OTG), park on ColdFire Core
/* XBS settings for SRAM Backdoor slave:
Fixed priority (Core, eDMA, FEC, LCD, USB Host, USB OTG), park on ColdFire Core
*/
MCF_XBS_PRS4 = MCF_XBS_PRS_M6(0x5) |
MCF_XBS_PRS_M5(0x4) |
MCF_XBS_PRS_M4(0x3) | MCF_XBS_PRS_M2(0x2) | MCF_XBS_PRS_M1(0x1);
MCF_XBS_CRS4 = 0;
/* XBS settings for Cryptography Modules slave:
Fixed priority (Core, eDMA, FEC, LCD, USB Host, USB OTG), park on ColdFire Core
/* XBS settings for Cryptography Modules slave:
Fixed priority (Core, eDMA, FEC, LCD, USB Host, USB OTG), park on ColdFire Core
*/
MCF_XBS_PRS6 = MCF_XBS_PRS_M6(0x5) |
MCF_XBS_PRS_M5(0x4) |
MCF_XBS_PRS_M4(0x3) | MCF_XBS_PRS_M2(0x2) | MCF_XBS_PRS_M1(0x1);
MCF_XBS_CRS6 = 0;
/* XBS settings for On-chip Peripherals slave:
Fixed priority (Core, eDMA, FEC, LCD, USB Host, USB OTG), park on ColdFire Core
/* XBS settings for On-chip Peripherals slave:
Fixed priority (Core, eDMA, FEC, LCD, USB Host, USB OTG), park on ColdFire Core
*/
MCF_XBS_PRS7 = MCF_XBS_PRS_M6(0x5) |
MCF_XBS_PRS_M5(0x4) |
@@ -249,11 +249,11 @@ void init_chip_selects(void)
/* Chip Select 5 disabled (CSMR5[V] = 0) */
MCF_FBCS5_CSMR = 0;
/* Chip Select 0: 2 MB of Flash at base address $00000000
Port size = 16 bits
Assert chip select on first rising clock edge after address is asserted
Generate internal transfer acknowledge after 7 wait states
Address is held for 1 clock at end of read and write cycles
/* Chip Select 0: 2 MB of Flash at base address $00000000
Port size = 16 bits
Assert chip select on first rising clock edge after address is asserted
Generate internal transfer acknowledge after 7 wait states
Address is held for 1 clock at end of read and write cycles
*/
MCF_FBCS0_CSAR = 0;
MCF_FBCS0_CSCR = MCF_FBCS_CSCR_WS(0x7) |
@@ -293,40 +293,40 @@ static void init_flexcan(void)
**********************************************************************/
void init_sdram_controller(void)
{
/* Check to see if the SDRAM has already been initialized
by a run control tool and skip if so
/* Check to see if the SDRAM has already been initialized
by a run control tool and skip if so
*/
if (MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF)
return;
/* Ensure that there is a delay from processor reset of the time recommended in
the SDRAM data sheet (typically 100-200 microseconds) until the following
code so that the SDRAM is ready for commands...
/* Ensure that there is a delay from processor reset of the time recommended in
the SDRAM data sheet (typically 100-200 microseconds) until the following
code so that the SDRAM is ready for commands...
*/
/* SDRAM controller configured for Double-data rate (DDR) SDRAM
Bus width = 16 bits
SDRAM specification:
SDRAM clock frequency = 80.00 MHz
CASL = 2.5
ACTV-to-read/write delay, tRCD = 20.0 nanoseconds
Write recovery time, tWR = 15.0 nanoseconds
Precharge comand to ACTV command, tRP = 20.0 nanoseconds
Auto refresh command period, tRFC = 75.0 nanoseconds
Average periodic refresh interval, tREFI = 7.8 microseconds
/* SDRAM controller configured for Double-data rate (DDR) SDRAM
Bus width = 16 bits
SDRAM specification:
SDRAM clock frequency = 80.00 MHz
CASL = 2.5
ACTV-to-read/write delay, tRCD = 20.0 nanoseconds
Write recovery time, tWR = 15.0 nanoseconds
Precharge comand to ACTV command, tRP = 20.0 nanoseconds
Auto refresh command period, tRFC = 75.0 nanoseconds
Average periodic refresh interval, tREFI = 7.8 microseconds
*/
/* Memory block 0 enabled - 32 MBytes at address $40000000
Block consists of 1 device x 256 MBits (13 rows x 9 columns x 4 banks)
/* Memory block 0 enabled - 32 MBytes at address $40000000
Block consists of 1 device x 256 MBits (13 rows x 9 columns x 4 banks)
*/
MCF_SDRAMC_SDCS0 = MCF_SDRAMC_SDCS_BASE(0x400) | MCF_SDRAMC_SDCS_CSSZ(0x18);
/* Memory block 1 disabled */
MCF_SDRAMC_SDCS1 = 0;
/* Initialise SDCFG1 register with delay and timing values
SRD2RWP = 4, SWT2RWP = 3, RD_LAT = 7, ACT2RW = 2
PRE2ACT = 2, REF2ACT = 6, WT_LAT = 3
/* Initialise SDCFG1 register with delay and timing values
SRD2RWP = 4, SWT2RWP = 3, RD_LAT = 7, ACT2RW = 2
PRE2ACT = 2, REF2ACT = 6, WT_LAT = 3
*/
MCF_SDRAMC_SDCFG1 = MCF_SDRAMC_SDCFG1_SRD2RW(0x4) |
MCF_SDRAMC_SDCFG1_SWT2RD(0x3) |
@@ -335,8 +335,8 @@ void init_sdram_controller(void)
MCF_SDRAMC_SDCFG1_PRE2ACT(0x2) |
MCF_SDRAMC_SDCFG1_REF2ACT(0x6) | MCF_SDRAMC_SDCFG1_WTLAT(0x3);
/* Initialise SDCFG2 register with delay and timing values
BRD2RP = 5, BWT2RWP = 6, BRD2W = 6, BL = 7
/* Initialise SDCFG2 register with delay and timing values
BRD2RP = 5, BWT2RWP = 6, BRD2W = 6, BL = 7
*/
MCF_SDRAMC_SDCFG2 = MCF_SDRAMC_SDCFG2_BRD2PRE(0x5) |
MCF_SDRAMC_SDCFG2_BWT2RW(0x6) |
@@ -361,8 +361,8 @@ void init_sdram_controller(void)
/* Issue a second Precharge All command */
MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IPALL;
/* Refresh sequence...
(check the number of refreshes required by the SDRAM manufacturer)
/* Refresh sequence...
(check the number of refreshes required by the SDRAM manufacturer)
*/
MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IREF;
MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IREF;
@@ -436,9 +436,9 @@ static void init_real_time_clock(void)
**********************************************************************/
static void init_watchdog_timers(void)
{
/* Watchdog Timer disabled (WCR[EN]=0)
NOTE: WCR and WMR cannot be written again until after the
processor is reset.
/* Watchdog Timer disabled (WCR[EN]=0)
NOTE: WCR and WMR cannot be written again until after the
processor is reset.
*/
MCF_WTM_WCR = MCF_WTM_WCR_WAIT | MCF_WTM_WCR_DOZE | MCF_WTM_WCR_HALTED;
MCF_WTM_WMR = MCF_WTM_WMR_WM(0xffff);
@@ -563,34 +563,34 @@ static void init_interrupt_controller(void)
**********************************************************************/
static void init_pin_assignments(void)
{
/* Pin assignments for port BUSCTL
Pin BUSCTL3 : External bus output enable, /OE
Pin BUSCTL2 : External bus transfer acknowledge, /TA
Pin BUSCTL1 : External bus read/write, R/W
Pin BUSCTL0 : External bus transfer start, /TS
/* Pin assignments for port BUSCTL
Pin BUSCTL3 : External bus output enable, /OE
Pin BUSCTL2 : External bus transfer acknowledge, /TA
Pin BUSCTL1 : External bus read/write, R/W
Pin BUSCTL0 : External bus transfer start, /TS
*/
MCF_GPIO_PDDR_BUSCTL = 0;
MCF_GPIO_PAR_BUSCTL = MCF_GPIO_PAR_BUSCTL_PAR_OE |
MCF_GPIO_PAR_BUSCTL_PAR_TA |
MCF_GPIO_PAR_BUSCTL_PAR_RWB | MCF_GPIO_PAR_BUSCTL_PAR_TS(0x3);
/* Pin assignments for port BE
Pin BE3 : External bus byte enable BW/BWE3
Pin BE2 : External bus byte enable BW/BWE2
Pin BE1 : External bus byte enable BW/BWE1
Pin BE0 : External bus byte enable BW/BWE0
/* Pin assignments for port BE
Pin BE3 : External bus byte enable BW/BWE3
Pin BE2 : External bus byte enable BW/BWE2
Pin BE1 : External bus byte enable BW/BWE1
Pin BE0 : External bus byte enable BW/BWE0
*/
MCF_GPIO_PDDR_BE = 0;
MCF_GPIO_PAR_BE = MCF_GPIO_PAR_BE_PAR_BE3 |
MCF_GPIO_PAR_BE_PAR_BE2 |
MCF_GPIO_PAR_BE_PAR_BE1 | MCF_GPIO_PAR_BE_PAR_BE0;
/* Pin assignments for port CS
Pin CS5 : Flex bus chip select /FB_CS5
Pin CS4 : Flex bus chip select /FB_CS4
Pin CS3 : Flex bus chip select /FB_CS3
Pin CS2 : Flex bus chip select /FB_CS2
Pin CS1 : Flex bus chip select /FB_CS1
/* Pin assignments for port CS
Pin CS5 : Flex bus chip select /FB_CS5
Pin CS4 : Flex bus chip select /FB_CS4
Pin CS3 : Flex bus chip select /FB_CS3
Pin CS2 : Flex bus chip select /FB_CS2
Pin CS1 : Flex bus chip select /FB_CS1
*/
MCF_GPIO_PDDR_CS = 0;
MCF_GPIO_PAR_CS = MCF_GPIO_PAR_CS_PAR_CS5 |
@@ -598,106 +598,106 @@ static void init_pin_assignments(void)
MCF_GPIO_PAR_CS_PAR_CS3 |
MCF_GPIO_PAR_CS_PAR_CS2 | MCF_GPIO_PAR_CS_PAR_CS1;
/* Pin assignments for port FECI2C
Pin FECI2C3 : FEC management data clock, FEC_MDC
Pin FECI2C2 : FEC management data, FEC_MDIO
Pin FECI2C1 : GPIO input
Pin FECI2C0 : GPIO input
/* Pin assignments for port FECI2C
Pin FECI2C3 : FEC management data clock, FEC_MDC
Pin FECI2C2 : FEC management data, FEC_MDIO
Pin FECI2C1 : GPIO input
Pin FECI2C0 : GPIO input
*/
MCF_GPIO_PDDR_FECI2C = 0;
MCF_GPIO_PAR_FECI2C = MCF_GPIO_PAR_FECI2C_PAR_MDC(0x3) |
MCF_GPIO_PAR_FECI2C_PAR_MDIO(0x3);
/* Pin assignments for ports FECH and FECL
Pin FECH7 : FEC transmit clock, FEC_TXCLK
Pin FECH6 : FEC transmit enable, FEC_TXEN
Pin FECH5 : FEC transmit data 0, FEC_TXD0
Pin FECH4 : FEC collision, FEC_COL
Pin FECH3 : FEC receive clock, FEC_RXCLK
Pin FECH2 : FEC receive data valid, FEC_RXDV
Pin FECH1 : FEC receive data 0, FEC_RXD0
Pin FECH0 : FEC carrier receive sense, FEC_CRS
Pin FECL7 : FEC transmit data 3, FEC_TXD3
Pin FECL6 : FEC transmit data 2, FEC_TXD2
Pin FECL5 : FEC transmit data 1, FEC_TXD1
Pin FECL4 : FEC transmit error, FEC_TXER
Pin FECL3 : FEC receive data 3, FEX_RXD3
Pin FECL2 : FEC receive data 2, FEX_RXD2
Pin FECL1 : FEC receive data 1, FEX_RXD1
Pin FECL0 : FEC receive error, FEC_RXER
/* Pin assignments for ports FECH and FECL
Pin FECH7 : FEC transmit clock, FEC_TXCLK
Pin FECH6 : FEC transmit enable, FEC_TXEN
Pin FECH5 : FEC transmit data 0, FEC_TXD0
Pin FECH4 : FEC collision, FEC_COL
Pin FECH3 : FEC receive clock, FEC_RXCLK
Pin FECH2 : FEC receive data valid, FEC_RXDV
Pin FECH1 : FEC receive data 0, FEC_RXD0
Pin FECH0 : FEC carrier receive sense, FEC_CRS
Pin FECL7 : FEC transmit data 3, FEC_TXD3
Pin FECL6 : FEC transmit data 2, FEC_TXD2
Pin FECL5 : FEC transmit data 1, FEC_TXD1
Pin FECL4 : FEC transmit error, FEC_TXER
Pin FECL3 : FEC receive data 3, FEX_RXD3
Pin FECL2 : FEC receive data 2, FEX_RXD2
Pin FECL1 : FEC receive data 1, FEX_RXD1
Pin FECL0 : FEC receive error, FEC_RXER
*/
MCF_GPIO_PDDR_FECH = 0;
MCF_GPIO_PDDR_FECL = 0;
MCF_GPIO_PAR_FEC = MCF_GPIO_PAR_FEC_PAR_FEC_7W(0x3) |
MCF_GPIO_PAR_FEC_PAR_FEC_MII(0x3);
/* Pin assignments for port IRQ
Pins are all used for EdgePort GPIO/IRQ
/* Pin assignments for port IRQ
Pins are all used for EdgePort GPIO/IRQ
*/
MCF_GPIO_PAR_IRQ = 0;
/* Pin assignments for port LCDDATAH
Pins are all GPIO inputs
/* Pin assignments for port LCDDATAH
Pins are all GPIO inputs
*/
MCF_GPIO_PDDR_LCDDATAH = 0;
MCF_GPIO_PAR_LCDDATA = 0;
/* Pin assignments for port LCDDATAM
Port LCDDATAM pins are all GPIO inputs
/* Pin assignments for port LCDDATAM
Port LCDDATAM pins are all GPIO inputs
*/
MCF_GPIO_PDDR_LCDDATAM = 0;
/* Pin assignments for port LCDDATAL
Port LCDDATAL pins are all GPIO inputs
/* Pin assignments for port LCDDATAL
Port LCDDATAL pins are all GPIO inputs
*/
MCF_GPIO_PDDR_LCDDATAL = 0;
/* Pin assignments for port LCDCTLH
Pins are all GPIO inputs
/* Pin assignments for port LCDCTLH
Pins are all GPIO inputs
*/
MCF_GPIO_PDDR_LCDCTLH = 0;
MCF_GPIO_PAR_LCDCTL = 0;
/* Pin assignments for port LCDCTLL
Pins are all GPIO inputs
/* Pin assignments for port LCDCTLL
Pins are all GPIO inputs
*/
MCF_GPIO_PDDR_LCDCTLL = 0;
/* Pin assignments for port PWM
Pins are all GPIO inputs
/* Pin assignments for port PWM
Pins are all GPIO inputs
*/
MCF_GPIO_PDDR_PWM = 0;
MCF_GPIO_PAR_PWM = 0;
/* Pin assignments for port QSPI
Pins are all GPIO inputs
/* Pin assignments for port QSPI
Pins are all GPIO inputs
*/
MCF_GPIO_PDDR_QSPI = 0;
MCF_GPIO_PAR_QSPI = 0;
/* Pin assignments for port SSI
Pins are all GPIO inputs
/* Pin assignments for port SSI
Pins are all GPIO inputs
*/
MCF_GPIO_PDDR_SSI = 0;
MCF_GPIO_PAR_SSI = 0;
/* Pin assignments for port TIMER
Pins are all GPIO outputs
/* Pin assignments for port TIMER
Pins are all GPIO outputs
*/
MCF_GPIO_PDDR_TIMER = MCF_GPIO_PDDR_TIMER_PDDR_TIMER3 |
MCF_GPIO_PDDR_TIMER_PDDR_TIMER2 |
MCF_GPIO_PDDR_TIMER_PDDR_TIMER1 | MCF_GPIO_PDDR_TIMER_PDDR_TIMER0;
MCF_GPIO_PAR_TIMER = 0;
/* Pin assignments for port UART
Pin UART7 : UART 1 clear-to-send, /U1CTS
Pin UART6 : UART 1 request-to-send, /U1RTS
Pin UART5 : UART 1 transmit data, U1TXD
Pin UART4 : UART 1 receive data, U1RXD
Pin UART3 : UART 0 clear-to-send, /U0CTS
Pin UART2 : UART 0 request-to-send, /U0RTS
Pin UART1 : UART 0 transmit data, U0TXD
Pin UART0 : UART 0 receive data, U0RXD
/* Pin assignments for port UART
Pin UART7 : UART 1 clear-to-send, /U1CTS
Pin UART6 : UART 1 request-to-send, /U1RTS
Pin UART5 : UART 1 transmit data, U1TXD
Pin UART4 : UART 1 receive data, U1RXD
Pin UART3 : UART 0 clear-to-send, /U0CTS
Pin UART2 : UART 0 request-to-send, /U0RTS
Pin UART1 : UART 0 transmit data, U0TXD
Pin UART0 : UART 0 receive data, U0RXD
*/
MCF_GPIO_PDDR_UART = 0;
MCF_GPIO_PAR_UART = MCF_GPIO_PAR_UART_PAR_UCTS1(0x3) |

14
c/src/lib/libbsp/m68k/mcf5329/startup/init5329.c
View File

@@ -31,13 +31,13 @@ void Init5329(void)
register uint8_t *dbp, *sbp;
register uint32_t *dp, *sp;
/*
/*
* Initialize the hardware
*/
init_main();
/*
* Copy the vector table to RAM
/*
* Copy the vector table to RAM
*/
if (_VBR != _INTERRUPT_VECTOR) {
@@ -50,8 +50,8 @@ void Init5329(void)
_wr_vbr((uint32_t) _VBR);
/*
* Move initialized data from ROM to RAM.
/*
* Move initialized data from ROM to RAM.
*/
if (_data_src_start != _data_dest_start) {
dbp = (uint8_t *) _data_dest_start;
@@ -61,8 +61,8 @@ void Init5329(void)
*dbp++ = *sbp++;
}
/*
* Zero uninitialized data
/*
* Zero uninitialized data
*/
if (_clear_start != _clear_end) {

80
c/src/lib/libbsp/m68k/mrm332/console/sci.c
View File

@@ -36,7 +36,7 @@
* $Id$
*
*****************************************************************************/
/*****************************************************************************
Overview of serial port console terminal input/output
*****************************************************************************/
@@ -74,7 +74,7 @@
| |
+---------+
*/
/*****************************************************************************
Section A - Include Files
@@ -89,7 +89,7 @@
#include <libchip/sersupp.h>
#include "sci.h"
/*#include "../misc/include/cpu332.h" */
/*****************************************************************************
Section B - Manifest Constants
@@ -115,19 +115,19 @@
#define SYS_CLOCK (XTAL * 4.0 * (NUMB_Y+1) * (1 << (2 * NUMB_W + NUMB_X)))
#endif
/*****************************************************************************
Section C - External Data
*****************************************************************************/
/*****************************************************************************
Section D - External Functions
*****************************************************************************/
/*****************************************************************************
Section E - Local Functions
@@ -199,7 +199,7 @@ static void SciRcvBufFlush( void ); /* unused routine */
void SciUnitTest(void); /* test routine */
void SciPrintStats(void); /* test routine */
/*****************************************************************************
Section F - Local Variables
@@ -237,7 +237,7 @@ BSP_polling_getchar_function_type BSP_poll_char = NULL;
#ifdef ID_STRINGS
static const char SciIdent[]="$Id$";
#endif
/*****************************************************************************
Section G - A circular buffer for rcv chars when the driver interface is used.
@@ -259,7 +259,7 @@ static uint8_t SciRcvBufGetIndex = 0; /* array index to take out next char */
static uint16_t SciRcvBufCount = 0; /* how many bytes are in the buffer */
/*****************************************************************************
Section H - RTEMS termios callbacks for the interrupt version of the driver
@@ -292,7 +292,7 @@ static const rtems_termios_callbacks SciPolledCallbacks =
NULL, /* start remote xmit */
FALSE /* output uses interrupts */
};
/*
* SECTION 0
@@ -316,7 +316,7 @@ void SCI_output_char(char c)
return;
}
/****************************************************************************
* Func: SciGetTermiosHandlers
@@ -339,7 +339,7 @@ const rtems_termios_callbacks * SciGetTermiosHandlers( int32_t polled )
return &SciInterruptCallbacks; /* interrupt driven */
}
}
/****************************************************************************
* Func: SciIsr
@@ -399,7 +399,7 @@ rtems_isr SciIsr( rtems_vector_number vector )
*SCSR &= SCI_CLEAR_RX_INT; /* clear the interrupt */
}
}
/*
* SECTION 1
@@ -440,7 +440,7 @@ static int8_t SciRcvBufGetChar(void)
return ch; /* return the char */
}
/****************************************************************************
* Func: SciRcvBufPutChar
@@ -474,7 +474,7 @@ static void SciRcvBufPutChar( uint8_t ch )
return; /* return */
}
/****************************************************************************
* Func: SciRcvBufFlush
@@ -505,7 +505,7 @@ static void SciRcvBufFlush( void )
return; /* return */
}
#endif
/*
*
@@ -579,7 +579,7 @@ int SciInterruptOpen(
return RTEMS_SUCCESSFUL;
}
/****************************************************************************
* Func: SciInterruptClose
@@ -602,7 +602,7 @@ int SciInterruptClose(
return RTEMS_SUCCESSFUL;
}
/****************************************************************************
* Func: SciInterruptWrite
@@ -647,7 +647,7 @@ int SciInterruptWrite(
return 1; /* return success */
}
/****************************************************************************
* Func: SciSetAttributes
@@ -735,7 +735,7 @@ int SciSetAttributes(
return RTEMS_SUCCESSFUL;
}
/*
*
@@ -796,7 +796,7 @@ int SciPolledOpen(
return RTEMS_SUCCESSFUL;
}
/****************************************************************************
* Func: SciPolledClose
@@ -819,7 +819,7 @@ int SciPolledClose(
return RTEMS_SUCCESSFUL;
}
/****************************************************************************
* Func: SciPolledRead
@@ -846,7 +846,7 @@ int SciPolledRead(
return -1; /* return error */
}
/****************************************************************************
* Func: SciPolledWrite
@@ -889,7 +889,7 @@ int SciPolledWrite(
return written; /* return count */
}
/*
*
@@ -938,7 +938,7 @@ rtems_device_driver SciInitialize (
return RTEMS_SUCCESSFUL;
}
/****************************************************************************
* Func: SciOpen
@@ -981,7 +981,7 @@ rtems_device_driver SciOpen (
return RTEMS_SUCCESSFUL;
}
/****************************************************************************
* Func: SciClose
@@ -1018,7 +1018,7 @@ rtems_device_driver SciClose (
return RTEMS_SUCCESSFUL;
}
/****************************************************************************
* Func: SciRead
@@ -1078,7 +1078,7 @@ rtems_device_driver SciRead (
return RTEMS_SUCCESSFUL;
}
/****************************************************************************
* Func: SciWrite
@@ -1127,7 +1127,7 @@ rtems_device_driver SciWrite (
return RTEMS_SUCCESSFUL;
}
/****************************************************************************
* Func: SciControl
@@ -1186,7 +1186,7 @@ rtems_device_driver SciControl (
return RTEMS_SUCCESSFUL;
}
/*
*
@@ -1231,7 +1231,7 @@ static void SciSetBaud(uint32_t rate)
return;
}
/****************************************************************************
* Func: SciSetParity
@@ -1271,7 +1271,7 @@ static void SciSetParity(uint16_t parity)
return;
}
/****************************************************************************
* Func: SciSetDataBits
@@ -1306,7 +1306,7 @@ static void SciSetDataBits(uint16_t bits)
return;
}
/****************************************************************************
* Func: SciDisableAllInterrupts
@@ -1345,7 +1345,7 @@ static void inline SciDisableTransmitInterrupts( void )
{
*SCCR1 &= SCI_DISABLE_INT_TX;
}
/****************************************************************************
* Func: SciEnableTransmitter, SciDisableTransmitter
@@ -1376,7 +1376,7 @@ static void inline SciDisableReceiver( void )
{
*SCCR1 &= SCI_DISABLE_RCVR;
}
/****************************************************************************
* Func: SciWriteCharWait
@@ -1432,7 +1432,7 @@ void SciWriteCharNoWait(uint8_t c)
return;
}
/****************************************************************************
* Func: SciReadCharWait
@@ -1486,7 +1486,7 @@ uint8_t inline SciReadCharNoWait( void )
return ch; /* return the char */
}
/****************************************************************************
* Func: SciCharAvailable
@@ -1501,7 +1501,7 @@ uint8_t inline SciCharAvailable( void )
{
return ( *SCSR & SCI_RCVR_READY ); /* char in data register? */
}
/****************************************************************************
* Func: SciSendBreak
@@ -1527,7 +1527,7 @@ void SciSendBreak( void )
return;
}
/*
*
@@ -1567,7 +1567,7 @@ printk("SCI read result=%d,byte=%x\r\n",result,byte);
return;
}
#endif
/****************************************************************************
* Func: SciPrintStats

12
c/src/lib/libbsp/m68k/mrm332/console/sci.h
View File

@@ -42,7 +42,7 @@
#define SCI_IOCTL_MODE_1200 0x80 /* 1200,n,8,1 download mode */
#define SCI_IOCTL_MODE_9600 0x81 /* 9600,n,8,1 download mode */
#define SCI_IOCTL_MODE_9_BIT 0x82 /* 9600,forced,8,1 command mode */
/*******************************************************************************
SCI Registers
@@ -83,7 +83,7 @@
#define SCI_BAUD_4800 109
#define SCI_BAUD_2400 218
#define SCI_BAUD_1200 437
/* SCI Control Register 1 (SCCR1) $FFFC0A
@@ -109,7 +109,7 @@
| | +------------------------------------- 13 wired-or mode
| +--------------------------------------- 14 loop mode
+----------------------------------------- 15 unused
0 0 0 0 - 0 0 0 0 - 0 0 0 0 - 0 0 0 0 reset value
*/
@@ -149,7 +149,7 @@
#define SCI_TXD_OPEN_DRAIN 0x2000 /* 0010-0000-0000-0000 */
#define SCI_LOOPBACK_MODE 0x4000 /* 0100-0000-0000-0000 */
#define SCI_SCCR1_UNUSED 0x8000 /* 1000-0000-0000-0000 */
/* SCI Status Register (SCSR) $FFFC0C
@@ -175,7 +175,7 @@
| | +------------------------------------- 13 always zero
| +--------------------------------------- 14 always zero
+----------------------------------------- 15 always zero
0 0 0 0 - 0 0 0 1 - 1 0 0 0 - 0 0 0 0 reset value
*/
@@ -197,7 +197,7 @@
#define SCI_XMTR_AVAILABLE 0x0180 /* 0000-0001-1000-0000 */
/*******************************************************************************
Function prototypes

2
c/src/lib/libbsp/m68k/mvme167/network/network.c
View File

@@ -1850,7 +1850,7 @@ void uti596_init(
printk(("uti596_init: After attach, status of board = 0x%x\n", sc->scb.status ))
#endif
}
/*
* In case the ISR discovers there are no resources it reclaims
* them and restarts

2
c/src/lib/libbsp/m68k/ods68302/startup/m68k-stub.c
View File

@@ -167,7 +167,7 @@ enum regnames {D0,D1,D2,D3,D4,D5,D6,D7,
FPCONTROL,FPSTATUS,FPIADDR
};
/* We keep a whole frame cache here. "Why?", I hear you cry, "doesn't
GDB handle that sort of thing?" Well, yes, I believe the only
reason for this cache is to save and restore floating point state

2
c/src/lib/libbsp/m68k/shared/gdbstub/m68k-stub.c
View File

@@ -152,7 +152,7 @@ const char gdb_hexchars[]="0123456789abcdef";
#define highhex(x) gdb_hexchars [(x >> 4) & 0xf]
#define lowhex(x) gdb_hexchars [x & 0xf]
/* We keep a whole frame cache here. "Why?", I hear you cry, "doesn't
GDB handle that sort of thing?" Well, yes, I believe the only
reason for this cache is to save and restore floating point state

20
c/src/lib/libbsp/m68k/uC5282/console/console.c
View File

@@ -37,7 +37,7 @@ static int IntUartInterruptWrite (int minor, const char *buf, int len);
static void
_BSP_null_char( char c )
{
{
int level;
if (c == '\n')
@@ -169,7 +169,7 @@ IntUartSet(int minor, int baud, int databits, int parity, int stopbits, int hwfl
Description : This provides the hardware-dependent portion of tcsetattr().
value and sets it. At the moment this just sets the baud rate.
Note: The highest baudrate is 115200 as this stays within
Note: The highest baudrate is 115200 as this stays within
an error of +/- 5% at 25MHz processor clock
***************************************************************************/
static int
@@ -401,9 +401,9 @@ IntUartInitialize(void)
/***************************************************************************
Function : IntUartInterruptWrite
Description : This writes a single character to the appropriate uart
Description : This writes a single character to the appropriate uart
channel. This is either called during an interrupt or in the user's task
to initiate a transmit sequence. Calling this routine enables Tx
to initiate a transmit sequence. Calling this routine enables Tx
interrupts.
***************************************************************************/
static int
@@ -529,7 +529,7 @@ IntUartTaskRead(int minor)
/* copy data into local buffer from rx buffer */
while ( ( index < count ) && ( index < RX_BUFFER_SIZE ) )
{
/* copy data byte */
/* copy data byte */
buffer[index] = info->rx_buffer[info->rx_out];
index++;
@@ -556,7 +556,7 @@ IntUartTaskRead(int minor)
/***************************************************************************
Function : IntUartPollRead
Description : This reads a character from the internal uart. It returns
Description : This reads a character from the internal uart. It returns
to the caller without blocking if not character is waiting.
***************************************************************************/
static int
@@ -572,8 +572,8 @@ IntUartPollRead (int minor)
/***************************************************************************
Function : IntUartPollWrite
Description : This writes out each character in the buffer to the
appropriate internal uart channel waiting till each one is sucessfully
Description : This writes out each character in the buffer to the
appropriate internal uart channel waiting till each one is sucessfully
transmitted.
***************************************************************************/
static int
@@ -611,7 +611,7 @@ rtems_device_driver console_initialize(
/* set io modes for the different channels and initialize device */
for ( chan = 0; chan < MAX_UART_INFO; chan++ )
IntUartInfo[chan].iomode = TERMIOS_IRQ_DRIVEN;
IntUartInitialize();
IntUartInitialize();
/* Register the console port */
status = rtems_io_register_name ("/dev/console", major, CONSOLE_PORT);
@@ -649,7 +649,7 @@ rtems_device_driver console_initialize(
/***************************************************************************
Function : console_open
Description : This actually opens the device depending on the minor
Description : This actually opens the device depending on the minor
number set during initialisation. The device specific access routines are
passed to termios when the devices is opened depending on whether it is
polled or not.

2
c/src/lib/libbsp/m68k/uC5282/include/bsp.h
View File

@@ -10,7 +10,7 @@
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*/
#ifndef _BSP_H
#define _BSP_H

24
c/src/lib/libbsp/m68k/uC5282/network/network.c
View File

@@ -162,7 +162,7 @@ static rtems_isr
mcf5282_fec_rx_interrupt_handler( rtems_vector_number v )
{
MCF5282_FEC_EIR = MCF5282_FEC_EIR_RXF;
MCF5282_FEC_EIMR &= ~MCF5282_FEC_EIMR_RXF;
MCF5282_FEC_EIMR &= ~MCF5282_FEC_EIMR_RXF;
enet_driver[0].rxInterrupts++;
rtems_event_send(enet_driver[0].rxDaemonTid, RX_INTERRUPT_EVENT);
}
@@ -171,7 +171,7 @@ static rtems_isr
mcf5282_fec_tx_interrupt_handler( rtems_vector_number v )
{
MCF5282_FEC_EIR = MCF5282_FEC_EIR_TXF;
MCF5282_FEC_EIMR &= ~MCF5282_FEC_EIMR_TXF;
MCF5282_FEC_EIMR &= ~MCF5282_FEC_EIMR_TXF;
enet_driver[0].txInterrupts++;
rtems_event_send(enet_driver[0].txDaemonTid, TX_INTERRUPT_EVENT);
}
@@ -276,7 +276,7 @@ mcf5282_fec_initialize_hardware(struct mcf5282_enet_struct *sc)
* Full duplex
* No loopback
*/
MCF5282_FEC_RCR = MCF5282_FEC_RCR_MAX_FL(MAX_MTU_SIZE) |
MCF5282_FEC_RCR = MCF5282_FEC_RCR_MAX_FL(MAX_MTU_SIZE) |
MCF5282_FEC_RCR_MII_MODE;
/*
@@ -547,9 +547,9 @@ fec_sendpacket(struct ifnet *ifp, struct mbuf *m)
*/
nAdded = 0;
firstTxBd = sc->txBdBase + sc->txBdHead;
while (m != NULL) {
/*
/*
* Wait for buffer descriptor to become available
*/
if ((sc->txBdActiveCount + nAdded) == sc->txBdCount) {
@@ -570,7 +570,7 @@ fec_sendpacket(struct ifnet *ifp, struct mbuf *m)
int level;
rtems_interrupt_disable(level);
MCF5282_FEC_EIMR |= MCF5282_FEC_EIMR_TXF;
MCF5282_FEC_EIMR |= MCF5282_FEC_EIMR_TXF;
rtems_interrupt_enable(level);
sc->txRawWait++;
rtems_bsdnet_event_receive(TX_INTERRUPT_EVENT,
@@ -580,13 +580,13 @@ fec_sendpacket(struct ifnet *ifp, struct mbuf *m)
fec_retire_tx_bd(sc);
}
}
/*
* Don't set the READY flag on the first fragment
* until the whole packet has been readied.
*/
status = nAdded ? MCF5282_FEC_TxBD_R : 0;
/*
* The IP fragmentation routine in ip_output
* can produce fragments with zero length.
@@ -665,9 +665,9 @@ fec_txDaemon(void *arg)
/*
* Wait for packet
*/
rtems_bsdnet_event_receive(START_TRANSMIT_EVENT,
RTEMS_EVENT_ANY | RTEMS_WAIT,
RTEMS_NO_TIMEOUT,
rtems_bsdnet_event_receive(START_TRANSMIT_EVENT,
RTEMS_EVENT_ANY | RTEMS_WAIT,
RTEMS_NO_TIMEOUT,
&events);
/*
@@ -836,7 +836,7 @@ enet_stats(struct mcf5282_enet_struct *sc)
printf("Link %s %d Mb/s, %s-duplex.\n",
fixed ? "fixed" : "auto-negotiate",
speed,
full ? "full" : "half");
full ? "full" : "half");
}
printf(" EIR:%8.8lx ", MCF5282_FEC_EIR);
printf("EIMR:%8.8lx ", MCF5282_FEC_EIMR);

16
c/src/lib/libbsp/m68k/uC5282/start/start.S
View File

@@ -298,9 +298,9 @@ Entry:
*/
.align 4
PUBLIC (_uhoh)
SYM(_uhoh):
SYM(_uhoh):
nop | Leave spot for breakpoint
stop #0x2700 | Stop with interrupts disabled
stop #0x2700 | Stop with interrupts disabled
bra.w SYM(_uhoh) | Stuck forever
.align 4
@@ -336,16 +336,16 @@ vectcpy:
move.l a0@+,a1@+ | Copy the vector table
sub.l #1,d0
bne.s vectcpy
/*
* Remainder of the startup code is handled by C code
*/
jmp SYM(Init5282) | Start C code (which never returns)
/***************************************************************************
Function : CopyDataClearBSSAndStart
Description : Copy DATA segment, Copy SRAM segment, clear BSS segment,
Description : Copy DATA segment, Copy SRAM segment, clear BSS segment,
start C program. Assume that DATA and BSS sizes are multiples of 4.
***************************************************************************/
.align 4
@@ -354,7 +354,7 @@ vectcpy:
SYM(CopyDataClearBSSAndStart):
lea SYM(_data_dest_start),a0 | Get start of DATA in RAM
lea SYM(_data_src_start),a2 | Get start of DATA in ROM
sub.l #SYM(_header_offset),a2 | Change source by the amount of the header offset
sub.l #SYM(_header_offset),a2 | Change source by the amount of the header offset
cmpl a0,a2 | Are they the same?
beq.s NODATACOPY | Yes, no copy necessary
lea SYM(_data_dest_end),a1 | Get end of DATA in RAM
@@ -365,7 +365,7 @@ DATACOPYLOOPTEST:
cmpl a1,a0 | Done?
bcs.s DATACOPYLOOP | No, skip
NODATACOPY:
/* Now, clear BSS */
lea _clear_start,a0 | Get start of BSS
lea _clear_end,a1 | Get end of BSS
@@ -389,7 +389,7 @@ MULTI_TASK_EXIT:
nop
nop
trap #14
bra MULTI_TASK_EXIT
bra MULTI_TASK_EXIT
END_CODE

36
c/src/lib/libbsp/m68k/uC5282/startup/bspstart.c
View File

@@ -14,14 +14,14 @@
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.com/license/LICENSE.
*
*
* $Id$
*/
#include <bsp.h>
#include <rtems/error.h>
#include <errno.h>
/*
* Location of 'VME' access
*/
@@ -53,7 +53,7 @@ extern char RamBase[];
* If a write to the CACR is performed to clear the cache (CINV = BIT 24 set)
* and only a partial clear will be done (INVI = BIT 21 or INVD = BIT 20 set),
* then cache corruption may occur.
*
*
* 6.2 Workaround
* All loads of the CACR that perform a cache clear operation (CINV = BIT 24)
* should be followed immediately by a NOP instruction. This avoids the cache
@@ -63,16 +63,16 @@ extern char RamBase[];
*
* Buffered writes must be disabled as described in "MCF5282 Chip Errata",
* MCF5282DE, Rev. 6, 5/2009:
* SECF124: Buffered Write May Be Executed Twice
* Errata type: Silicon
* Affected component: Cache
* SECF124: Buffered Write May Be Executed Twice
* Errata type: Silicon
* Affected component: Cache
* Description: If buffered writes are enabled using the CACR or ACR
* registers, the imprecise write transaction generated
* by a buffered write may be executed twice.
* Workaround: Do not enable buffered writes in the CACR or ACR registers:
* CACR[8] = DBWE (default buffered write enable) must be 0
* ACRn[5] = BUFW (buffered write enable) must be 0
* Fix plan: Currently, there are no plans to fix this.
* by a buffered write may be executed twice.
* Workaround: Do not enable buffered writes in the CACR or ACR registers:
* CACR[8] = DBWE (default buffered write enable) must be 0
* ACRn[5] = BUFW (buffered write enable) must be 0
* Fix plan: Currently, there are no plans to fix this.
*/
#define m68k_set_cacr_nop(_cacr) asm volatile ("movec %0,%%cacr\n\tnop" : : "d" (_cacr))
#define m68k_set_cacr(_cacr) asm volatile ("movec %0,%%cacr" : : "d" (_cacr))
@@ -282,7 +282,7 @@ void bsp_start( void )
* Two A24/D16 spaces, supervisor data acces
*/
MCF5282_CS1_CSAR = MCF5282_CS_CSAR_BA(VME_ONE_BASE);
MCF5282_CS1_CSMR = MCF5282_CS_CSMR_BAM_16M |
MCF5282_CS1_CSMR = MCF5282_CS_CSMR_BAM_16M |
MCF5282_CS_CSMR_CI |
MCF5282_CS_CSMR_SC |
MCF5282_CS_CSMR_UC |
@@ -290,7 +290,7 @@ void bsp_start( void )
MCF5282_CS_CSMR_V;
MCF5282_CS1_CSCR = MCF5282_CS_CSCR_PS_16;
MCF5282_CS2_CSAR = MCF5282_CS_CSAR_BA(VME_TWO_BASE);
MCF5282_CS2_CSMR = MCF5282_CS_CSMR_BAM_16M |
MCF5282_CS2_CSMR = MCF5282_CS_CSMR_BAM_16M |
MCF5282_CS_CSMR_CI |
MCF5282_CS_CSMR_SC |
MCF5282_CS_CSMR_UC |
@@ -511,7 +511,7 @@ fpga_trampoline (rtems_vector_number v)
static rtems_isr
trampoline (rtems_vector_number v)
{
if (handlerTab[v].func)
if (handlerTab[v].func)
(*handlerTab[v].func)(handlerTab[v].arg, (unsigned long)v);
}
@@ -605,7 +605,7 @@ rtems_interrupt_level level;
if (source < 8)
MCF5282_EPORT_EPIER |= 1 << source;
else
*(&MCF5282_INTC0_ICR1 + (source - 1)) =
*(&MCF5282_INTC0_ICR1 + (source - 1)) =
MCF5282_INTC_ICR_IL(l) |
MCF5282_INTC_ICR_IP(p);
enable_irq(source);
@@ -691,7 +691,7 @@ rtems_bsp_reset_cause(char *buf, size_t capacity)
int bit, rsr;
size_t i;
const char *cp;
if (buf == NULL)
return;
if (capacity)
@@ -709,13 +709,13 @@ rtems_bsp_reset_cause(char *buf, size_t capacity)
case MCF5282_RESET_RSR_LOL: cp = "Loss of lock"; break;
default: cp = "??"; break;
}
i += snprintf(buf+i, capacity-i, cp);
i += snprintf(buf+i, capacity-i, cp);
if (i >= capacity)
break;
rsr &= ~bit;
if (rsr == 0)
break;
i += snprintf(buf+i, capacity-i, ", ");
i += snprintf(buf+i, capacity-i, ", ");
if (i >= capacity)
break;
}

4
c/src/lib/libbsp/m68k/uC5282/startup/init5282.c
View File

@@ -2,7 +2,7 @@
* This is where the real hardware setup is done. A minimal stack
* has been provided by the start.S code. No normal C or RTEMS
* functions can be called from here.
*
*
* This routine is pretty simple for the uC5282 because all the hard
* work has been done by the bootstrap dBUG code.
*
@@ -26,7 +26,7 @@
void Init5282 (void)
{
extern void CopyDataClearBSSAndStart (void);
/*
* Copy data, clear BSS and call boot_card()
*/