From c538079ec1d72b6d6d87b3913337fe2f65c7bda4 Mon Sep 17 00:00:00 2001 From: Sebastian Huber Date: Fri, 4 Oct 2024 03:48:19 +0200 Subject: [PATCH] aarch64: Remove trapped FP exceptions support Whether a floating-point implementation supports trapping of floating-point exceptions is implementation defined. At least Qemu, Cortex-A53, and Cortex-A72 do not support them. --- .../cpu/aarch64/aarch64-exception-default.c | 21 ------------------- 1 file changed, 21 deletions(-) diff --git a/cpukit/score/cpu/aarch64/aarch64-exception-default.c b/cpukit/score/cpu/aarch64/aarch64-exception-default.c index e8c7a2bab9..da13639bd7 100644 --- a/cpukit/score/cpu/aarch64/aarch64-exception-default.c +++ b/cpukit/score/cpu/aarch64/aarch64-exception-default.c @@ -42,29 +42,8 @@ #include #include -#include void _AArch64_Exception_default( CPU_Exception_frame *frame ) { - uint64_t EC = AARCH64_ESR_EL1_EC_GET( frame->register_syndrome ); - - /* Emulate FPSR flags for FENV if a FPU exception occurred */ - if ( EC == 0x2c ) { - /* - * This must be done because FENV depends on FPSR values, but trapped FPU - * exceptions don't set FPSR bits. In the case where a signal is mapped, the - * signal code executes after the exception frame is restored and FENV - * functions executed in that context will need this information to be - * accurate. - */ - uint64_t ISS = AARCH64_ESR_EL1_EC_GET( frame->register_syndrome ); - - /* If the exception bits are valid, use them */ - if ( ( ISS & ( 1 << 23 ) ) != 0 ) { - /* The bits of the lower byte match the FPSR exception bits */ - frame->register_fpsr |= ( ISS & 0xff ); - } - } - rtems_fatal( RTEMS_FATAL_SOURCE_EXCEPTION, (rtems_fatal_code) frame ); }