RTOS/rtems
1
0
Fork 0
forked from Imagelibrary/rtems
Code Pull Requests Activity

bsps/arm: Use fatal error for data cache disable

Browse Source 
On the Cortex-A cores, at least the L1 data cache is required to provide
support for atomic operations.

Close #5050.
This commit is contained in:
Sebastian Huber
2024-06-24 08:30:49 +02:00
committed by Amar Takhar
parent 3a281aca37
commit c4c3e68790
4 changed files with 4 additions and 32 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
bsps/arm/shared/cache/cache-cp15.h vendored
View File

@@ -360,15 +360,6 @@ static inline void arm_cache_l1_unfreeze_instruction( void )
/* To be implemented as needed, if supported by hardware at all */
}
static inline void arm_cache_l1_disable_data( void )
{
/* Clean and invalidate the Data cache */
arm_cache_l1_flush_entire_data();
/* Disable the Data cache */
arm_cp15_set_control( arm_cp15_get_control() & ~ARM_CP15_CTRL_C );
}
static inline size_t arm_cache_l1_get_data_cache_size( void )
{
size_t size;