From c4c3e687903dccbb3679e3bd5babb87b95c507dc Mon Sep 17 00:00:00 2001
From: Sebastian Huber <sebastian.huber@embedded-brains.de>
Date: Mon, 24 Jun 2024 08:30:49 +0200
Subject: [PATCH] bsps/arm: Use fatal error for data cache disable

On the Cortex-A cores, at least the L1 data cache is required to provide
support for atomic operations.

Close #5050.
---
 bsps/arm/shared/cache/cache-cp15.h            |  9 --------
 bsps/arm/shared/cache/cache-l2c-310.c         | 22 +------------------
 .../validation/objcachedisabledata.yml        |  3 ++-
 .../validation/objcachenodisabledata.yml      |  2 +-
 4 files changed, 4 insertions(+), 32 deletions(-)

diff --git a/bsps/arm/shared/cache/cache-cp15.h b/bsps/arm/shared/cache/cache-cp15.h
index 92eb16ca2b..61d9f6fae7 100644
--- a/bsps/arm/shared/cache/cache-cp15.h
+++ b/bsps/arm/shared/cache/cache-cp15.h
@@ -360,15 +360,6 @@ static inline void arm_cache_l1_unfreeze_instruction( void )
   /* To be implemented as needed, if supported by hardware at all */
 }
 
-static inline void arm_cache_l1_disable_data( void )
-{
-  /* Clean and invalidate the Data cache */
-  arm_cache_l1_flush_entire_data();
-
-  /* Disable the Data cache */
-  arm_cp15_set_control( arm_cp15_get_control() & ~ARM_CP15_CTRL_C );
-}
-
 static inline size_t arm_cache_l1_get_data_cache_size( void )
 {
   size_t   size;
diff --git a/bsps/arm/shared/cache/cache-l2c-310.c b/bsps/arm/shared/cache/cache-l2c-310.c
index 16a5489fcc..212d2adc27 100644
--- a/bsps/arm/shared/cache/cache-l2c-310.c
+++ b/bsps/arm/shared/cache/cache-l2c-310.c
@@ -1154,25 +1154,6 @@ l2c_310_enable( void )
   }
 }
 
-static inline void
-l2c_310_disable( void )
-{
-  volatile L2CC               *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE;
-  rtems_interrupt_lock_context lock_context;
-
-  if ( l2cc->ctrl & L2C_310_CTRL_ENABLE ) {
-    /* Clean and Invalidate L2 Cache */
-    l2c_310_flush_entire();
-    rtems_interrupt_lock_acquire( &l2c_310_lock, &lock_context );
-
-    l2c_310_wait_for_background_ops( l2cc );
-
-    /* Disable the L2 cache */
-    l2cc->ctrl &= ~L2C_310_CTRL_ENABLE;
-    rtems_interrupt_lock_release( &l2c_310_lock, &lock_context );
-  }
-}
-
 static inline void
 _CPU_cache_enable_data( void )
 {
@@ -1182,8 +1163,7 @@ _CPU_cache_enable_data( void )
 static inline void
 _CPU_cache_disable_data( void )
 {
-  arm_cache_l1_disable_data();
-  l2c_310_disable();
+  _Internal_error( INTERNAL_ERROR_CANNOT_DISABLE_DATA_CACHE );
 }
 
 static void l2c_310_enable_instruction( void *arg )
diff --git a/spec/build/testsuites/validation/objcachedisabledata.yml b/spec/build/testsuites/validation/objcachedisabledata.yml
index 949fa7ee55..e02a415496 100644
--- a/spec/build/testsuites/validation/objcachedisabledata.yml
+++ b/spec/build/testsuites/validation/objcachedisabledata.yml
@@ -5,7 +5,8 @@ copyrights:
 - Copyright (C) 2024 embedded brains GmbH & Co. KG
 cppflags: []
 cxxflags: []
-enabled-by: true
+enabled-by:
+  not: bsps/arm/xilinx-zynq
 includes: []
 install: []
 links: []
diff --git a/spec/build/testsuites/validation/objcachenodisabledata.yml b/spec/build/testsuites/validation/objcachenodisabledata.yml
index 51bd214301..13e0377c2f 100644
--- a/spec/build/testsuites/validation/objcachenodisabledata.yml
+++ b/spec/build/testsuites/validation/objcachenodisabledata.yml
@@ -5,7 +5,7 @@ copyrights:
 - Copyright (C) 2024 embedded brains GmbH & Co. KG
 cppflags: []
 cxxflags: []
-enabled-by: false
+enabled-by: bsps/arm/xilinx-zynq
 includes: []
 install: []
 links: []