forked from Imagelibrary/rtems
122 lines
2.6 KiB
C
122 lines
2.6 KiB
C
/**
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* @file
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*
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* @ingroup arm_gic
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*
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* @brief ARM GIC IRQ
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*/
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/*
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* Copyright (c) 2013, 2019 embedded brains GmbH. All rights reserved.
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*
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* embedded brains GmbH
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* Dornierstr. 4
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* 82178 Puchheim
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* Germany
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* <info@embedded-brains.de>
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.org/license/LICENSE.
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*/
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#ifndef LIBBSP_ARM_SHARED_ARM_GIC_IRQ_H
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#define LIBBSP_ARM_SHARED_ARM_GIC_IRQ_H
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#include <bsp.h>
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#include <dev/irq/arm-gic.h>
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#include <rtems/score/processormask.h>
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#ifdef __cplusplus
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extern "C" {
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#endif /* __cplusplus */
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#define ARM_GIC_IRQ_SGI_0 0
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#define ARM_GIC_IRQ_SGI_1 1
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#define ARM_GIC_IRQ_SGI_2 2
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#define ARM_GIC_IRQ_SGI_3 3
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#define ARM_GIC_IRQ_SGI_5 5
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#define ARM_GIC_IRQ_SGI_6 6
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#define ARM_GIC_IRQ_SGI_7 7
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#define ARM_GIC_IRQ_SGI_8 8
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#define ARM_GIC_IRQ_SGI_9 9
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#define ARM_GIC_IRQ_SGI_10 10
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#define ARM_GIC_IRQ_SGI_11 11
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#define ARM_GIC_IRQ_SGI_12 12
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#define ARM_GIC_IRQ_SGI_13 13
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#define ARM_GIC_IRQ_SGI_14 14
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#define ARM_GIC_IRQ_SGI_15 15
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#define ARM_GIC_DIST ((volatile gic_dist *) BSP_ARM_GIC_DIST_BASE)
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rtems_status_code arm_gic_irq_set_priority(
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rtems_vector_number vector,
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uint8_t priority
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);
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rtems_status_code arm_gic_irq_get_priority(
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rtems_vector_number vector,
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uint8_t *priority
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);
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rtems_status_code arm_gic_irq_set_group(
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rtems_vector_number vector,
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gic_group group
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);
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rtems_status_code arm_gic_irq_get_group(
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rtems_vector_number vector,
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gic_group *group
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);
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void bsp_interrupt_set_affinity(
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rtems_vector_number vector,
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const Processor_mask *affinity
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);
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void bsp_interrupt_get_affinity(
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rtems_vector_number vector,
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Processor_mask *affinity
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);
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void arm_gic_trigger_sgi(rtems_vector_number vector, uint32_t targets);
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static inline rtems_status_code arm_gic_irq_generate_software_irq(
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rtems_vector_number vector,
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uint32_t targets
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)
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{
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rtems_status_code sc = RTEMS_SUCCESSFUL;
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if (vector <= ARM_GIC_IRQ_SGI_15) {
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arm_gic_trigger_sgi(vector, targets);
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} else {
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sc = RTEMS_INVALID_ID;
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}
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return sc;
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}
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/**
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* This architecture-specific function sets the exception vector for handling
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* IRQs.
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*/
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void arm_interrupt_facility_set_exception_handler(void);
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/**
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* This architecture-specific function dispatches a triggered IRQ.
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*
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* @param[in] vector The vector on which the IRQ occurred.
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*/
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void arm_interrupt_handler_dispatch(rtems_vector_number vector);
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uint32_t arm_gic_irq_processor_count(void);
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void arm_gic_irq_initialize_secondary_cpu(void);
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#ifdef __cplusplus
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}
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#endif /* __cplusplus */
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#endif /* LIBBSP_ARM_SHARED_ARM_GIC_IRQ_H */
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