forked from Imagelibrary/rtems
2002-04-18 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
* shared/include/cpu.h: Removed. * shared/include/Makefile.am: Reflect changes above. * shared/include/spr.h: Include rtems/powerpc/registers.h instead of libcpu/cpu.h. * mpc6xx/clock/c_clock.c: Reflect changes to <rtems/score/cpu.h>. * mpc6xx/exceptions/asm_utils.S: Ditto. * mpc6xx/exceptions/raw_exception.c: Ditto. * mpc6xx/mmu/mmuAsm.S: Ditto. * mpc6xx/timer/timer.c: Ditto. * mpc8260/exceptions/asm_utils.S: Ditto. * mpc8260/exceptions/raw_exception.c: Ditto. * mpc8xx/exceptions/asm_utils.S: Ditto. * mpc8xx/exceptions/raw_exception.c: Ditto. * ppc403/vectors/vectors.S: Include <asm.h> instead of "asm.h".
This commit is contained in:
Joel Sherrill
@@ -1,3 +1,20 @@
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2002-04-18 Ralf Corsepius <corsepiu@faw.uni-ulm.de>
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* shared/include/cpu.h: Removed.
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* shared/include/Makefile.am: Reflect changes above.
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* shared/include/spr.h: Include rtems/powerpc/registers.h instead of
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libcpu/cpu.h.
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* mpc6xx/clock/c_clock.c: Reflect changes to <rtems/score/cpu.h>.
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* mpc6xx/exceptions/asm_utils.S: Ditto.
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* mpc6xx/exceptions/raw_exception.c: Ditto.
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* mpc6xx/mmu/mmuAsm.S: Ditto.
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* mpc6xx/timer/timer.c: Ditto.
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* mpc8260/exceptions/asm_utils.S: Ditto.
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* mpc8260/exceptions/raw_exception.c: Ditto.
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* mpc8xx/exceptions/asm_utils.S: Ditto.
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* mpc8xx/exceptions/raw_exception.c: Ditto.
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* ppc403/vectors/vectors.S: Include <asm.h> instead of "asm.h".
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2001-04-17 Joel Sherrill <joel@OARcorp.com>
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* shared/include/cpu.h: Added ifndef ASM.
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@@ -19,11 +19,11 @@
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* $Id$
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*/
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#include <rtems/system.h>
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#include <rtems.h>
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#include <rtems/libio.h>
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#include <stdlib.h> /* for atexit() */
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#include <assert.h>
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#include <libcpu/cpu.h>
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#include <libcpu/c_clock.h>
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#include <rtems/bspIo.h> /* for printk() */
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@@ -10,10 +10,9 @@
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*
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*/
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#include <libcpu/cpu.h>
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#include <asm.h>
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#include <rtems/score/cpu.h>
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#include <libcpu/io.h>
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#include <rtems/score/targopts.h>
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#include "asm.h"
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.globl codemove
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codemove:
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@@ -20,12 +20,10 @@
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*
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* $Id$
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*/
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#include <rtems/score/targopts.h>
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#include <rtems/system.h>
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#include <rtems/score/ppc.h>
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#include <rtems/system.h>
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#include <rtems/score/cpu.h>
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#include <libcpu/raw_exception.h>
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#include <libcpu/cpu.h>
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#include <libcpu/cpuIdent.h>
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static rtems_raw_except_connect_data* raw_except_table;
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@@ -14,10 +14,9 @@
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*
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*/
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#include <libcpu/cpu.h>
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#include <asm.h>
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#include <rtems/score/cpu.h>
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#include <libcpu/io.h>
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#include <rtems/score/targopts.h>
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#include "asm.h"
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/*
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* Each setdbat routine start by invalidating the DBAT as some
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@@ -14,9 +14,9 @@
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* $Id$
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*/
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#include <rtems/system.h>
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#include <assert.h>
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#include <rtems.h>
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#include <libcpu/cpu.h>
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#include <bsp.h>
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rtems_unsigned64 Timer_driver_Start_time;
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@@ -10,10 +10,9 @@
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*
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*/
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#include <libcpu/cpu.h>
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#include <asm.h>
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#include <rtems/score/cpu.h>
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#include <libcpu/io.h>
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#include <rtems/score/targopts.h>
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#include "asm.h"
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.globl codemove
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codemove:
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@@ -20,12 +20,10 @@
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*
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* $Id$
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*/
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#include <rtems/score/targopts.h>
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#include <rtems/score/ppc.h>
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#include <rtems/system.h>
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#include <rtems/score/cpu.h>
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#include <rtems/score/ppc.h>
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#include <libcpu/raw_exception.h>
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#include <libcpu/cpu.h>
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#include <libcpu/cpuIdent.h>
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static rtems_raw_except_connect_data* raw_except_table;
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@@ -10,10 +10,9 @@
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*
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*/
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#include <libcpu/cpu.h>
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#include <asm.h>
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#include <rtems/score/cpu.h>
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#include <libcpu/io.h>
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#include <rtems/score/targopts.h>
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#include "asm.h"
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.globl codemove
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codemove:
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@@ -17,13 +17,13 @@
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*
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* $Id$
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*/
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#include <rtems/score/targopts.h>
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#include <rtems/score/ppc.h>
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#include <rtems/system.h>
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#include <rtems/score/cpu.h>
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#include <rtems/score/ppc.h>
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#include <libcpu/raw_exception.h>
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#include <libcpu/cpu.h>
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#include <libcpu/cpuIdent.h>
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#include <rtems/bspIo.h> /* for printk */
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static rtems_raw_except_connect_data* raw_except_table;
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static rtems_raw_except_connect_data default_raw_except_entry;
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@@ -41,7 +41,7 @@
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*/
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#include <bsp.h> /* PPC_VECTOR_FILE_BASE */
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#include "asm.h"
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#include <asm.h>
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#ifndef PPC_VECTOR_FILE_BASE
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#error "PPC_VECTOR_FILE_BASE is not defined."
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@@ -8,7 +8,7 @@ C_O_FILES = $(C_FILES:%.c=$(ARCH)/%.o)
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include_libcpudir = $(includedir)/libcpu
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include_libcpu_HEADERS = cpu.h spr.h io.h mmu.h page.h byteorder.h pgtable.h \
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include_libcpu_HEADERS = spr.h io.h mmu.h page.h byteorder.h pgtable.h \
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cpuIdent.h
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OBJS = $(C_O_FILES)
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@@ -1,310 +0,0 @@
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/*
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* cpu.h
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*
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* This file contains some powerpc MSR and registers access definitions.
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*
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* It is a stripped down version of linux ppc processor.h file...
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*
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* Copyright (C) 1999 Eric Valette (valette@crf.canon.fr)
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* Canon Centre Recherche France.
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*
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* Added MPC8260 Andy Dachs <a.dachs@sstl.co.uk>
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* Surrey Satellite Technology Limited
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*
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*
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* The license and distribution terms for this file may be
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* found in found in the file LICENSE in this distribution or at
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* http://www.OARcorp.com/rtems/license.html.
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*
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* $Id$
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*/
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#ifndef __PPC_CPU_H
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#define __PPC_CPU_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Bit encodings for Machine State Register (MSR) */
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#define MSR_POW (1<<18) /* Enable Power Management */
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#define MSR_TGPR (1<<17) /* TLB Update registers in use */
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#define MSR_ILE (1<<16) /* Interrupt Little-Endian enable */
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#define MSR_EE (1<<15) /* External Interrupt enable */
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#define MSR_PR (1<<14) /* Supervisor/User privilege */
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#define MSR_FP (1<<13) /* Floating Point enable */
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#define MSR_ME (1<<12) /* Machine Check enable */
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#define MSR_FE0 (1<<11) /* Floating Exception mode 0 */
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#define MSR_SE (1<<10) /* Single Step */
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#define MSR_BE (1<<9) /* Branch Trace */
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#define MSR_FE1 (1<<8) /* Floating Exception mode 1 */
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#define MSR_IP (1<<6) /* Exception prefix 0x000/0xFFF */
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#define MSR_IR (1<<5) /* Instruction MMU enable */
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#define MSR_DR (1<<4) /* Data MMU enable */
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#define MSR_RI (1<<1) /* Recoverable Exception */
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#define MSR_LE (1<<0) /* Little-Endian enable */
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#define MSR_ MSR_ME|MSR_RI
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#define MSR_KERNEL MSR_|MSR_IR|MSR_DR
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#define MSR_USER MSR_KERNEL|MSR_PR|MSR_EE
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/* Bit encodings for Hardware Implementation Register (HID0)
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on PowerPC 603, 604, etc. processors (not 601). */
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#define HID0_EMCP (1<<31) /* Enable Machine Check pin */
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#define HID0_EBA (1<<29) /* Enable Bus Address Parity */
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#define HID0_EBD (1<<28) /* Enable Bus Data Parity */
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#define HID0_SBCLK (1<<27)
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#define HID0_EICE (1<<26)
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#define HID0_ECLK (1<<25)
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#define HID0_PAR (1<<24)
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#define HID0_DOZE (1<<23)
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#define HID0_NAP (1<<22)
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#define HID0_SLEEP (1<<21)
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#define HID0_DPM (1<<20)
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#define HID0_ICE (1<<15) /* Instruction Cache Enable */
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#define HID0_DCE (1<<14) /* Data Cache Enable */
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#define HID0_ILOCK (1<<13) /* Instruction Cache Lock */
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#define HID0_DLOCK (1<<12) /* Data Cache Lock */
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#define HID0_ICFI (1<<11) /* Instruction Cache Flash Invalidate */
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#define HID0_DCI (1<<10) /* Data Cache Invalidate */
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#define HID0_SIED (1<<7) /* Serial Instruction Execution [Disable] */
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#define HID0_BHTE (1<<2) /* Branch History Table Enable */
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#define HID0_BTCD (1<<1) /* Branch target cache disable */
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/* fpscr settings */
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#define FPSCR_FX (1<<31)
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#define FPSCR_FEX (1<<30)
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#define _MACH_prep 1
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#define _MACH_Pmac 2 /* pmac or pmac clone (non-chrp) */
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#define _MACH_chrp 4 /* chrp machine */
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#define _MACH_mbx 8 /* Motorola MBX board */
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#define _MACH_apus 16 /* amiga with phase5 powerup */
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#define _MACH_fads 32 /* Motorola FADS board */
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/* see residual.h for these */
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#define _PREP_Motorola 0x01 /* motorola prep */
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#define _PREP_Firm 0x02 /* firmworks prep */
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#define _PREP_IBM 0x00 /* ibm prep */
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#define _PREP_Bull 0x03 /* bull prep */
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/* these are arbitrary */
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#define _CHRP_Motorola 0x04 /* motorola chrp, the cobra */
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#define _CHRP_IBM 0x05 /* IBM chrp, the longtrail and longtrail 2 */
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#define _GLOBAL(n)\
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.globl n;\
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n:
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#define TBRU 269 /* Time base Upper/Lower (Reading) */
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#define TBRL 268
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#define TBWU 284 /* Time base Upper/Lower (Writing) */
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#define TBWL 285
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#define XER 1
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#define LR 8
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#define CTR 9
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#define HID0 1008 /* Hardware Implementation */
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#define PVR 287 /* Processor Version */
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#define IBAT0U 528 /* Instruction BAT #0 Upper/Lower */
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#define IBAT0L 529
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#define IBAT1U 530 /* Instruction BAT #1 Upper/Lower */
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#define IBAT1L 531
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#define IBAT2U 532 /* Instruction BAT #2 Upper/Lower */
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#define IBAT2L 533
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#define IBAT3U 534 /* Instruction BAT #3 Upper/Lower */
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#define IBAT3L 535
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#define DBAT0U 536 /* Data BAT #0 Upper/Lower */
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#define DBAT0L 537
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#define DBAT1U 538 /* Data BAT #1 Upper/Lower */
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#define DBAT1L 539
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#define DBAT2U 540 /* Data BAT #2 Upper/Lower */
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#define DBAT2L 541
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#define DBAT3U 542 /* Data BAT #3 Upper/Lower */
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#define DBAT3L 543
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#define DMISS 976 /* TLB Lookup/Refresh registers */
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#define DCMP 977
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#define HASH1 978
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#define HASH2 979
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#define IMISS 980
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#define ICMP 981
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#define RPA 982
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#define SDR1 25 /* MMU hash base register */
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#define DAR 19 /* Data Address Register */
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#define SPR0 272 /* Supervisor Private Registers */
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#define SPRG0 272
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#define SPR1 273
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#define SPRG1 273
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#define SPR2 274
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#define SPRG2 274
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#define SPR3 275
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#define SPRG3 275
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#define DSISR 18
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#define SRR0 26 /* Saved Registers (exception) */
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#define SRR1 27
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#define IABR 1010 /* Instruction Address Breakpoint */
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#define DEC 22 /* Decrementer */
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#define EAR 282 /* External Address Register */
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#define L2CR 1017 /* PPC 750 L2 control register */
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#define THRM1 1020
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#define THRM2 1021
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#define THRM3 1022
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#define THRM1_TIN 0x1
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#define THRM1_TIV 0x2
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#define THRM1_THRES (0x7f<<2)
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#define THRM1_TID (1<<29)
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#define THRM1_TIE (1<<30)
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#define THRM1_V (1<<31)
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#define THRM3_E (1<<31)
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/* Segment Registers */
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#define SR0 0
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#define SR1 1
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#define SR2 2
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#define SR3 3
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#define SR4 4
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#define SR5 5
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#define SR6 6
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#define SR7 7
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#define SR8 8
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#define SR9 9
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#define SR10 10
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#define SR11 11
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#define SR12 12
|
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#define SR13 13
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#define SR14 14
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#define SR15 15
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/*
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* Routines to access the time base register
|
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*/
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#ifndef ASM
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static inline unsigned long long PPC_Get_timebase_register( void )
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{
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unsigned long tbr_low;
|
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unsigned long tbr_high;
|
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unsigned long tbr_high_old;
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unsigned long long tbr;
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do {
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asm volatile( "mftbu %0" : "=r" (tbr_high_old));
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asm volatile( "mftb %0" : "=r" (tbr_low));
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asm volatile( "mftbu %0" : "=r" (tbr_high));
|
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} while ( tbr_high_old != tbr_high );
|
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tbr = tbr_high;
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tbr <<= 32;
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tbr |= tbr_low;
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return tbr;
|
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}
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static inline void PPC_Set_timebase_register (unsigned long long tbr)
|
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{
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unsigned long tbr_low;
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unsigned long tbr_high;
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|
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tbr_low = (tbr & 0xffffffff) ;
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tbr_high = (tbr >> 32) & 0xffffffff;
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asm volatile( "mtspr 284, %0" : : "r" (tbr_low));
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asm volatile( "mtspr 285, %0" : : "r" (tbr_high));
|
||||
|
||||
}
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#endif /* ASM */
|
||||
|
||||
#define _CPU_MSR_GET( _msr_value ) \
|
||||
do { \
|
||||
_msr_value = 0; \
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asm volatile ("mfmsr %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); \
|
||||
} while (0)
|
||||
|
||||
#define _CPU_MSR_SET( _msr_value ) \
|
||||
{ asm volatile ("mtmsr %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); }
|
||||
|
||||
#define _CPU_ISR_Disable( _isr_cookie ) \
|
||||
{ register unsigned int _disable_mask = MSR_EE; \
|
||||
_isr_cookie = 0; \
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||||
asm volatile ( \
|
||||
"mfmsr %0; andc %1,%0,%1; mtmsr %1" : \
|
||||
"=&r" ((_isr_cookie)), "=&r" ((_disable_mask)) : \
|
||||
"0" ((_isr_cookie)), "1" ((_disable_mask)) \
|
||||
); \
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
|
||||
* This indicates the end of an RTEMS critical section. The parameter
|
||||
* _isr_cookie is not modified.
|
||||
*/
|
||||
|
||||
#define _CPU_ISR_Enable( _isr_cookie ) \
|
||||
{ \
|
||||
asm volatile ( "mtmsr %0" : \
|
||||
"=r" ((_isr_cookie)) : \
|
||||
"0" ((_isr_cookie))); \
|
||||
}
|
||||
|
||||
/*
|
||||
* This temporarily restores the interrupt to _isr_cookie before immediately
|
||||
* disabling them again. This is used to divide long RTEMS critical
|
||||
* sections into two or more parts. The parameter _isr_cookie is not
|
||||
* modified.
|
||||
*
|
||||
* NOTE: The version being used is not very optimized but it does
|
||||
* not trip a problem in gcc where the disable mask does not
|
||||
* get loaded. Check this for future (post 10/97 gcc versions.
|
||||
*/
|
||||
|
||||
#define _CPU_ISR_Flash( _isr_cookie ) \
|
||||
{ register unsigned int _disable_mask = MSR_EE; \
|
||||
asm volatile ( \
|
||||
"mtmsr %0; andc %1,%0,%1; mtmsr %1" : \
|
||||
"=r" ((_isr_cookie)), "=r" ((_disable_mask)) : \
|
||||
"0" ((_isr_cookie)), "1" ((_disable_mask)) \
|
||||
); \
|
||||
}
|
||||
|
||||
|
||||
/* end of ISR handler macros */
|
||||
|
||||
/*
|
||||
* Simple spin delay in microsecond units for device drivers.
|
||||
* This is very dependent on the clock speed of the target.
|
||||
*/
|
||||
|
||||
#define CPU_Get_timebase_low( _value ) \
|
||||
asm volatile( "mftb %0" : "=r" (_value) )
|
||||
|
||||
#define rtems_bsp_delay( _microseconds ) \
|
||||
do { \
|
||||
unsigned32 start, ticks, now; \
|
||||
CPU_Get_timebase_low( start ) ; \
|
||||
ticks = (_microseconds) * rtems_cpu_configuration_get_clicks_per_usec(); \
|
||||
do \
|
||||
CPU_Get_timebase_low( now ) ; \
|
||||
while (now - start < ticks); \
|
||||
} while (0)
|
||||
|
||||
#define rtems_bsp_delay_in_bus_cycles( _cycles ) \
|
||||
do { \
|
||||
unsigned32 start, now; \
|
||||
CPU_Get_timebase_low( start ); \
|
||||
do \
|
||||
CPU_Get_timebase_low( now ); \
|
||||
while (now - start < (_cycles)); \
|
||||
} while (0)
|
||||
|
||||
#define PPC_Set_decrementer( _clicks ) \
|
||||
do { \
|
||||
asm volatile( "mtdec %0" : "=r" ((_clicks)) : "r" ((_clicks)) ); \
|
||||
} while (0)
|
||||
|
||||
#define PPC_Get_decrementer( _clicks ) \
|
||||
asm volatile( "mfdec %0" : "=r" (_clicks) )
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __PPC_CPU_H */
|
||||
@@ -20,7 +20,7 @@
|
||||
#ifndef _PPC_SPR_H
|
||||
#define _PPC_SPR_H
|
||||
|
||||
#include <libcpu/cpu.h>
|
||||
#include <rtems/powerpc/registers.h>
|
||||
|
||||
#define __MFSPR(reg, val) \
|
||||
__asm__ __volatile__("mfspr %0,"#reg : "=r" (val))
|
||||
|
||||
Reference in New Issue
Block a user