forked from Imagelibrary/rtems
a73a977d73
* shared/include/cpu.h: Removed. * shared/include/Makefile.am: Reflect changes above. * shared/include/spr.h: Include rtems/powerpc/registers.h instead of libcpu/cpu.h. * mpc6xx/clock/c_clock.c: Reflect changes to <rtems/score/cpu.h>. * mpc6xx/exceptions/asm_utils.S: Ditto. * mpc6xx/exceptions/raw_exception.c: Ditto. * mpc6xx/mmu/mmuAsm.S: Ditto. * mpc6xx/timer/timer.c: Ditto. * mpc8260/exceptions/asm_utils.S: Ditto. * mpc8260/exceptions/raw_exception.c: Ditto. * mpc8xx/exceptions/asm_utils.S: Ditto. * mpc8xx/exceptions/raw_exception.c: Ditto. * ppc403/vectors/vectors.S: Include <asm.h> instead of "asm.h".
65 lines
1.2 KiB
ArmAsm
65 lines
1.2 KiB
ArmAsm
/*
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* asm_utils.s
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*
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* $Id$
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*
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* Copyright (C) 1999 Eric Valette (valette@crf.canon.fr)
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*
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* This file contains the low-level support for moving exception
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* exception code to appropriate location.
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*
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*/
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#include <asm.h>
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#include <rtems/score/cpu.h>
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#include <libcpu/io.h>
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.globl codemove
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codemove:
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.type codemove,@function
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/* r3 dest, r4 src, r5 length in bytes, r6 cachelinesize */
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cmplw cr1,r3,r4
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addi r0,r5,3
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srwi. r0,r0,2
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beq cr1,4f /* In place copy is not necessary */
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beq 7f /* Protect against 0 count */
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mtctr r0
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bge cr1,2f
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la r8,-4(r4)
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la r7,-4(r3)
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1: lwzu r0,4(r8)
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stwu r0,4(r7)
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bdnz 1b
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b 4f
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2: slwi r0,r0,2
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add r8,r4,r0
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add r7,r3,r0
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3: lwzu r0,-4(r8)
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stwu r0,-4(r7)
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bdnz 3b
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/* Now flush the cache: note that we must start from a cache aligned
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* address. Otherwise we might miss one cache line.
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*/
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4: cmpwi r6,0
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add r5,r3,r5
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beq 7f /* Always flush prefetch queue in any case */
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subi r0,r6,1
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andc r3,r3,r0
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mr r4,r3
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5: cmplw r4,r5
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dcbst 0,r4
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add r4,r4,r6
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blt 5b
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sync /* Wait for all dcbst to complete on bus */
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mr r4,r3
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6: cmplw r4,r5
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icbi 0,r4
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add r4,r4,r6
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blt 6b
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7: sync /* Wait for all icbi to complete on bus */
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isync
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blr
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