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2007-05-31 Alain Schaefer <alani@easc.ch>

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* rtems/score/cpu.h: Modifiy inline assembly language
	constraints to use a data register as the CTL/STI
	instructions requires. This is not only more correct,
	it avoids GCC PR31787.
This commit is contained in:
Joel Sherrill
2007-05-31 16:55:37 +00:00
parent a607c87225
commit 008171099d
2 changed files with 12 additions and 5 deletions
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7
cpukit/score/cpu/bfin/ChangeLog
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@@ -1,3 +1,10 @@
2007-05-31 Alain Schaefer <alani@easc.ch>
* rtems/score/cpu.h: Modifiy inline assembly language
constraints to use a data register as the CTL/STI
instructions requires. This is not only more correct,
it avoids GCC PR31787.
2007-05-24 Alain Schaefer <alani@easc.ch> 2007-05-24 Alain Schaefer <alani@easc.ch>
* rtems/score/cpu.h: Fix incorrect interrupt mask. * rtems/score/cpu.h: Fix incorrect interrupt mask.

6
cpukit/score/cpu/bfin/rtems/score/cpu.h
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@@ -847,7 +847,7 @@ SCORE_EXTERN void (*_CPU_Thread_dispatch_pointer)();
#define _CPU_ISR_Disable( _level ) \ #define _CPU_ISR_Disable( _level ) \
{ \ { \
asm volatile ("cli %0 \n" \ asm volatile ("cli %0 \n" \
: "=r" (_level) ); \ : "=d" (_level) ); \
\ \
} }
@@ -866,8 +866,8 @@ SCORE_EXTERN void (*_CPU_Thread_dispatch_pointer)();
*/ */
#define _CPU_ISR_Enable( _level ) \ #define _CPU_ISR_Enable( _level ) \
{ \ { \
asm volatile ("STI %0" \ asm volatile ("STI %0 \n" \
: : "r" (_level) ); \ : : "d" (_level) ); \
} }
/** /**