diff --git a/cpukit/score/cpu/bfin/ChangeLog b/cpukit/score/cpu/bfin/ChangeLog
index 5869fa2cc7..2584deb2b7 100644
--- a/cpukit/score/cpu/bfin/ChangeLog
+++ b/cpukit/score/cpu/bfin/ChangeLog
@@ -1,3 +1,10 @@
+2007-05-31	Alain Schaefer <alani@easc.ch>
+
+	* rtems/score/cpu.h: Modifiy inline assembly language
+	constraints to use a data register as the CTL/STI
+	instructions requires. This is not only more correct,
+	it avoids GCC PR31787.
+
 2007-05-24	Alain Schaefer <alani@easc.ch>
 
 	* rtems/score/cpu.h: Fix incorrect interrupt mask.
diff --git a/cpukit/score/cpu/bfin/rtems/score/cpu.h b/cpukit/score/cpu/bfin/rtems/score/cpu.h
index db3ff20617..0d4bbeb5b7 100644
--- a/cpukit/score/cpu/bfin/rtems/score/cpu.h
+++ b/cpukit/score/cpu/bfin/rtems/score/cpu.h
@@ -846,8 +846,8 @@ SCORE_EXTERN void           (*_CPU_Thread_dispatch_pointer)();
  */
 #define _CPU_ISR_Disable( _level ) \
   {                                     \
-    asm volatile ("cli %0 \n"           \
-                   : "=r" (_level) );   \
+       asm volatile ("cli %0 \n"       \
+                : "=d" (_level) );     \
                                         \
   }
   
@@ -865,9 +865,9 @@ SCORE_EXTERN void           (*_CPU_Thread_dispatch_pointer)();
  *  XXX document implementation including references if appropriate
  */
 #define _CPU_ISR_Enable( _level )  \
-  {                                   \
-    asm volatile ("STI %0"            \
-                   : : "r" (_level) );  \
+  {                                    \
+    asm volatile ("STI %0 \n"                  \
+                   : : "d" (_level) );         \
   }
 
 /**