RTOS/rtems
1
0
Fork 0
forked from Imagelibrary/rtems
Code Pull Requests Activity

2007-05-31 Alain Schaefer <alani@easc.ch>

Browse Source 
* rtems/score/cpu.h: Modifiy inline assembly language
	constraints to use a data register as the CTL/STI
	instructions requires. This is not only more correct,
	it avoids GCC PR31787.
This commit is contained in:
Joel Sherrill
2007-05-31 16:55:37 +00:00
parent a607c87225
commit 008171099d
2 changed files with 12 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
cpukit/score/cpu/bfin/ChangeLog
View File

@@ -1,3 +1,10 @@
2007-05-31 Alain Schaefer <alani@easc.ch>
* rtems/score/cpu.h: Modifiy inline assembly language
constraints to use a data register as the CTL/STI
instructions requires. This is not only more correct,
it avoids GCC PR31787.
2007-05-24 Alain Schaefer <alani@easc.ch>
* rtems/score/cpu.h: Fix incorrect interrupt mask.

10
cpukit/score/cpu/bfin/rtems/score/cpu.h
View File

@@ -846,8 +846,8 @@ SCORE_EXTERN void (*_CPU_Thread_dispatch_pointer)();
*/
#define _CPU_ISR_Disable( _level ) \
{ \
asm volatile ("cli %0 \n" \
: "=r" (_level) ); \
asm volatile ("cli %0 \n" \
: "=d" (_level) ); \
\
}
@@ -865,9 +865,9 @@ SCORE_EXTERN void (*_CPU_Thread_dispatch_pointer)();
* XXX document implementation including references if appropriate
*/
#define _CPU_ISR_Enable( _level ) \
{ \
asm volatile ("STI %0" \
: : "r" (_level) ); \
{ \
asm volatile ("STI %0 \n" \
: : "d" (_level) ); \
}
/**