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manual: Reorg riscv32/64 hardware objects

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This drops subsection for riscv so that subsections for rv32/64
belong to same level as those of x86 and arm32/64.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
This commit is contained in:
Yanfeng Liu
2026-05-04 16:21:29 +08:00
committed by Gerwin Klein
parent 744104654d
commit a0b4f2d25d
1 changed files with 4 additions and 5 deletions
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9
manual/parts/vspace.tex
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@@ -125,13 +125,10 @@ under a generic name. The table below shows the four-level configuration.
\bottomrule
\end{tabularx}
\subsection{RISC-V}
RISC-V provides the same paging structure for all levels, \obj{PageTable}. This means the VSpace
object is here also implemented by the \obj{PageTable} object.
\subsubsection{RISC-V 32-bit}
On RISC-V, all levels use the same structure. This means VSpace is a \obj{PageTable} object.
32-bit RISC-V \obj{PageTables} are indexed by 10 bits of virtual address.
\begin{tabularx}{\textwidth}{Xlll} \toprule
@@ -143,6 +140,8 @@ object is here also implemented by the \obj{PageTable} object.
\subsubsection{RISC-V 64-bit}
On RISC-V, all levels use the same structure. This means VSpace is a \obj{PageTable} object.
64-bit RISC-V follows the SV39 model, where \obj{PageTables} are indexed by 9 bits of virtual address.
Although RISC-V allows
for multiple different numbers of paging levels, currently seL4 only supports exactly three levels