x86/vcpu: expose VMX-preemption timer scale MSR

Currently, the kernel permits userspace VMMs to enable and use the
VMX-preemption timer by allowing writes to the following VMCS fields:
- VMX_GUEST_PREEMPTION_TIMER_VALUE (count)
- VMX_CONTROL_PIN_EXECUTION_CONTROLS (timer enable bit)
- VMX_CONTROL_EXIT_CONTROLS (save current count on context switch bit)

It also forwards the timer expiry event as a VM exit.

But it does not tell userspace how fast the timer will count down,
making it impossible to use. This commit exposes the timer's scale
via `seL4_X86_VCPU_ReadMSR`.

Signed-off-by: Bill Nguyen <bill.nguyen@unsw.edu.au>

include/arch/x86/arch/machine.h

@@ -38,6 +38,7 @@
 #define IA32_VMX_PROCBASED_CTLS2_MSR 0x48B
 #define IA32_VMX_EXIT_CTLS_MSR  0x483
 #define IA32_VMX_ENTRY_CTLS_MSR 0x484
+#define IA32_VMX_MISC_MSR 0x485
 #define IA32_VMX_TRUE_PINBASED_CTLS_MSR 0x48D
 #define IA32_VMX_TRUE_PROCBASED_CTLS_MSR 0x48E
 #define IA32_VMX_TRUE_EXIT_CTLS_MSR 0x48F

src/arch/x86/object/vcpu.c

@@ -666,6 +666,9 @@ static exception_t invokeReadMSR(vcpu_t *vcpu, word_t field, word_t *buffer)
     case IA32_FMASK_MSR:
         value = vcpu->syscall_registers[VCPU_SYSCALL_MASK];
         break;
+    case IA32_VMX_MISC_MSR:
+        value = x86_rdmsr(field);
+        break;
     }
 
     setMR(thread, buffer, 0, value);
@@ -688,6 +691,7 @@ static exception_t decodeVCPUReadMSR(cap_t cap, word_t length, word_t *buffer)
     case IA32_STAR_MSR:
     case IA32_CSTAR_MSR:
     case IA32_FMASK_MSR:
+    case IA32_VMX_MISC_MSR:
         break;
     default:
         userError("VCPU ReadMSR: Invalid field %lx.", (long)field);