Imagelibrary/rtems
1
0
Fork 1
mirror of https://gitlab.rtems.org/rtems/rtos/rtems.git synced 2025-12-28 15:30:17 +00:00
Code Issues Packages Projects Releases Wiki Activity
36,744 Commits 7 Branches 55 Tags
f80cee565baa89cb65ac85f56226582925bf2bbf
Commit Graph

36744 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Kinsey Moore
f80cee565b spec/libtests: Exclude Thumb-only BSPs from building dl13 
This test requires ARM instruction support and causes build failures on
Thumb-only BSPs.
 2024-10-03 02:03:09 +00:00
Sebastian Huber
410436b800 arm/xilinx-zynqmp-rpu: Use UART 0 by default 
This simplifies the setup for sequential test runs of the APU and RPU
BSPs.
 2024-10-02 05:36:00 +02:00
Sebastian Huber
9624b31408 arm/xilinx-zynqmp-rpu: Implement bsp_reset() 2024-10-02 05:36:00 +02:00
Sebastian Huber
95649a0aca arm/xilinx-zynqmp-rpu: Add section for the OCM 2024-10-02 05:36:00 +02:00
Sebastian Huber
75062c2dbf arm/xilinx-zynqmp-rpu: Simplify MPU configuration 
Use the PMSAv7 support from <rtems/score/armv7-pmsa.h> instead of the
one from the Xilinx support.
 2024-10-02 05:36:00 +02:00
Sebastian Huber
dddbdf4d9a arm/xilinx-zynqmp-rpu: Add split mode BSP variants 
Rename xilinx_zynqmp_rpu BSP variant to zynqmp_rpu_lock_step to
emphasize that this BSP is for the lock-step mode RPU configuration.
Add BSP variants zynqmp_rpu_split_0 and zynqmp_rpu_split_1 for the split
mode RPU configuration for core 0 and 1 respectively.
 2024-10-02 05:35:47 +02:00
Sebastian Huber
5f1a9d3346 arm/xilinx-zynqmp-rpu: Simplify startup 
There is no need to copy sections since the linker command file has no separate
runtime and load regions for the sections.
 2024-10-02 05:24:30 +02:00
Sebastian Huber
1b2ebe1516 arm/xilinx-zynqmp-rpu: Remove superfluous defines 2024-10-02 05:24:30 +02:00
Sebastian Huber
08f27b35aa arm/xilinx-zynqmp-rpu: Remove superfluous option 2024-10-02 05:24:30 +02:00
Sebastian Huber
a78d31de7f arm/xilinx-zynqmp-rpu: Fix file header and copyrights 
Remove copyright from DornerWorks since the files contain not contributions
from this company.  Fix the copyright years of the embedded brains
contributions.
 2024-10-02 05:24:30 +02:00
Sebastian Huber
c91b26ef76 arm/xilinx-zynqmp-rpu: Add cache manager support 2024-10-02 05:24:30 +02:00
Sebastian Huber
4515a7b593 arm/xilinx-zynqmp-rpu: Remove superfluous object 2024-10-02 05:24:30 +02:00
Sebastian Huber
7d9914b90e arm/xilinx-zynqmp-rpu: Use -O2 2024-10-02 05:24:30 +02:00
Sebastian Huber
c4a5dfeb5d arm/xilinx-zynqmp-rpu: Include standard header 2024-10-02 05:24:30 +02:00
Sebastian Huber
ddef4ed1b0 dev/irq: Conditionally enable GIC get/set group 2024-10-02 05:24:30 +02:00
Sebastian Huber
a947bba9df dev/irq: Add BSP_IRQ_HAVE_GET_SET_AFFINITY 
Allow BSPs to provide the interrupt get/set affinity implementation even for
non-SMP configurations.
 2024-10-02 05:24:30 +02:00
Sebastian Huber
2c2f9a1451 dev/irq: Add BSP_ARM_GIC_MULTI_PROCESSOR_SECONDARY 
Add support for the BSP_ARM_GIC_MULTI_PROCESSOR_SECONDARY build option
for the GICv2 support.  This option is useful for multiprocessor systems
without SMP support.
 2024-10-02 05:24:30 +02:00
Sebastian Huber
54c64352d5 bsps/arm: Add files to Doxygen group 2024-10-02 05:24:30 +02:00
Sebastian Huber
8c497f2693 bsps/shared/xil: Add files to Doxygen group 2024-10-02 05:24:30 +02:00
Sebastian Huber
559d90bb10 arm: Improve CPU_Exception_frame 
Add a registers member to allow an indexed access to the registers.
 2024-10-02 05:24:30 +02:00
Sebastian Huber
11b772c867 arm: Add support for PMSAv7 2024-10-02 05:24:30 +02:00
Sebastian Huber
9a5f00965b arm: Install missing header files 2024-10-02 05:24:30 +02:00
Sebastian Huber
5cc08c8f4c build: Add "set-value-enabled-by" build option action 2024-10-02 05:24:30 +02:00
Sebastian Huber
344526b3e4 build: Add "comment" build option action 2024-10-02 05:24:30 +02:00
Sebastian Huber
4ca49fc200 score: Remove _Per_CPU_State_wait_for_non_initial_state() 
This function is unused.
 2024-09-29 23:13:32 +00:00
Sebastian Huber
e2be5ac899 bsps/arm: Allow parallel start of processors 
Do not wait in the individual _CPU_SMP_Start_processor() for the
secondary processor.  Wait for all of them in
_CPU_SMP_Finalize_initialization() before the L2 cache is enabled.
 2024-09-29 23:13:32 +00:00
Sebastian Huber
276d2efb37 bsp/raspberrypi: Simplify SMP support 
There is no need to wait for the secondary processor in
_CPU_SMP_Start_processor() since _CPU_SMP_Finalize_initialization() does
nothing.

The caller of _CPU_SMP_Start_processor() ensures that we do not start
the current processor.
 2024-09-29 23:13:32 +00:00
Sebastian Huber
bbc87a471d bsps/aarch64: Simplify SMP support 
Remove copy and paste from the arm SMP support.  The shared aarch64
implementation of rtems_cache_enable_data() does not enable a particular
cache, it just enables the C bit in the SCTLR_EL1.  This is already done
in aarch64_mmu_enable().  There is no need to wait for secondary
processors in _CPU_SMP_Start_processor().
 2024-09-29 23:13:32 +00:00
Sebastian Huber
b0a688e69c bsps: Simplify _CPU_SMP_Finalize_initialization() 
The processor count is always positive.
 2024-09-29 23:13:32 +00:00
Sebastian Huber
d8822514e7 score: Add _SMP_Wait_for_ready_to_start_multitasking() 2024-09-29 23:13:32 +00:00
Sebastian Huber
296d7150f0 score: Set boot CPU properties before others 
This allows other CPUs to figure out the boot CPU.
 2024-09-29 23:13:32 +00:00
Sebastian Huber
7bd4725942 score: Use _Per_CPU_Get() 
The _Per_CPU_Get() may be more efficient if
_CPU_Get_current_per_CPU_control() is available.
 2024-09-29 23:13:32 +00:00
Alex White
38bafce42d Add aarch64 cpukit paravirtualization support 2024-09-27 20:01:34 +00:00
alessandronardin
653dbdcdbf posix/aio_misc.c: Added returns on error path in rtems_aio_init() 
Coverity CID 1619695

Added returns on error path in rtems_aio_init().
Without them the code could access uninitialized memory.

Closes #5132.
 2024-09-26 19:09:35 +02:00
alessandronardin
617808b979 posix/aio_misc.c/aio_init(): lock before accessing data 
Coverity CID 1592924

added lock before accessing data.

Closes #5129.
 2024-09-25 17:48:11 +00:00
alessandronardin
de196e0586 posix/aio_misc.c: changed malloc call into calloc 
Coverity CID 1512510

Changed a call to malloc() into a call to calloc()
to avoid access to uninitialized memory.

Closes #5131.
 2024-09-25 17:47:28 +00:00
Kinsey Moore
9eb23924e8 testsuites/sptree01: Fix missing prototype warning 2024-09-25 11:55:40 +00:00
Kinsey Moore
81930e2638 testsuites: Add dl13 test for Thumb to ARM transitions 2024-09-24 20:57:56 -05:00
Kinsey Moore
8f8d0c806b cpukit/libdl/arm: Add support for trailing Thumb to ARM calls 
This expands the size of an ARM trampoline from 8 bytes to 10 bytes to
support THM_JUMP24 tail calls that require a BX instruction to change
modes.
 2024-09-24 19:57:08 -05:00
Kinsey Moore
701e8b2d63 cpukit/libdl/arm: Obey instruction encoding requirements for Thumb BLX 
Calls from Thumb code into ARM code require the use of a BLX instruction
and an optional offset prefix instruction. The BLX instruction encoding
requires that the least significant bit be 0 in all cases while the BL
instruction for Thumb-to-Thumb calls includes that bit as part of the
offset. This ensures that bit 0 of the BLX is set to 0 as required by
the instruction encoding specification.
 2024-09-24 19:57:08 -05:00
Gedare Bloom
7cda579524 spec/build: make minimum sample norun 2024-09-24 14:53:02 -06:00
Sebastian Huber
6003ea9d94 aarch64: Add _AArch64_Get_current_processor_for_system_start() 
This allows BSPs to customize how the current processor index is
determined during system start.

Update #5064.
 2024-09-20 06:17:09 +02:00
Sebastian Huber
c311068a9e smpfatal08: Fix build for aarch64 
Update #5064.
 2024-09-20 06:17:09 +02:00
Kinsey Moore
3ec16d5f9d spec/aarch64: Add missing symbols to ILP32 linker script 2024-09-20 04:10:11 +00:00
zhengxiaojun
5e5214b786 bsp/aarch64:Fix _CPU_SMP_Get_current_processor() 
Fix _CPU_SMP_Get_current_processor(), since read from register MPIDR_EL1
(the least significant byte) is not always right,for example the least
significant byte of MPIDR_EL1 is always zero for cortex-a55.

aarch64 has a thread ID register TPIDR_EL1 available for for OS management
purposes. RTEMS stores per-CPU control in TPIDR_EL1 when the core startup,
so we can use _Per_CPU_Get_index() to get current processor index.

update #5064
 2024-09-19 19:15:10 +08:00
Ning Yang
1b5cd007e7 spec: Refactor arm-pl011 build options 
Close #5026
 2024-09-19 05:42:16 +00:00
Sebastian Huber
6482c5cc56 bsps/arm: Fix BSP_START_VECTOR_RESERVED_SLOT 
The option value is a string.
 2024-09-19 04:57:35 +02:00
Sebastian Huber
2aa921c3be validation: Fix synchronization issue 2024-09-19 04:35:20 +02:00
Sebastian Huber
518d27fa75 libtest: Fix format specifier 
This fixes a ttest01 failure.
 2024-09-19 04:34:55 +02:00
Sebastian Huber
1119981e7c tests: Enable ISR in fatal extensions 
Fix code locations left over by commit
3332e54772.

Update #5067.
 2024-09-19 04:34:38 +02:00