mirror of
https://gitlab.rtems.org/rtems/rtos/rtems.git
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arm: Add support for PMSAv7
This commit is contained in:
Sebastian Huber
367
cpukit/score/cpu/arm/include/rtems/score/armv7-pmsa.h
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367
cpukit/score/cpu/arm/include/rtems/score/armv7-pmsa.h
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@@ -0,0 +1,367 @@
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/* SPDX-License-Identifier: BSD-2-Clause */
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/**
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* @file
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*
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* @ingroup RTEMSScoreCPUARMPMSAv7
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*
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* @brief This header file provides the API to manage an Arm PMSAv7 based
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* Memory Protection Unit (MPU).
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*/
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/*
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* Copyright (C) 2024 embedded brains GmbH & Co. KG
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _RTEMS_SCORE_ARMV7_PMSA_H
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#define _RTEMS_SCORE_ARMV7_PMSA_H
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#include <rtems/score/cpu.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*
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* Allow users of this header file to optionally place the inline functions
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* into a non-standard section.
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*/
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#ifndef ARMV7_PMSA_TEXT_SECTION
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#define ARMV7_PMSA_TEXT_SECTION
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#endif
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/**
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* @defgroup RTEMSScoreCPUARMPMSAv7 PMSAv7 Support
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*
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* @ingroup RTEMSScoreCPUARM
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*
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* @brief This group provides support functions to manage an Arm PMSAv7
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* (Protected Memory System Architecture) based Memory Protection Unit (MPU).
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*
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* @{
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*/
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/* RGNR, MPU Region Number Register */
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#define ARMV7_RGNR_REGION_SHIFT 0
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#define ARMV7_RGNR_REGION_MASK 0xffU
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#define ARMV7_RGNR_REGION_GET(_reg) \
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(((_reg)&ARMV7_RGNR_REGION_MASK) >> ARMV7_RGNR_REGION_SHIFT)
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#define ARMV7_RGNR_REGION_SET(_reg, _val) \
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(((_reg) & ~ARMV7_RGNR_REGION_MASK) | \
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(((_val) << ARMV7_RGNR_REGION_SHIFT) & ARMV7_RGNR_REGION_MASK))
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#define ARMV7_RGNR_REGION(_val) \
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(((_val) << ARMV7_RGNR_REGION_SHIFT) & ARMV7_RGNR_REGION_MASK)
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static inline uint32_t _ARMV7_Read_rgnr(void) {
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uint32_t value;
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__asm__ volatile("mrc p15, 0, %0, c6, c2, 0" : "=&r"(value) : : "memory");
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return value;
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}
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static inline void _ARMV7_Write_rgnr(uint32_t value) {
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__asm__ volatile("mcr p15, 0, %0, c6, c2, 0" : : "r"(value) : "memory");
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}
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/* DRBAR, Data Region Base Address Register */
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static inline uint32_t _ARMV7_Read_drbar(void) {
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uint32_t value;
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__asm__ volatile("mrc p15, 0, %0, c6, c1, 0" : "=&r"(value) : : "memory");
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return value;
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}
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static inline void _ARMV7_Write_drbar(uint32_t value) {
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__asm__ volatile("mcr p15, 0, %0, c6, c1, 0" : : "r"(value) : "memory");
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}
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/* IRBAR, Instruction Region Base Address Register */
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static inline uint32_t _ARMV7_Read_irbar(void) {
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uint32_t value;
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__asm__ volatile("mrc p15, 0, %0, c6, c1, 1" : "=&r"(value) : : "memory");
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return value;
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}
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static inline void _ARMV7_Write_irbar(uint32_t value) {
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__asm__ volatile("mcr p15, 0, %0, c6, c1, 1" : : "r"(value) : "memory");
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}
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#define ARMV7_RSR_EN 0x1U
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#define ARMV7_RSR_RSIZE_SHIFT 1
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#define ARMV7_RSR_RSIZE_MASK 0x3eU
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#define ARMV7_RSR_RSIZE_GET(_reg) \
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(((_reg)&ARMV7_RSR_RSIZE_MASK) >> ARMV7_RSR_RSIZE_SHIFT)
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#define ARMV7_RSR_RSIZE_SET(_reg, _val) \
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(((_reg) & ~ARMV7_RSR_RSIZE_MASK) | \
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(((_val) << ARMV7_RSR_RSIZE_SHIFT) & ARMV7_RSR_RSIZE_MASK))
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#define ARMV7_RSR_RSIZE(_val) \
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(((_val) << ARMV7_RSR_RSIZE_SHIFT) & ARMV7_RSR_RSIZE_MASK)
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#define ARMV7_RSR_SD_SHIFT 8
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#define ARMV7_RSR_SD_MASK 0xff00U
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#define ARMV7_RSR_SD_GET(_reg) \
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(((_reg)&ARMV7_RSR_SD_MASK) >> ARMV7_RSR_SD_SHIFT)
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#define ARMV7_RSR_SD_SET(_reg, _val) \
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(((_reg) & ~ARMV7_RSR_SD_MASK) | \
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(((_val) << ARMV7_RSR_SD_SHIFT) & ARMV7_RSR_SD_MASK))
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#define ARMV7_RSR_SD(_val) (((_val) << ARMV7_RSR_SD_SHIFT) & ARMV7_RSR_SD_MASK)
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/* DRSR, Data Region Size and Enable Register */
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static inline uint32_t _ARMV7_Read_drsr(void) {
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uint32_t value;
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__asm__ volatile("mrc p15, 0, %0, c6, c1, 2" : "=&r"(value) : : "memory");
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return value;
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}
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static inline void _ARMV7_Write_drsr(uint32_t value) {
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__asm__ volatile("mcr p15, 0, %0, c6, c1, 2" : : "r"(value) : "memory");
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}
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/* IRSR, Instruction Region Size and Enable Register */
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static inline uint32_t _ARMV7_Read_irsr(void) {
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uint32_t value;
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__asm__ volatile("mrc p15, 0, %0, c6, c1, 3" : "=&r"(value) : : "memory");
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return value;
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}
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static inline void _ARMV7_Write_irsr(uint32_t value) {
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__asm__ volatile("mcr p15, 0, %0, c6, c1, 3" : : "r"(value) : "memory");
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}
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#define ARMV7_RACR_B 0x1U
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#define ARMV7_RACR_C 0x2U
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#define ARMV7_RACR_S 0x4U
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#define ARMV7_RACR_TEX_0 0x8U
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#define ARMV7_RACR_TEX_1 0x10U
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#define ARMV7_RACR_TEX_2 0x20U
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#define ARMV7_RACR_AP_0 0x100U
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#define ARMV7_RACR_AP_1 0x200U
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#define ARMV7_RACR_AP_2 0x400U
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#define ARMV7_RACR_XN 0x1000U
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/* DRACR, Data Region Access Control Register */
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static inline uint32_t _ARMV7_Read_dracr(void) {
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uint32_t value;
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__asm__ volatile("mrc p15, 0, %0, c6, c1, 4" : "=&r"(value) : : "memory");
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return value;
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}
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static inline void _ARMV7_Write_dracr(uint32_t value) {
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__asm__ volatile("mcr p15, 0, %0, c6, c1, 4" : : "r"(value) : "memory");
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}
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/* IRACR, Instruction Region Access Control Register */
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static inline uint32_t _ARMV7_Read_iracr(void) {
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uint32_t value;
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__asm__ volatile("mrc p15, 0, %0, c6, c1, 5" : "=&r"(value) : : "memory");
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return value;
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}
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static inline void _ARMV7_Write_iracr(uint32_t value) {
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__asm__ volatile("mcr p15, 0, %0, c6, c1, 5" : : "r"(value) : "memory");
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}
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#define ARMV7_PMSA_READ_ONLY_CACHED \
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(ARMV7_RACR_TEX_0 | ARMV7_RACR_C | ARMV7_RACR_B | ARMV7_RACR_AP_0 | \
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ARMV7_RACR_AP_2)
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#define ARMV7_PMSA_READ_ONLY_UNCACHED \
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(ARMV7_RACR_TEX_0 | ARMV7_RACR_AP_0 | ARMV7_RACR_AP_2)
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#define ARMV7_PMSA_READ_WRITE_CACHED \
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(ARMV7_RACR_TEX_0 | ARMV7_RACR_C | ARMV7_RACR_B | ARMV7_RACR_AP_0)
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#define ARMV7_PMSA_READ_WRITE_UNCACHED (ARMV7_RACR_TEX_0 | ARMV7_RACR_AP_0)
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#define ARMV7_PMSA_READ_WRITE_SHARED \
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(ARMV7_RACR_TEX_0 | ARMV7_RACR_S | ARMV7_RACR_AP_0)
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#define ARMV7_PMSA_SHAREABLE_DEVICE (ARMV7_RACR_B | ARMV7_RACR_AP_0)
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#define ARMV7_PMSA_NON_SHAREABLE_DEVICE (ARMV7_RACR_TEX_1 | ARMV7_RACR_AP_0)
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/**
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* @brief The region definition is used to initialize the Memory Protection
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* Unit (MPU).
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*
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* A region is empty if the size is zero.
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*/
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typedef struct ARMV7_PMSA_Region {
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/**
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* @brief This member defines the begin address of the region.
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*/
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uint32_t begin;
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/**
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* @brief This member defines the size in bytes of the region.
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*/
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uint32_t size;
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/**
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* @brief This member defines the attributes of the region.
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*/
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uint32_t attributes;
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} ARMV7_PMSA_Region;
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ARMV7_PMSA_TEXT_SECTION static inline uint32_t _ARMV7_PMSA_Power2(uint32_t x) {
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return 32 - __builtin_clz(x - 1U);
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}
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ARMV7_PMSA_TEXT_SECTION static inline uint32_t _ARMV7_PMSA_Ceil2(uint32_t x) {
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return 1U << _ARMV7_PMSA_Power2(x);
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}
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ARMV7_PMSA_TEXT_SECTION static inline uint32_t _ARMV7_PMSA_Down2(uint32_t x,
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uint32_t y) {
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uint32_t m = y - 1U;
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return x & ~m;
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}
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ARMV7_PMSA_TEXT_SECTION static inline uint32_t _ARMV7_PMSA_Up2(uint32_t x,
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uint32_t y) {
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uint32_t m = y - 1U;
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return (x + m) & ~m;
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}
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ARMV7_PMSA_TEXT_SECTION static inline uint32_t
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_ARMV7_PMSA_Get_region(uint32_t b, uint32_t s, uint32_t* rs) {
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uint32_t e = b + s;
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uint32_t s2 = _ARMV7_PMSA_Ceil2(s);
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uint32_t b2 = _ARMV7_PMSA_Down2(b, s2);
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uint32_t e2 = _ARMV7_PMSA_Up2(e, s2);
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uint32_t s3 = _ARMV7_PMSA_Ceil2(e2 - b2);
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*rs = s3;
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return _ARMV7_PMSA_Down2(b2, s3);
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}
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ARMV7_PMSA_TEXT_SECTION static inline void _ARMV7_PMSA_Write_region(
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uint32_t index,
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uint32_t b,
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uint32_t s,
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uint32_t rb,
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uint32_t rs,
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uint32_t attr) {
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int rp = _ARMV7_PMSA_Power2(rs);
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int shift = rp - 3;
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uint32_t u = (b - rb) >> shift;
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uint32_t v = (_ARMV7_PMSA_Up2(b + s, 1U << shift) - rb) >> shift;
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uint32_t sub = ((0xffU >> (8 - v)) >> u) << u;
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_ARMV7_Write_rgnr(ARMV7_RGNR_REGION(index));
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_ARM_Instruction_synchronization_barrier();
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_ARMV7_Write_drbar(rb);
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_ARMV7_Write_dracr(attr);
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_ARMV7_Write_drsr(ARMV7_RSR_SD(~sub) | ARMV7_RSR_RSIZE(rp - 1) |
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ARMV7_RSR_EN);
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_ARM_Data_synchronization_barrier();
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_ARM_Instruction_synchronization_barrier();
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}
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ARMV7_PMSA_TEXT_SECTION static inline uint32_t
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_ARMV7_PMSA_Add_regions(uint32_t index, uint32_t b, uint32_t s, uint32_t attr) {
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uint32_t rs;
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uint32_t rb = _ARMV7_PMSA_Get_region(b, s, &rs);
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uint32_t e = b + s;
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if (e - rb > rs) {
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uint32_t re = rb + rs;
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uint32_t bl = b;
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uint32_t sl = re - b;
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rb = _ARMV7_PMSA_Get_region(bl, sl, &rs);
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_ARMV7_PMSA_Write_region(index, bl, sl, rb, rs, attr);
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++index;
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s = e - re;
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b = re;
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rb = _ARMV7_PMSA_Get_region(b, s, &rs);
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}
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_ARMV7_PMSA_Write_region(index, b, s, rb, rs, attr);
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return index + 1;
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}
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ARMV7_PMSA_TEXT_SECTION static inline uint32_t _ARMV7_PMSA_Find_region(
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uintptr_t address,
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uint32_t index) {
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uint32_t region_count = _ARMV7_Read_rgnr();
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while (index < region_count) {
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_ARMV7_Write_rgnr(ARMV7_RGNR_REGION(index));
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_ARM_Instruction_synchronization_barrier();
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uint32_t rsr = _ARMV7_Read_drsr();
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if ((rsr & ARMV7_RSR_EN) != 0) {
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uint32_t rbar = _ARMV7_Read_drbar();
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uint32_t offset = (address & ~UINT32_C(0x3)) - rbar;
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uint32_t region_power = ARMV7_RSR_RSIZE_GET(rsr) + 1;
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uint32_t region_size = UINT32_C(1) << region_power;
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if (offset < region_size) {
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if (region_size < 256) {
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return index;
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}
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uint32_t sub = offset >> (region_power - 3);
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if ((ARMV7_RSR_SD_GET(rsr) & (UINT32_C(1) << sub)) == 0) {
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return index;
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}
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}
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}
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++index;
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}
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return UINT32_MAX;
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}
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* _RTEMS_SCORE_ARMV7_PMSA_H */
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@@ -25,6 +25,7 @@ install:
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- cpukit/score/cpu/arm/include/rtems/score/arm.h
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- cpukit/score/cpu/arm/include/rtems/score/armv4.h
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- cpukit/score/cpu/arm/include/rtems/score/armv7m.h
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- cpukit/score/cpu/arm/include/rtems/score/armv7-pmsa.h
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- cpukit/score/cpu/arm/include/rtems/score/cpu.h
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- cpukit/score/cpu/arm/include/rtems/score/cpu_asm.h
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- cpukit/score/cpu/arm/include/rtems/score/cpuimpl.h
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