This refactors the AArch64 exception handling to remove the mutable code
sections that are generally flagged as a bad idea by code analysis
tools. This also removes any casting between data pointers and function
pointers to avoid the need to use pragmas to disable warnings about such
casting.
This adds support for a the Image header protocol similar to the zImage
protocol that Linux kernels use to describe their expectations of the
system configuration.
The AArch64-specific timer selection mechanism was using the wrong macro
for selecting the timer interrupt and would therefore partially ignore
configurations that selected the use of virtual timers. The virtual
timer will now be used correctly when selected.
The functions lpc24xx_uart_set_register() and
lpc24xx_uart_set_register() were unused if all of the
feature macros LPC24XX_CONFIG_CONSOLE and LPC24XX_CONFIG_UART_[123]
were undefined.
lpc32xx_mlc_write_blocks() had a different prototype in the header
from the implementation. Changed to match the prototype and Doxygen.
LPC32XX_SCRATCH_AREA_SIZE was tested with "ifdef" not "if" which
resulted in it being used as an array size when undefined or
set to 0.
This header file defines multiple empty structures which are
reported as errors by the test spstdc17 using GCC 15. Added an element
named "unused" to each structure. The macro LPC32XX_FILL() was
checked to ensure it handles the modified structure correctly.
Closes#5295.
Removed all uses and implementations of set_vector() function across ERC32,
LEON2, and LEON3 BSPs. Replaced with rtems_interrupt_handler_install() and
rtems_interrupt_entry_install().
- Added ERC32_Clear_and_unmask_interrupt() and LEON_Clear_and_unmask_interrupt()
for unmasking logic previously in set_vector().
- Deleted set_vector() definitions and implementations in each BSP.
- Updated related obj.yml files.
- Replaced set_vector() with rtems_interrupt_catch() in shared/gnatcommon.c.
The list formerly included the erc32 and pc386 varants which do not
support multi-core. Added the pc386 variants which include the
support necessary for multi-core.
This BSP supports a custom STM32U5 based board. It uses a similar
structure like the existing STM32H7 BSP and therefore should be well
adaptable to other boards.
Co-authored-by: Christian Mauderer <christian.mauderer@embedded-brains.de>
Some fixes where necessary to not handle ARMv8M identical to (for
example) ARMv8A. ARMv8M is more similar to ARMv7M.
Co-authored-by: Christian Mauderer <christian.mauderer@embedded-brains.de>
Include armv7m_cachel1.h in core_cm33.h file to allow access to
cache functions.
Co-authored-by: Christian Mauderer <christian.mauderer@embedded-brains.de>
Files are imported from https://github.com/ARM-software/CMSIS_5 revision
55b19837f5703e418ca37894d5745b1dc05e4c91
Like already checked in RTEMS commit
6b2318acef, the project still don't have a
NOTICE file.
If the Double Trap Extension is implemented, the
MDT bit of the mstatus (or mstatush in RV32)
register will be set when a trap is to be taken.
The MIE (Machine Interrupt Enable) bit can only
be set to 1 if the MDT bit is zero.
Thus, we need to clear MDT first if we want to
enable interrupts when dispatching a thread.
MDT is also cleared in register a1 before
restoring the interrupt frame as writing 1 to MDT
will cause MIE to be set to 0. In RV64 this
happens regardless of the value written to MIE in
the same write.
In RV32, MDT is in the mstatush so we do not need
to clear during restore as this register is not
restored.
With this change all 60 SMP tests pass (compared
to 20/60 before the fix). The tests have been run
on hardware using two RV64 CPUs that implement
the double trap extension.
Update #5274
- Modified the psximfs01 test to validate the functionality
- Modified the IMFS_fs_info_t keeping the jnode counter
- Added imfs_statvfs.c which sets the statvfs struct fields for imfs
Avoid reading from the pl011 data register unnecessarily. There is no
need to preserve the contents of this register as it is not normal
memory. This unnecessary read causes console spam when running under the
Xen hypervisor when the read FIFO is empty since the read is not
expected.
