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bsps/m68k: Fix incorrect register offsets for PIT in mcf5282.h

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PIT register blocks are 64k in size, not 4k.
This commit is contained in:
Jeremy Lorelli
2025-12-24 13:41:07 -08:00
committed by Joel Sherrill
parent c2eb7644ce
commit 2be044fc4e
1 changed files with 3 additions and 3 deletions
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6
bsps/m68k/include/mcf5282/mcf5282.h
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@@ -1824,9 +1824,9 @@ extern uint8 __IPSBAR[];
#define MCF5282_PIT3_PMR (*(vuint16 *)(&__IPSBAR[0x180002]))
#define MCF5282_PIT3_PCNTR (*(vuint16 *)(&__IPSBAR[0x180004]))
#define MCF5282_PIT_PCSR(x) (*(vuint16 *)(&__IPSBAR[0x150000+(0x1000*(x))]))
#define MCF5282_PIT_PMR(x) (*(vuint16 *)(&__IPSBAR[0x150002+(0x1000*(x))]))
#define MCF5282_PIT_PCNTR(x) (*(vuint16 *)(&__IPSBAR[0x150004+(0x1000*(x))]))
#define MCF5282_PIT_PCSR(x) (*(vuint16 *)(&__IPSBAR[0x150000+(0x10000*(x))]))
#define MCF5282_PIT_PMR(x) (*(vuint16 *)(&__IPSBAR[0x150002+(0x10000*(x))]))
#define MCF5282_PIT_PCNTR(x) (*(vuint16 *)(&__IPSBAR[0x150004+(0x10000*(x))]))
/* Bit level definitions and macros */
#define MCF5282_PIT_PCSR_PRE(x) (((x)&0x000F)<<8)