From 2be044fc4e5a9105de0a702cb8c9229628b6e245 Mon Sep 17 00:00:00 2001 From: Jeremy Lorelli Date: Wed, 24 Dec 2025 13:41:07 -0800 Subject: [PATCH] bsps/m68k: Fix incorrect register offsets for PIT in mcf5282.h PIT register blocks are 64k in size, not 4k. --- bsps/m68k/include/mcf5282/mcf5282.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/bsps/m68k/include/mcf5282/mcf5282.h b/bsps/m68k/include/mcf5282/mcf5282.h index 3724f489de..80d61f7d09 100644 --- a/bsps/m68k/include/mcf5282/mcf5282.h +++ b/bsps/m68k/include/mcf5282/mcf5282.h @@ -1824,9 +1824,9 @@ extern uint8 __IPSBAR[]; #define MCF5282_PIT3_PMR (*(vuint16 *)(&__IPSBAR[0x180002])) #define MCF5282_PIT3_PCNTR (*(vuint16 *)(&__IPSBAR[0x180004])) -#define MCF5282_PIT_PCSR(x) (*(vuint16 *)(&__IPSBAR[0x150000+(0x1000*(x))])) -#define MCF5282_PIT_PMR(x) (*(vuint16 *)(&__IPSBAR[0x150002+(0x1000*(x))])) -#define MCF5282_PIT_PCNTR(x) (*(vuint16 *)(&__IPSBAR[0x150004+(0x1000*(x))])) +#define MCF5282_PIT_PCSR(x) (*(vuint16 *)(&__IPSBAR[0x150000+(0x10000*(x))])) +#define MCF5282_PIT_PMR(x) (*(vuint16 *)(&__IPSBAR[0x150002+(0x10000*(x))])) +#define MCF5282_PIT_PCNTR(x) (*(vuint16 *)(&__IPSBAR[0x150004+(0x10000*(x))])) /* Bit level definitions and macros */ #define MCF5282_PIT_PCSR_PRE(x) (((x)&0x000F)<<8)