Imagelibrary/rtems
1
0
Fork 1
mirror of https://gitlab.rtems.org/rtems/rtos/rtems.git synced 2026-02-04 04:31:36 +00:00
Code Issues Packages Projects Releases Wiki Activity

bsps/microblaze: Mask interrupts before enabling MER

Browse Source 
On startup mask off the interrupt register prior to starting interrupts.
Also update the comment to describe the delay slot.
This commit is contained in:
Sam Price
2025-11-23 23:34:57 -05:00
committed by Kinsey Moore
parent 69a9314281
commit 25ab337428
2 changed files with 7 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
bsps/microblaze/microblaze_fpga/irq/irq.c
View File

@@ -159,12 +159,15 @@ void bsp_interrupt_facility_initialize( void )
* Enable HW interrupts on the interrupt controller. This happens before
* interrupts are enabled on the processor.
*/
mblaze_intc = (volatile Microblaze_INTC *) try_get_prop_from_device_tree(
mblaze_intc = (volatile Microblaze_INTC *) try_get_prop_from_device_tree(
"xlnx,xps-intc-1.00.a",
"reg",
BSP_MICROBLAZE_FPGA_INTC_BASE
);
/* Mask off all interrupt sources to prevent spurious interrupts */
mblaze_intc->ier = 0;
mblaze_intc->mer = MICROBLAZE_INTC_MER_ME | MICROBLAZE_INTC_MER_HIE;
}

4
bsps/microblaze/microblaze_fpga/start/_interrupt_handler.S
View File

@@ -62,7 +62,9 @@
mfs r3, rmsr
swi r3, r1, MICROBLAZE_INTERRUPT_FRAME_MSR
/* Indicate unknown interrupt source */
/* Indicate unknown interrupt source; 0xFF tells _ISR_Handler to query the INTC. */
/* Use addik so MSR flags stay unchanged before calling the handler. */
/* braid has a delay slot; addik will occur prior to the branch. */
braid _ISR_Handler
addik r5, r0, 0xFF
#endif /* __rtems__ */