From 25ab3374288156231da884f5601bb7b2181f90b1 Mon Sep 17 00:00:00 2001 From: Sam Price Date: Sun, 23 Nov 2025 23:34:57 -0500 Subject: [PATCH] bsps/microblaze: Mask interrupts before enabling MER On startup mask off the interrupt register prior to starting interrupts. Also update the comment to describe the delay slot. --- bsps/microblaze/microblaze_fpga/irq/irq.c | 5 ++++- bsps/microblaze/microblaze_fpga/start/_interrupt_handler.S | 4 +++- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/bsps/microblaze/microblaze_fpga/irq/irq.c b/bsps/microblaze/microblaze_fpga/irq/irq.c index a57ac0f875..61e472c9d9 100644 --- a/bsps/microblaze/microblaze_fpga/irq/irq.c +++ b/bsps/microblaze/microblaze_fpga/irq/irq.c @@ -159,12 +159,15 @@ void bsp_interrupt_facility_initialize( void ) * Enable HW interrupts on the interrupt controller. This happens before * interrupts are enabled on the processor. */ - mblaze_intc = (volatile Microblaze_INTC *) try_get_prop_from_device_tree( + mblaze_intc = (volatile Microblaze_INTC *) try_get_prop_from_device_tree( "xlnx,xps-intc-1.00.a", "reg", BSP_MICROBLAZE_FPGA_INTC_BASE ); + /* Mask off all interrupt sources to prevent spurious interrupts */ + mblaze_intc->ier = 0; + mblaze_intc->mer = MICROBLAZE_INTC_MER_ME | MICROBLAZE_INTC_MER_HIE; } diff --git a/bsps/microblaze/microblaze_fpga/start/_interrupt_handler.S b/bsps/microblaze/microblaze_fpga/start/_interrupt_handler.S index eda8f5c01a..710d4cd48f 100644 --- a/bsps/microblaze/microblaze_fpga/start/_interrupt_handler.S +++ b/bsps/microblaze/microblaze_fpga/start/_interrupt_handler.S @@ -62,7 +62,9 @@ mfs r3, rmsr swi r3, r1, MICROBLAZE_INTERRUPT_FRAME_MSR - /* Indicate unknown interrupt source */ + /* Indicate unknown interrupt source; 0xFF tells _ISR_Handler to query the INTC. */ + /* Use addik so MSR flags stay unchanged before calling the handler. */ + /* braid has a delay slot; addik will occur prior to the branch. */ braid _ISR_Handler addik r5, r0, 0xFF #endif /* __rtems__ */