[HC32] support HC32F472 & remove residual files

.github/workflows/bsp_buildings.yml

@@ -84,6 +84,7 @@ jobs:
                 - "hc32/ev_hc32f4a0_lqfp176"
                 - "hc32/ev_hc32f448_lqfp80"
                 - "hc32/ev_hc32f460_lqfp100_v2"
+                - "hc32/ev_hc32f472_lqfp100"
                 - "hc32l196"
                 - "mm32/mm32f3270-100ask-pitaya"
                 - "mm32f327x"

bsp/hc32/README.md

@@ -10,6 +10,7 @@ HC32 系列 BSP 目前支持情况如下表所示：
 | [ev_hc32f460_lqfp100_v2](ev_hc32f460_lqfp100_v2) | 小华 官方 EV_F460_LQ100_V2 开发板 |
 | [ev_hc32f4a0_lqfp176](ev_hc32f4a0_lqfp176) | 小华 官方 EV_F4A0_LQ176 开发板 |
 | [ev_hc32f448_lqfp80](ev_hc32f448_lqfp80) | 小华 官方 EV_F448_LQ80 开发板 |
+| [ev_hc32f472_lqfp100](ev_hc32f472_lqfp100) | 小华 官方 EV_F472_LQ100 开发板 |
 | **M1 系列** |  |
 | **M4 系列** |  |
 

bsp/hc32/ev_hc32f472_lqfp100/.gitignore

@@ -0,0 +1,42 @@
+*.pyc
+*.map
+*.dblite
+*.elf
+*.bin
+*.hex
+*.axf
+*.exe
+*.pdb
+*.idb
+*.ilk
+*.old
+build
+Debug
+documentation/html
+packages/
+*~
+*.o
+*.obj
+*.out
+*.bak
+*.dep
+*.lib
+*.i
+*.d
+.DS_Stor*
+.config 3
+.config 4
+.config 5
+Midea-X1
+*.uimg
+GPATH
+GRTAGS
+GTAGS
+.vscode
+JLinkLog.txt
+JLinkSettings.ini
+DebugConfig/
+RTE/
+settings/
+*.uvguix*
+cconfig.h

bsp/hc32/ev_hc32f472_lqfp100/Kconfig

@@ -0,0 +1,21 @@
+mainmenu "RT-Thread Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../../.."
+
+config PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+source "../libraries/Kconfig"
+source "board/Kconfig"

bsp/hc32/ev_hc32f472_lqfp100/README.md

@@ -0,0 +1,125 @@
+# XHSC EV_F472_LQ100_Rev1.0 开发板 BSP 说明
+
+## 简介
+
+本文档为小华半导体为 EV_F472_LQ100_Rev1.0 开发板提供的 BSP (板级支持包) 说明。
+
+主要内容如下：
+
+- 开发板资源介绍
+- BSP 快速上手
+- 进阶使用方法
+
+通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。
+
+## 开发板介绍
+
+EV_F472_LQ100_Rev1.0 是 XHSC 官方推出的开发板，搭载 HC32F472PETI 芯片，基于 ARM Cortex-M4 内核，最高主频 120 MHz，具有丰富的板载资源，可以充分发挥 HC32F472PETI 的芯片性能。
+
+开发板外观如下图所示：
+
+ ![board](figures/board.png)
+
+EV_F472_LQ100_Rev1.0 开发板常用 **板载资源** 如下：
+
+- **MCU**
+  - HC32F472PETI
+  - 主频120MHz
+  - 512KB FLASH
+  - 68KB RAM
+- **外部Memory**
+  - BL24C256（EEPROM, 256Kbits）
+  - W25Q64（SPI NOR，64MB）
+  - IS62WV51216（SRAM， 1MB）
+- **常用外设**
+  - LED: 4 个，User LED（LED0，LED1，LED2，LED5）。
+  - 按键: 9 个，矩阵键盘（K1~K9）， WAKEUP（K10），RESET（K0）
+- **常用接口**
+  - USB转串口
+  - CAN DB9接口 * 3
+  - SmartCard接口
+  - I2C/USART/SPI接口
+- **调试接口**
+  - 板载DAP调试器
+  - 标准JTAG/SWD/Trace
+
+开发板更多详细信息请参考小华半导体半导体[EV_F472_LQ100_Rev1.0](https://www.xhsc.com.cn)
+
+## 外设支持
+
+本 BSP 目前对外设的支持情况如下：
+
+| **板载外设**  | **支持情况** |               **备注**                |
+| :------------ | :-----------: | :-----------------------------------: |
+| USB 转串口    |      支持     |          使用 UART2                  |
+| LED           |     支持     |           LED1~4                   |
+
+| **片上外设**  | **支持情况** |               **备注**                |
+| :------------ | :-----------: | :-----------------------------------: |
+| GPIO          |     支持     | PA0, PA1... PF8 ---> PIN: 0, 1...88 |
+| I2C           |     支持     | 软件模拟<br>硬件I2C1~2<br>I2C1支持EEPROM（BL24C256） |
+| SPI           |     支持     | SPI1~3<br>SPI1支持W25Q |
+| QSPI          |     支持     | 支持W25Q |
+| UART          |     支持     |              UART1~6<br>UART2为console使用                 |
+
+
+## 使用说明
+
+使用说明分为如下两个章节：
+
+- 快速上手
+
+    本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。
+
+- 进阶使用
+
+    本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。
+
+
+### 快速上手
+
+本 BSP 为开发者提供 MDK5 和 IAR 工程。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。
+
+#### 硬件连接
+
+使用Type-A to MircoUSB线连接开发板和PC供电。
+
+#### 编译下载
+
+双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。
+
+> 工程默认配置使用板载 DAP 下载程序，点击下载按钮即可下载程序到开发板。
+
+#### 运行结果
+
+下载程序成功之后，系统会自动运行，观察开发板上LED的运行效果，绿色LED5会周期性闪烁。
+
+USB虚拟COM端口默认连接串口2，在终端工具里打开相应的串口，复位设备后，可以看到 RT-Thread 的输出信息:
+
+```
+ \ | /
+- RT -     Thread Operating System
+ / | \     5.0.1 build Feb  4 2024 16:44:26
+ 2006 - 2022 Copyright by RT-Thread team
+msh >
+```
+
+### 进阶使用
+
+此 BSP 默认只开启了 GPIO 和 串口 2 的功能，更多高级功能需要利用 env 工具对 BSP 进行配置，步骤如下：
+
+1. 在 bsp 下打开 env 工具。
+
+2. 输入`menuconfig`命令配置工程，配置好之后保存退出。
+
+3. 输入`pkgs --update`命令更新软件包。
+
+4. 输入`scons --target=mdk5/iar` 命令重新生成工程。
+
+## 注意事项
+无
+## 联系人信息
+
+维护人:
+
+-  [小华半导体MCU](https://www.xhsc.com.cn)，邮箱：<xhsc_mcu@xhsc.com.cn>

bsp/hc32/ev_hc32f472_lqfp100/SConscript

@@ -0,0 +1,15 @@
+# for module compiling
+import os
+Import('RTT_ROOT')
+from building import *
+
+cwd = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')

bsp/hc32/ev_hc32f472_lqfp100/SConstruct

@@ -0,0 +1,64 @@
+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+try:
+    from building import *
+except:
+    print('Cannot found RT-Thread root directory, please check RTT_ROOT')
+    print(RTT_ROOT)
+    exit(-1)
+
+TARGET = 'rtthread.' + rtconfig.TARGET_EXT
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+    AR = rtconfig.AR, ARFLAGS = '-rc',
+    CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
+    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+if rtconfig.PLATFORM in ['iccarm']:
+    env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
+    env.Replace(ARFLAGS = [''])
+    env.Replace(LINKCOM = env["LINKCOM"] + ' --map rtthread.map')
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+SDK_ROOT = os.path.abspath('./')
+
+if os.path.exists(SDK_ROOT + '/libraries'):
+    libraries_path_prefix = SDK_ROOT + '/libraries'
+else:
+    libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
+
+SDK_LIB = libraries_path_prefix
+Export('SDK_LIB')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+hc32_library = 'hc32f472_ddl'
+rtconfig.BSP_LIBRARY_TYPE = hc32_library
+
+# include libraries
+objs.extend(SConscript(os.path.join(libraries_path_prefix, hc32_library, 'SConscript')))
+
+# include drivers
+objs.extend(SConscript(os.path.join(libraries_path_prefix, 'hc32_drivers', 'SConscript')))
+
+# include platform
+platform_path_prefix = os.path.dirname(SDK_ROOT) + '/platform'
+objs.extend(SConscript(os.path.join(platform_path_prefix, 'SConscript')))
+
+# make a building
+DoBuilding(TARGET, objs)

bsp/hc32/ev_hc32f472_lqfp100/applications/SConscript

@@ -0,0 +1,15 @@
+from building import *
+import os
+
+cwd = GetCurrentDir()
+src = Glob('*.c')
+CPPPATH = [cwd]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+list = os.listdir(cwd)
+for item in list:
+    if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
+        group = group + SConscript(os.path.join(item, 'SConscript'))
+
+Return('group')

bsp/hc32/ev_hc32f472_lqfp100/applications/main.c

@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2006-2024, RT-Thread Development Team
+ * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2024-02-20     CDT          first version
+ */
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <board.h>
+
+/* defined the LED_GREEN pin: PC9 */
+#define LED_GREEN_PIN GET_PIN(C, 9)
+
+int main(void)
+{
+    /* set LED_GREEN_PIN pin mode to output */
+    rt_pin_mode(LED_GREEN_PIN, PIN_MODE_OUTPUT);
+
+    while (1)
+    {
+        rt_pin_write(LED_GREEN_PIN, PIN_HIGH);
+        rt_thread_mdelay(500);
+        rt_pin_write(LED_GREEN_PIN, PIN_LOW);
+        rt_thread_mdelay(500);
+    }
+}
+

bsp/hc32/ev_hc32f472_lqfp100/applications/xtal32_fcm.c

@@ -0,0 +1,99 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2024-02-20     CDT          first version
+ */
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <board.h>
+
+#if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM)
+
+#define XTAL32_FCM_THREAD_STACK_SIZE    (1024)
+
+/**
+ * @brief This thread is used to monitor whether XTAL32 is stable.
+ *        This thread only runs once after the system starts.
+ *        When stability is detected or 2s times out, the thread will end.
+ *       (When a timeout occurs it will be prompted via rt_kprintf)
+ */
+void xtal32_fcm_thread_entry(void *parameter)
+{
+    stc_fcm_init_t stcFcmInit;
+    uint32_t u32TimeOut = 0UL;
+    uint32_t u32Time = 200UL; /* 200*10ms = 2s */
+
+    /* FCM config */
+    FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_FCM, ENABLE);
+    (void)FCM_StructInit(&stcFcmInit);
+    stcFcmInit.u32RefClock       = FCM_REF_CLK_MRC;
+    stcFcmInit.u32RefClockDiv    = FCM_REF_CLK_DIV8192; /* ~1ms cycle */
+    stcFcmInit.u32RefClockEdge   = FCM_REF_CLK_RISING;
+    stcFcmInit.u32TargetClock    = FCM_TARGET_CLK_XTAL32;
+    stcFcmInit.u32TargetClockDiv = FCM_TARGET_CLK_DIV1;
+    stcFcmInit.u16LowerLimit     = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 96UL / 100UL);
+    stcFcmInit.u16UpperLimit     = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 104UL / 100UL);
+    (void)FCM_Init(&stcFcmInit);
+    /* Enable FCM, to ensure xtal32 stable */
+    FCM_Cmd(ENABLE);
+
+    while (1)
+    {
+        if (SET == FCM_GetStatus(FCM_FLAG_END))
+        {
+            FCM_ClearStatus(FCM_FLAG_END);
+            if ((SET == FCM_GetStatus(FCM_FLAG_ERR)) || (SET == FCM_GetStatus(FCM_FLAG_OVF)))
+            {
+                FCM_ClearStatus(FCM_FLAG_ERR | FCM_FLAG_OVF);
+            }
+            else
+            {
+                (void)FCM_DeInit();
+                FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_FCM, DISABLE);
+                /* XTAL32 stabled */
+                break;
+            }
+        }
+        u32TimeOut++;
+        if (u32TimeOut > u32Time)
+        {
+            (void)FCM_DeInit();
+            FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_FCM, DISABLE);
+            rt_kprintf("Error: XTAL32 still unstable, timeout.\n");
+            break;
+        }
+        rt_thread_mdelay(10);
+    }
+}
+
+int xtal32_fcm_thread_create(void)
+{
+    rt_thread_t tid;
+
+    tid = rt_thread_create("xtal32_fcm", xtal32_fcm_thread_entry, RT_NULL,
+                           XTAL32_FCM_THREAD_STACK_SIZE, RT_THREAD_PRIORITY_MAX - 2, 10);
+    if (tid != RT_NULL)
+    {
+        rt_thread_startup(tid);
+    }
+    else
+    {
+        rt_kprintf("create xtal32_fcm thread err!");
+    }
+    return RT_EOK;
+}
+INIT_APP_EXPORT(xtal32_fcm_thread_create);
+
+#endif
+
+

bsp/hc32/ev_hc32f472_lqfp100/board/Kconfig

@@ -0,0 +1,671 @@
+menu "Hardware Drivers Config"
+
+config SOC_HC32F472MC
+    bool
+    select SOC_SERIES_HC32F4
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    default y
+
+menu "On-chip Drivers"
+    menuconfig BSP_USING_ON_CHIP_FLASH_CACHE
+        bool "Enable on-chip Flash Cache"
+        default y
+        if BSP_USING_ON_CHIP_FLASH_CACHE
+            config BSP_USING_ON_CHIP_FLASH_ICODE_CACHE
+                bool "Enable on-chip Flash ICODE Cache"
+                default y
+            config BSP_USING_ON_CHIP_FLASH_DCODE_CACHE
+                bool "Enable on-chip Flash DCODE Cache"
+                default y
+            config BSP_USING_ON_CHIP_FLASH_ICODE_PREFETCH
+                bool "Enable on-chip Flash ICODE Prefetch"
+                default y
+        endif
+endmenu
+
+menu "Onboard Peripheral Drivers"
+    config BSP_USING_TCA9539
+        bool "Enable TCA9539"
+        select BSP_USING_I2C
+        select BSP_USING_I2C1
+        default n
+
+    config BSP_USING_SPI_FLASH
+        bool "Enable SPI FLASH (w25q64 spi1)"
+        select BSP_USING_SPI
+        select BSP_USING_SPI1
+        select BSP_USING_ON_CHIP_FLASH
+        select RT_USING_SFUD
+        select RT_USING_DFS
+        select RT_USING_FAL
+        select RT_USING_MTD_NOR
+        default n
+
+    config BSP_USING_EXT_IO
+        bool
+        default y
+
+endmenu
+
+menu "On-chip Peripheral Drivers"
+    config BSP_USING_GPIO
+        bool "Enable GPIO"
+        select RT_USING_PIN
+        default y
+
+    menuconfig BSP_USING_UART
+        bool "Enable UART"
+        default y
+        select RT_USING_SERIAL
+        if BSP_USING_UART
+            menuconfig BSP_USING_UART1
+                bool "Enable UART1"
+                default y
+                if BSP_USING_UART1
+                    config BSP_UART1_RX_USING_DMA
+                        bool "Enable UART1 RX DMA"
+                        depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA
+                        default n
+
+                    config BSP_UART1_TX_USING_DMA
+                        bool "Enable UART1 TX DMA"
+                        depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA
+                        default n
+
+                    config BSP_UART1_RX_BUFSIZE
+                        int "Set UART1 RX buffer size"
+                        range 64 65535
+                        depends on RT_USING_SERIAL_V2
+                        default 256
+
+                    config BSP_UART1_TX_BUFSIZE
+                        int "Set UART1 TX buffer size"
+                        range 0 65535
+                        depends on RT_USING_SERIAL_V2
+                        default 256
+                endif
+
+            menuconfig BSP_USING_UART2
+                bool "Enable UART2"
+                default n
+                if BSP_USING_UART2
+                    config BSP_UART2_RX_USING_DMA
+                        bool "Enable UART2 RX DMA"
+                        depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA
+                        default n
+
+                    config BSP_UART2_TX_USING_DMA
+                        bool "Enable UART2 TX DMA"
+                        depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA
+                        default n
+
+                    config BSP_UART2_RX_BUFSIZE
+                        int "Set UART2 RX buffer size"
+                        range 64 65535
+                        depends on RT_USING_SERIAL_V2
+                        default 256
+
+                    config BSP_UART2_TX_BUFSIZE
+                        int "Set UART2 TX buffer size"
+                        range 0 65535
+                        depends on RT_USING_SERIAL_V2
+                        default 0
+                endif
+
+            menuconfig BSP_USING_UART3
+                bool "Enable UART3"
+                default n
+                if BSP_USING_UART3
+                    config BSP_UART3_RX_BUFSIZE
+                        int "Set UART3 RX buffer size"
+                        range 64 65535
+                        depends on RT_USING_SERIAL_V2
+                        default 256
+
+                    config BSP_UART3_TX_BUFSIZE
+                        int "Set UART3 TX buffer size"
+                        range 0 65535
+                        depends on RT_USING_SERIAL_V2
+                        default 0
+                endif
+
+            menuconfig BSP_USING_UART4
+                bool "Enable UART4"
+                default n
+                if BSP_USING_UART4
+                    config BSP_UART4_RX_USING_DMA
+                        bool "Enable UART4 RX DMA"
+                        depends on BSP_USING_UART4 && RT_SERIAL_USING_DMA
+                        default n
+
+                    config BSP_UART4_TX_USING_DMA
+                        bool "Enable UART4 TX DMA"
+                        depends on BSP_USING_UART4 && RT_SERIAL_USING_DMA
+                        default n
+
+                    config BSP_UART4_RX_BUFSIZE
+                        int "Set UART4 RX buffer size"
+                        range 64 65535
+                        depends on RT_USING_SERIAL_V2
+                        default 256
+
+                    config BSP_UART4_TX_BUFSIZE
+                        int "Set UART4 TX buffer size"
+                        range 0 65535
+                        depends on RT_USING_SERIAL_V2
+                        default 256
+                endif
+
+            menuconfig BSP_USING_UART5
+                bool "Enable UART5"
+                default n
+                if BSP_USING_UART5
+                    config BSP_UART5_RX_USING_DMA
+                        bool "Enable UART5 RX DMA"
+                        depends on BSP_USING_UART5 && RT_SERIAL_USING_DMA
+                        default n
+
+                    config BSP_UART5_TX_USING_DMA
+                        bool "Enable UART5 TX DMA"
+                        depends on BSP_USING_UART5 && RT_SERIAL_USING_DMA
+                        default n
+
+                    config BSP_UART5_RX_BUFSIZE
+                        int "Set UART5 RX buffer size"
+                        range 64 65535
+                        depends on RT_USING_SERIAL_V2
+                        default 256
+
+                    config BSP_UART5_TX_BUFSIZE
+                        int "Set UART5 TX buffer size"
+                        range 0 65535
+                        depends on RT_USING_SERIAL_V2
+                        default 256
+                endif
+
+            menuconfig BSP_USING_UART6
+                bool "Enable UART6"
+                default n
+                if BSP_USING_UART6
+                    config BSP_UART6_RX_BUFSIZE
+                        int "Set UART6 RX buffer size"
+                        range 64 65535
+                        depends on RT_USING_SERIAL_V2
+                        default 256
+
+                    config BSP_UART6_TX_BUFSIZE
+                        int "Set UART6 TX buffer size"
+                        range 0 65535
+                        depends on RT_USING_SERIAL_V2
+                        default 0
+                endif
+        endif
+
+    menuconfig BSP_USING_I2C
+        bool "Enable I2C BUS"
+        default n
+        select RT_USING_I2C
+
+        if BSP_USING_I2C
+            menuconfig BSP_USING_I2C1_SW
+                bool "Enable I2C1 BUS (software simulation)"
+                default n
+                select RT_USING_I2C_BITOPS
+                select RT_USING_PIN
+                if BSP_USING_I2C1_SW
+                    config BSP_I2C1_SCL_PIN
+                        int "i2c1 scl pin number"
+                        range 1 176
+                        default 51
+                    config BSP_I2C1_SDA_PIN
+                        int "I2C1 sda pin number"
+                        range 1 176
+                        default 90
+                endif
+        endif
+
+        if BSP_USING_I2C
+            config BSP_I2C_USING_DMA
+                bool
+                default n
+            config BSP_USING_I2C_HW
+                bool
+                default n
+
+            menuconfig BSP_USING_I2C1
+                bool "Enable I2C1 BUS"
+                default n
+                select BSP_USING_I2C_HW
+                if BSP_USING_I2C1
+                    config BSP_I2C1_USING_DMA
+                        bool
+                        default n
+                    config BSP_I2C1_TX_USING_DMA
+                        bool "Enable I2C1 TX DMA"
+                        default n
+                        select BSP_I2C_USING_DMA
+                        select BSP_I2C1_USING_DMA
+                    config BSP_I2C1_RX_USING_DMA
+                        bool "Enable I2C1 RX DMA"
+                        default n
+                        select BSP_I2C_USING_DMA
+                        select BSP_I2C1_USING_DMA
+                endif
+
+            menuconfig BSP_USING_I2C2
+                bool "Enable I2C2 BUS"
+                default n
+                select BSP_USING_I2C_HW
+                if BSP_USING_I2C2
+                    config BSP_I2C2_USING_DMA
+                        bool
+                        default n
+                    config BSP_I2C2_TX_USING_DMA
+                        bool "Enable I2C2 TX DMA"
+                        default n
+                        select BSP_I2C_USING_DMA
+                        select BSP_I2C2_USING_DMA
+                    config BSP_I2C2_RX_USING_DMA
+                        bool "Enable I2C2 RX DMA"
+                        default n
+                        select BSP_I2C_USING_DMA
+                        select BSP_I2C2_USING_DMA
+                endif
+        endif
+
+    config BSP_USING_ON_CHIP_FLASH
+        bool "Enable on-chip FLASH"
+        default n
+
+    menuconfig BSP_USING_SPI
+        bool "Enable SPI BUS"
+        default n
+        select RT_USING_SPI
+        if BSP_USING_SPI
+            config BSP_SPI_USING_DMA
+                bool
+                default n
+
+            menuconfig BSP_USING_SPI1
+                bool "Enable SPI1 BUS"
+                default n
+                if BSP_USING_SPI1
+                    config BSP_SPI1_TX_USING_DMA
+                        bool "Enable SPI1 TX DMA"
+                        select BSP_SPI_USING_DMA
+                        default n
+                    config BSP_SPI1_RX_USING_DMA
+                        bool "Enable SPI1 RX DMA"
+                        select BSP_SPI_USING_DMA
+                        select BSP_SPI1_TX_USING_DMA
+                        default n
+                endif
+
+            menuconfig BSP_USING_SPI2
+                bool "Enable SPI2 BUS"
+                default n
+                if BSP_USING_SPI2
+                    config BSP_SPI2_TX_USING_DMA
+                        bool "Enable SPI2 TX DMA"
+                        select BSP_SPI_USING_DMA
+                        default n
+                    config BSP_SPI2_RX_USING_DMA
+                        bool "Enable SPI2 RX DMA"
+                        select BSP_SPI_USING_DMA
+                        select BSP_SPI2_TX_USING_DMA
+                        default n
+                endif
+
+            menuconfig BSP_USING_SPI3
+                bool "Enable SPI3 BUS"
+                default n
+                if BSP_USING_SPI3
+                    config BSP_SPI3_TX_USING_DMA
+                        bool "Enable SPI3 TX DMA"
+                        select BSP_SPI_USING_DMA
+                        default n
+                    config BSP_SPI3_RX_USING_DMA
+                        bool "Enable SPI3 RX DMA"
+                        select BSP_SPI_USING_DMA
+                        select BSP_SPI3_TX_USING_DMA
+                        default n
+                endif
+
+            menuconfig BSP_USING_SPI4
+                bool "Enable SPI4 BUS"
+                default n
+                if BSP_USING_SPI4
+                    config BSP_SPI4_TX_USING_DMA
+                        bool "Enable SPI4 TX DMA"
+                        select BSP_SPI_USING_DMA
+                        default n
+                    config BSP_SPI4_RX_USING_DMA
+                        bool "Enable SPI4 RX DMA"
+                        select BSP_SPI_USING_DMA
+                        select BSP_SPI4_TX_USING_DMA
+                        default n
+                endif
+        endif
+
+    menuconfig BSP_USING_ADC
+        bool "Enable ADC"
+        default n
+        select RT_USING_ADC
+        if BSP_USING_ADC
+            menuconfig BSP_USING_ADC1
+                bool "Enable ADC1"
+                default n
+                if BSP_USING_ADC1
+                    config BSP_ADC1_USING_DMA
+                        bool "using adc1 dma"
+                        default n
+                endif
+            menuconfig BSP_USING_ADC2
+                bool "Enable ADC2"
+                default n
+                if BSP_USING_ADC2
+                    config BSP_ADC2_USING_DMA
+                        bool "using adc2 dma"
+                        default n
+                endif
+            menuconfig BSP_USING_ADC3
+                bool "Enable ADC3"
+                default n
+                if BSP_USING_ADC3
+                    config BSP_ADC3_USING_DMA
+                        bool "using adc3 dma"
+                        default n
+                endif
+        endif
+
+    menuconfig BSP_USING_DAC
+        bool "Enable DAC"
+        default n
+        select RT_USING_DAC
+        if BSP_USING_DAC
+            config BSP_USING_DAC1
+                bool "using dac1"
+                default n
+            config BSP_USING_DAC2
+                bool "using dac2"
+                default n
+        endif
+
+    menuconfig BSP_USING_CAN
+        bool "Enable CAN"
+        default n
+        select RT_USING_CAN
+        select RT_CAN_USING_HDR
+        select BSP_USING_TCA9539
+        if BSP_USING_CAN
+            config BSP_USING_CAN1
+                bool "using can1"
+                default n
+            config BSP_USING_CAN2
+                bool "using can2"
+                default n
+        endif
+
+    menuconfig BSP_USING_WDT_TMR
+        bool "Enable Watchdog Timer"
+        default n
+        select RT_USING_WDT
+        if BSP_USING_WDT_TMR
+            choice
+                prompt "Select SWDT/WDT"
+                default BSP_USING_SWDT
+
+                config BSP_USING_SWDT
+                    bool "SWDT(3.72hour(max))"
+                config BSP_USING_WDT
+                    bool "WDT(10.7s(max))"
+            endchoice
+
+            config BSP_WDT_CONTINUE_COUNT
+                bool "Low Power Mode Keeps Counting"
+                default n
+        endif
+
+    menuconfig BSP_USING_RTC
+        bool "Enable RTC"
+        select RT_USING_RTC
+        default n
+        if BSP_USING_RTC
+            choice
+                prompt "Select clock source"
+                default BSP_RTC_USING_XTAL32
+
+                config BSP_RTC_USING_XTAL32
+                    bool "RTC USING XTAL32"
+
+                config BSP_RTC_USING_LRC
+                    bool "RTC USING LRC"
+            endchoice
+        endif
+
+    menuconfig BSP_USING_PM
+        bool "Enable PM"
+        default n
+        select RT_USING_PM
+        if BSP_USING_PM
+            choice
+                prompt "Select WKTM Clock Src"
+                default BSP_USING_WKTM_LRC
+
+                config BSP_USING_WKTM_XTAL32
+                    bool "Using Xtal32"
+                config BSP_USING_WKTM_LRC
+                    bool "Using LRC"
+                if BSP_RTC_USING_XTAL32
+                    config BSP_USING_WKTM_64HZ
+                        bool "Using 64HZ(Note:must use XTAL32 and run RTC)"
+                endif
+            endchoice
+        endif
+
+    menuconfig BSP_USING_HWCRYPTO
+        bool "Using Hardware Crypto drivers"
+        default n
+        select RT_USING_HWCRYPTO
+        if BSP_USING_HWCRYPTO
+            config BSP_USING_UQID
+            bool "Enable UQID (unique id)"
+            default n
+
+            config BSP_USING_RNG
+            bool "Using Hardware RNG"
+            default n
+            select RT_HWCRYPTO_USING_RNG
+
+            config BSP_USING_CRC
+            bool "Using Hardware CRC"
+            default n
+            select RT_HWCRYPTO_USING_CRC
+
+            config BSP_USING_AES
+            bool "Using Hardware AES"
+            default n
+            select RT_HWCRYPTO_USING_AES
+            if BSP_USING_AES
+                choice
+                    prompt "Select AES Mode"
+                    default BSP_USING_AES_ECB
+
+                    config BSP_USING_AES_ECB
+                        bool "ECB mode"
+                        select RT_HWCRYPTO_USING_AES_ECB
+                endchoice
+            endif
+
+            config BSP_USING_HASH
+            bool "Using Hardware Hash"
+            default n
+            select RT_HWCRYPTO_USING_SHA2
+            if BSP_USING_HASH
+                choice
+                    prompt "Select Hash Mode"
+                    default BSP_USING_SHA2_256
+
+                    config BSP_USING_SHA2_256
+                        bool "SHA2_256 Mode"
+                        select RT_HWCRYPTO_USING_SHA2_256
+                endchoice
+            endif
+
+        endif
+
+    menuconfig BSP_USING_PWM
+        bool "Enable output PWM"
+        default n
+        select RT_USING_PWM
+        if BSP_USING_PWM
+            menuconfig BSP_USING_PWM_TMRA
+                bool "Enable timerA output PWM"
+                default n
+                if BSP_USING_PWM_TMRA
+                    menuconfig BSP_USING_PWM_TMRA_1
+                        bool "Enable timerA-1 output PWM"
+                        default n
+                        if BSP_USING_PWM_TMRA_1
+                            config BSP_USING_PWM_TMRA_1_CH1
+                                bool "Enable timerA-1 channel1"
+                                default n
+                            config BSP_USING_PWM_TMRA_1_CH2
+                                bool "Enable timerA-1 channel2"
+                                default n
+                        endif
+                    menuconfig BSP_USING_PWM_TMRA_2
+                        bool "Enable timerA-2 output PWM"
+                        default n
+                        if BSP_USING_PWM_TMRA_2
+                            config BSP_USING_PWM_TMRA_2_CH1
+                                bool "Enable timerA-2 channel1"
+                                default n
+                            config BSP_USING_PWM_TMRA_2_CH2
+                                bool "Enable timerA-2 channel2"
+                                default n
+                        endif
+                endif
+            menuconfig BSP_USING_PWM_TMR4
+                bool "Enable timer4 output PWM"
+                default n
+                if BSP_USING_PWM_TMR4
+                    menuconfig BSP_USING_PWM_TMR4_1
+                        bool "Enable timer4-1 output PWM"
+                        default n
+                        if BSP_USING_PWM_TMR4_1
+                            config BSP_USING_PWM_TMR4_1_OUH
+                                bool "Enable TMR4_1_OUH channel0"
+                                default n
+                            config BSP_USING_PWM_TMR4_1_OUL
+                                bool "Enable TMR4_1_OUL channel1"
+                                default n
+                            config BSP_USING_PWM_TMR4_1_OVH
+                                bool "Enable TMR4_1_OVH channel2"
+                                default n
+                            config BSP_USING_PWM_TMR4_1_OVL
+                                bool "Enable TMR4_1_OVL channel3"
+                                default n
+                            config BSP_USING_PWM_TMR4_1_OWH
+                                bool "Enable TMR4_1_OWH channel4"
+                                default n
+                            config BSP_USING_PWM_TMR4_1_OWL
+                                bool "Enable TMR4_1_OWL channel5"
+                                default n
+                        endif
+                endif
+            menuconfig BSP_USING_PWM_TMR6
+                bool "Enable timer6 output PWM"
+                default n
+                if BSP_USING_PWM_TMR6
+                    menuconfig BSP_USING_PWM_TMR6_1
+                        bool "Enable timer6-1 output PWM"
+                        default n
+                        if BSP_USING_PWM_TMR6_1
+                            config BSP_USING_PWM_TMR6_1_A
+                                bool "Enable TMR6_1_A channel0"
+                                default n
+                            config BSP_USING_PWM_TMR6_1_B
+                                bool "Enable TMR6_1_B channel1"
+                                default n
+                        endif
+                endif
+        endif
+
+    menuconfig BSP_USING_QSPI
+        bool "Enable QSPI BUS"
+        select RT_USING_QSPI
+        select RT_USING_SPI
+        default n
+        if BSP_USING_QSPI
+            config BSP_QSPI_USING_DMA
+                bool "Enable QSPI DMA support"
+                default n
+            config BSP_QSPI_USING_SOFT_CS
+                bool "Enable QSPI Soft CS Pin"
+                default n
+        endif
+
+    menuconfig BSP_USING_PULSE_ENCODER
+        bool "Enable Pulse Encoder"
+        default n
+        select RT_USING_PULSE_ENCODER
+        if BSP_USING_PULSE_ENCODER
+            menuconfig BSP_USING_TMRA_PULSE_ENCODER
+                bool "Use TIMERA As The Pulse Encoder"
+                default n
+                if BSP_USING_TMRA_PULSE_ENCODER
+                    config BSP_USING_PULSE_ENCODER_TMRA_1
+                        bool "Use TIMERA_1 As The Pulse Encoder"
+                        default n
+                endif
+            menuconfig BSP_USING_TMR6_PULSE_ENCODER
+                bool "Use TIMER6 As The Pulse Encoder"
+                default n
+                if BSP_USING_TMR6_PULSE_ENCODER
+                    config BSP_USING_PULSE_ENCODER_TMR6_1
+                        bool "Use TIMER6_1 As The Pulse Encoder"
+                        default n
+                endif
+        endif
+
+    menuconfig BSP_USING_HWTIMER
+        bool "Enable Hw Timer"
+        default n
+        select RT_USING_HWTIMER
+        if BSP_USING_HWTIMER
+            config BSP_USING_TMRA_1
+                bool "Use Timer_a1 As The Hw Timer"
+                default n
+            config BSP_USING_TMRA_2
+                bool "Use Timer_a2 As The Hw Timer"
+                default n
+            config BSP_USING_TMRA_3
+                bool "Use Timer_a3 As The Hw Timer"
+                default n
+            config BSP_USING_TMRA_4
+                bool "Use Timer_a4 As The Hw Timer"
+                default n
+            config BSP_USING_TMRA_5
+                bool "Use Timer_a5 As The Hw Timer"
+                default n
+        endif
+
+    menuconfig BSP_USING_SENSOR
+        bool "Enable SENSOR"
+        default n
+        select RT_USING_HWTIMER
+        if BSP_USING_SENSOR
+            config BSP_USING_TMR0_2B
+                bool "Use KEYSCAN"
+                select RT_USING_KEYSCAN
+                default n
+        endif
+endmenu
+
+menu "Board extended module Drivers"
+
+endmenu
+
+endmenu

bsp/hc32/ev_hc32f472_lqfp100/board/SConscript

@@ -0,0 +1,31 @@
+import os
+import rtconfig
+from building import *
+
+Import('SDK_LIB')
+
+cwd = GetCurrentDir()
+
+# add general drivers
+src = Split('''
+board.c
+board_config.c
+''')
+
+path =  [cwd]
+path += [cwd + '/ports']
+path += [cwd + '/config']
+
+startup_path_prefix = SDK_LIB
+
+if rtconfig.PLATFORM in ['gcc']:
+    src += [startup_path_prefix + '/hc32f472_ddl/cmsis/Device/HDSC/hc32f4xx/Source/GCC/startup_hc32f472.S']
+elif rtconfig.PLATFORM in ['armcc', 'armclang']:
+    src += [startup_path_prefix + '/hc32f472_ddl/cmsis/Device/HDSC/hc32f4xx/Source/ARM/startup_hc32f472.s']
+elif rtconfig.PLATFORM in ['iccarm']:
+    src += [startup_path_prefix + '/hc32f472_ddl/cmsis/Device/HDSC/hc32f4xx/Source/IAR/startup_hc32f472.s']
+
+CPPDEFINES = ['HC32F472', '__DEBUG']
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
+
+Return('group')

bsp/hc32/ev_hc32f472_lqfp100/board/board.c

@@ -0,0 +1,113 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2024-02-20     CDT          first version
+ */
+
+#include "board.h"
+#include "board_config.h"
+
+/* unlock/lock peripheral */
+#define EXAMPLE_PERIPH_WE               (LL_PERIPH_GPIO | LL_PERIPH_EFM | LL_PERIPH_FCG | \
+                                         LL_PERIPH_PWC_CLK_RMU)
+#define EXAMPLE_PERIPH_WP               (LL_PERIPH_EFM | LL_PERIPH_FCG)
+
+/** System Base Configuration
+*/
+void SystemBase_Config(void)
+{
+#if defined(BSP_USING_ON_CHIP_FLASH_ICODE_CACHE)
+    EFM_ICacheCmd(ENABLE);
+#endif
+#if defined(BSP_USING_ON_CHIP_FLASH_DCODE_CACHE)
+    EFM_DCacheCmd(ENABLE);
+#endif
+#if defined(BSP_USING_ON_CHIP_FLASH_ICODE_PREFETCH)
+    EFM_PrefetchCmd(ENABLE);
+#endif
+}
+
+/** System Clock Configuration
+*/
+void SystemClock_Config(void)
+{
+    stc_clock_xtal_init_t stcXtalInit;
+    stc_clock_pll_init_t stcPLLHInit;
+#if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM)
+    stc_clock_xtal32_init_t stcXtal32Init;
+#endif
+
+    /* PCLK0, HCLK Max 200MHz */
+    /* PCLK1, PCLK4 Max 100MHz */
+    /* PCLK2, EXCLK Max 60MHz */
+    /* PCLK3 Max 50MHz */
+    CLK_SetClockDiv(CLK_BUS_CLK_ALL,
+                    (CLK_PCLK0_DIV1 | CLK_PCLK1_DIV2 | CLK_PCLK2_DIV4 |
+                     CLK_PCLK3_DIV4 | CLK_PCLK4_DIV2 | CLK_EXCLK_DIV4 |
+                     CLK_HCLK_DIV1));
+
+    GPIO_AnalogCmd(XTAL_PORT, XTAL_IN_PIN | XTAL_OUT_PIN, ENABLE);
+    (void)CLK_XtalStructInit(&stcXtalInit);
+    /* Config Xtal and enable Xtal */
+    stcXtalInit.u8Mode   = CLK_XTAL_MD_OSC;
+    stcXtalInit.u8Drv    = CLK_XTAL_DRV_ULOW;
+    stcXtalInit.u8State  = CLK_XTAL_ON;
+    stcXtalInit.u8StableTime = CLK_XTAL_STB_2MS;
+    (void)CLK_XtalInit(&stcXtalInit);
+
+    (void)CLK_PLLStructInit(&stcPLLHInit);
+    /* VCO = (12/1)*40 = 480MHz*/
+    stcPLLHInit.u8PLLState = CLK_PLL_ON;
+    stcPLLHInit.PLLCFGR = 0UL;
+    stcPLLHInit.PLLCFGR_f.PLLM = 1UL - 1UL;
+    stcPLLHInit.PLLCFGR_f.PLLN = 40UL - 1UL;
+    stcPLLHInit.PLLCFGR_f.PLLP = 4UL - 1UL;
+    stcPLLHInit.PLLCFGR_f.PLLQ = 4UL - 1UL;
+    stcPLLHInit.PLLCFGR_f.PLLR = 4UL - 1UL;
+    stcPLLHInit.PLLCFGR_f.PLLSRC = CLK_PLL_SRC_XTAL;
+    (void)CLK_PLLInit(&stcPLLHInit);
+
+    /* 0-wait @ 40MHz */
+    (void)EFM_SetWaitCycle(EFM_WAIT_CYCLE2);
+    /* 2 cycles for 100 ~ 150MHz */
+    GPIO_SetReadWaitCycle(GPIO_RD_WAIT2);
+    CLK_SetSysClockSrc(CLK_SYSCLK_SRC_PLL);
+
+#if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM)
+    /* Xtal32 config */
+    GPIO_AnalogCmd(XTAL32_PORT, XTAL32_IN_PIN | XTAL32_OUT_PIN, ENABLE);
+    (void)CLK_Xtal32StructInit(&stcXtal32Init);
+    stcXtal32Init.u8State  = CLK_XTAL32_ON;
+    stcXtal32Init.u8Drv    = CLK_XTAL32_DRV_HIGH;
+    stcXtal32Init.u8Filter = CLK_XTAL32_FILTER_RUN_MD;
+    (void)CLK_Xtal32Init(&stcXtal32Init);
+#endif
+}
+
+/** Peripheral Clock Configuration
+*/
+void PeripheralClock_Config(void)
+{
+#if defined(BSP_USING_CAN1)
+    CLK_SetCANClockSrc(CLK_CAN1, CLK_CANCLK_SYSCLK_DIV6);
+#endif
+#if defined(BSP_USING_CAN2)
+    CLK_SetCANClockSrc(CLK_CAN2, CLK_CANCLK_SYSCLK_DIV6);
+#endif
+
+#if defined(RT_USING_ADC)
+    CLK_SetPeriClockSrc(CLK_PERIPHCLK_PCLK);
+#endif
+}
+
+/** Peripheral Registers Unlock
+*/
+void PeripheralRegister_Unlock(void)
+{
+    LL_PERIPH_WE(EXAMPLE_PERIPH_WE);
+}

bsp/hc32/ev_hc32f472_lqfp100/board/board.h

@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2024-02-20     CDT          first version
+ */
+
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#include <rtthread.h>
+#include "hc32_ll.h"
+#include "drv_gpio.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#define HC32_FLASH_SIZE_GRANULARITY     (8 * 1024)
+#define HC32_FLASH_SIZE                 (512 * 1024)
+#define HC32_FLASH_START_ADDRESS        (0)
+#define HC32_FLASH_END_ADDRESS          (HC32_FLASH_START_ADDRESS + HC32_FLASH_SIZE)
+
+#define HC32_SRAM_SIZE                  (64)
+#define HC32_SRAM_END                   (0x1FFF8000 + HC32_SRAM_SIZE * 1024)
+
+#ifdef __ARMCC_VERSION
+extern int Image$$RW_IRAM2$$ZI$$Limit;
+#define HEAP_BEGIN                      (&Image$$RW_IRAM2$$ZI$$Limit)
+#elif __ICCARM__
+#pragma section="HEAP"
+#define HEAP_BEGIN                      (__segment_end("HEAP"))
+#else
+extern int __bss_end;
+#define HEAP_BEGIN                      (&__bss_end)
+#endif
+
+#define HEAP_END                        HC32_SRAM_END
+
+void PeripheralRegister_Unlock(void);
+void PeripheralClock_Config(void);
+void SystemBase_Config(void);
+void SystemClock_Config(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

bsp/hc32/ev_hc32f472_lqfp100/board/board_config.c

@@ -0,0 +1,499 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2024-02-20     CDT          first version
+ */
+
+#include <rtdevice.h>
+#include "board_config.h"
+#if defined(RT_USING_CAN)
+#include "tca9539_port.h"
+#endif
+
+/**
+ * The below functions will initialize HC32 board.
+ */
+
+#if defined RT_USING_SERIAL
+rt_err_t rt_hw_board_uart_init(CM_USART_TypeDef *USARTx)
+{
+    rt_err_t result = RT_EOK;
+
+    switch ((rt_uint32_t)USARTx)
+    {
+#if defined(BSP_USING_UART1)
+    case (rt_uint32_t)CM_USART1:
+        /* Configure USART RX/TX pin. */
+        GPIO_SetFunc(USART1_RX_PORT, USART1_RX_PIN, USART1_RX_FUNC);
+        GPIO_SetFunc(USART1_TX_PORT, USART1_TX_PIN, USART1_TX_FUNC);
+        break;
+#endif
+#if defined(BSP_USING_UART2)
+    case (rt_uint32_t)CM_USART2:
+        /* Configure USART RX/TX pin. */
+        GPIO_SetFunc(USART2_RX_PORT, USART2_RX_PIN, USART2_RX_FUNC);
+        GPIO_SetFunc(USART2_TX_PORT, USART2_TX_PIN, USART2_TX_FUNC);
+        break;
+#endif
+#if defined(BSP_USING_UART5)
+    case (rt_uint32_t)CM_USART5:
+        /* Configure USART RX/TX pin. */
+        GPIO_SetFunc(USART5_RX_PORT, USART5_RX_PIN, USART5_RX_FUNC);
+        GPIO_SetFunc(USART5_TX_PORT, USART5_TX_PIN, USART5_TX_FUNC);
+        break;
+#endif
+    default:
+        result = -RT_ERROR;
+        break;
+    }
+
+    return result;
+}
+#endif
+
+#if defined(RT_USING_I2C)
+rt_err_t rt_hw_board_i2c_init(CM_I2C_TypeDef *I2Cx)
+{
+    rt_err_t result = RT_EOK;
+    stc_gpio_init_t stcGpioInit;
+    (void)GPIO_StructInit(&stcGpioInit);
+
+    switch ((rt_uint32_t)I2Cx)
+    {
+#if defined(BSP_USING_I2C1)
+    case (rt_uint32_t)CM_I2C1:
+        /* Configure I2C1 SDA/SCL pin. */
+        GPIO_SetFunc(I2C1_SDA_PORT, I2C1_SDA_PIN, I2C1_SDA_FUNC);
+        GPIO_SetFunc(I2C1_SCL_PORT, I2C1_SCL_PIN, I2C1_SCL_FUNC);
+        break;
+#endif
+#if defined(BSP_USING_I2C2)
+    case (rt_uint32_t)CM_I2C2:
+        /* Configure I2C2 SDA/SCL pin. */
+        GPIO_SetFunc(I2C2_SDA_PORT, I2C2_SDA_PIN, I2C2_SDA_FUNC);
+        GPIO_SetFunc(I2C2_SCL_PORT, I2C2_SCL_PIN, I2C2_SCL_FUNC);
+        break;
+#endif
+    default:
+        result = -RT_ERROR;
+        break;
+    }
+    return result;
+}
+#endif
+
+#if defined(RT_USING_ADC)
+rt_err_t rt_hw_board_adc_init(CM_ADC_TypeDef *ADCx)
+{
+    rt_err_t result = RT_EOK;
+    stc_gpio_init_t stcGpioInit;
+
+    (void)GPIO_StructInit(&stcGpioInit);
+    stcGpioInit.u16PinAttr = PIN_ATTR_ANALOG;
+    switch ((rt_uint32_t)ADCx)
+    {
+#if defined(BSP_USING_ADC1)
+    case (rt_uint32_t)CM_ADC1:
+        (void)GPIO_Init(ADC1_CH_PORT, ADC1_CH_PIN, &stcGpioInit);
+        break;
+#endif
+#if defined(BSP_USING_ADC2)
+    case (rt_uint32_t)CM_ADC2:
+        (void)GPIO_Init(ADC2_CH_PORT, ADC2_CH_PIN, &stcGpioInit);
+        break;
+#endif
+#if defined(BSP_USING_ADC3)
+    case (rt_uint32_t)CM_ADC3:
+        (void)GPIO_Init(ADC3_CH_PORT, ADC3_CH_PIN, &stcGpioInit);
+        break;
+#endif
+    default:
+        result = -RT_ERROR;
+        break;
+    }
+
+    return result;
+}
+#endif
+
+#if defined(RT_USING_DAC)
+rt_err_t rt_hw_board_dac_init(CM_DAC_TypeDef *DACx)
+{
+    rt_err_t result = RT_EOK;
+    stc_gpio_init_t stcGpioInit;
+
+    (void)GPIO_StructInit(&stcGpioInit);
+    stcGpioInit.u16PinAttr = PIN_ATTR_ANALOG;
+    switch ((rt_uint32_t)DACx)
+    {
+#if defined(BSP_USING_DAC1)
+    case (rt_uint32_t)CM_DAC1:
+        (void)GPIO_Init(DAC1_CH1_PORT, DAC1_CH1_PIN, &stcGpioInit);
+        (void)GPIO_Init(DAC1_CH2_PORT, DAC1_CH2_PIN, &stcGpioInit);
+        break;
+#endif
+    default:
+        result = -RT_ERROR;
+        break;
+    }
+
+    return result;
+}
+#endif
+
+#if defined(RT_USING_CAN)
+void CanPhyEnable(void)
+{
+#if defined(BSP_USING_CAN1)
+    TCA9539_WritePin(CAN1_STB_PORT, CAN1_STB_PIN, TCA9539_PIN_RESET);
+    TCA9539_ConfigPin(CAN1_STB_PORT, CAN1_STB_PIN, TCA9539_DIR_OUT);
+#endif
+#if defined(BSP_USING_CAN2)
+    TCA9539_WritePin(CAN2_STB_PORT, CAN2_STB_PIN, TCA9539_PIN_RESET);
+    TCA9539_ConfigPin(CAN2_STB_PORT, CAN2_STB_PIN, TCA9539_DIR_OUT);
+#endif
+}
+rt_err_t rt_hw_board_can_init(CM_CAN_TypeDef *CANx)
+{
+    rt_err_t result = RT_EOK;
+
+    switch ((rt_uint32_t)CANx)
+    {
+#if defined(BSP_USING_CAN1)
+    case (rt_uint32_t)CM_CAN1:
+        GPIO_SetFunc(CAN1_TX_PORT, CAN1_TX_PIN, CAN1_TX_PIN_FUNC);
+        GPIO_SetFunc(CAN1_RX_PORT, CAN1_RX_PIN, CAN1_RX_PIN_FUNC);
+        break;
+#endif
+#if defined(BSP_USING_CAN2)
+    case (rt_uint32_t)CM_CAN2:
+        GPIO_SetFunc(CAN2_TX_PORT, CAN2_TX_PIN, CAN2_TX_PIN_FUNC);
+        GPIO_SetFunc(CAN2_RX_PORT, CAN2_RX_PIN, CAN2_RX_PIN_FUNC);
+        break;
+#endif
+    default:
+        result = -RT_ERROR;
+        break;
+    }
+
+    return result;
+}
+#endif
+
+
+#if defined (RT_USING_SPI)
+rt_err_t rt_hw_spi_board_init(CM_SPI_TypeDef *CM_SPIx)
+{
+    rt_err_t result = RT_EOK;
+#if defined(BSP_USING_SPI1)
+    stc_gpio_init_t stcGpioInit;
+#endif
+
+    switch ((rt_uint32_t)CM_SPIx)
+    {
+#if defined(BSP_USING_SPI1)
+    case (rt_uint32_t)CM_SPI1:
+        GPIO_StructInit(&stcGpioInit);
+        stcGpioInit.u16PinState = PIN_STAT_SET;
+        stcGpioInit.u16PinDir   = PIN_DIR_OUT;
+        GPIO_Init(SPI1_WP_PORT, SPI1_WP_PIN, &stcGpioInit);
+        GPIO_Init(SPI1_HOLD_PORT, SPI1_HOLD_PIN, &stcGpioInit);
+
+        (void)GPIO_StructInit(&stcGpioInit);
+        stcGpioInit.u16PinDrv = PIN_HIGH_DRV;
+        stcGpioInit.u16PinInputType = PIN_IN_TYPE_CMOS;
+        (void)GPIO_Init(SPI1_SCK_PORT,  SPI1_SCK_PIN,  &stcGpioInit);
+        (void)GPIO_Init(SPI1_MOSI_PORT, SPI1_MOSI_PIN, &stcGpioInit);
+        (void)GPIO_Init(SPI1_MISO_PORT, SPI1_MISO_PIN, &stcGpioInit);
+        GPIO_SetFunc(SPI1_SCK_PORT,  SPI1_SCK_PIN,  SPI1_SCK_FUNC);
+        GPIO_SetFunc(SPI1_MOSI_PORT, SPI1_MOSI_PIN, SPI1_MOSI_FUNC);
+        GPIO_SetFunc(SPI1_MISO_PORT, SPI1_MISO_PIN, SPI1_MISO_FUNC);
+        break;
+#endif
+    default:
+        result = -RT_ERROR;
+        break;
+    }
+
+    return result;
+}
+#endif
+
+#if defined(RT_USING_PWM)
+#if defined(BSP_USING_PWM_TMRA)
+rt_err_t rt_hw_board_pwm_tmra_init(CM_TMRA_TypeDef *TMRAx)
+{
+    rt_err_t result = RT_EOK;
+    switch ((rt_uint32_t)TMRAx)
+    {
+#if defined(BSP_USING_PWM_TMRA_1)
+    case (rt_uint32_t)CM_TMRA_1:
+#ifdef BSP_USING_PWM_TMRA_1_CH1
+        GPIO_SetFunc(PWM_TMRA_1_CH1_PORT, PWM_TMRA_1_CH1_PIN, PWM_TMRA_1_CH1_PIN_FUNC);
+#endif
+#ifdef BSP_USING_PWM_TMRA_1_CH2
+        GPIO_SetFunc(PWM_TMRA_1_CH2_PORT, PWM_TMRA_1_CH2_PIN, PWM_TMRA_1_CH2_PIN_FUNC);
+#endif
+#ifdef BSP_USING_PWM_TMRA_1_CH3
+        GPIO_SetFunc(PWM_TMRA_1_CH3_PORT, PWM_TMRA_1_CH3_PIN, PWM_TMRA_1_CH3_PIN_FUNC);
+#endif
+#ifdef BSP_USING_PWM_TMRA_1_CH4
+        GPIO_SetFunc(PWM_TMRA_1_CH4_PORT, PWM_TMRA_1_CH4_PIN, PWM_TMRA_1_CH4_PIN_FUNC);
+#endif
+        break;
+#endif
+#if defined(BSP_USING_PWM_TMRA_2)
+    case (rt_uint32_t)CM_TMRA_2:
+#ifdef BSP_USING_PWM_TMRA_2_CH1
+        GPIO_SetFunc(PWM_TMRA_2_CH1_PORT, PWM_TMRA_2_CH1_PIN, PWM_TMRA_2_CH1_PIN_FUNC);
+#endif
+#ifdef BSP_USING_PWM_TMRA_2_CH2
+        GPIO_SetFunc(PWM_TMRA_2_CH2_PORT, PWM_TMRA_2_CH2_PIN, PWM_TMRA_2_CH2_PIN_FUNC);
+#endif
+#ifdef BSP_USING_PWM_TMRA_2_CH3
+        GPIO_SetFunc(PWM_TMRA_2_CH3_PORT, PWM_TMRA_2_CH3_PIN, PWM_TMRA_2_CH3_PIN_FUNC);
+#endif
+#ifdef BSP_USING_PWM_TMRA_2_CH4
+        GPIO_SetFunc(PWM_TMRA_2_CH4_PORT, PWM_TMRA_2_CH4_PIN, PWM_TMRA_2_CH4_PIN_FUNC);
+#endif
+        break;
+#endif
+    default:
+        result = -RT_ERROR;
+        break;
+    }
+
+    return result;
+}
+#endif
+
+#if defined(BSP_USING_PWM_TMR4)
+rt_err_t rt_hw_board_pwm_tmr4_init(CM_TMR4_TypeDef *TMR4x)
+{
+    rt_err_t result = RT_EOK;
+    switch ((rt_uint32_t)TMR4x)
+    {
+#if defined(BSP_USING_PWM_TMR4_1)
+    case (rt_uint32_t)CM_TMR4_1:
+#ifdef BSP_USING_PWM_TMR4_1_OUH
+        GPIO_SetFunc(PWM_TMR4_1_OUH_PORT, PWM_TMR4_1_OUH_PIN, PWM_TMR4_1_OUH_PIN_FUNC);
+#endif
+#ifdef BSP_USING_PWM_TMR4_1_OUL
+        GPIO_SetFunc(PWM_TMR4_1_OUL_PORT, PWM_TMR4_1_OUL_PIN, PWM_TMR4_1_OUL_PIN_FUNC);
+#endif
+#ifdef BSP_USING_PWM_TMR4_1_OVH
+        GPIO_SetFunc(PWM_TMR4_1_OVH_PORT, PWM_TMR4_1_OVH_PIN, PWM_TMR4_1_OVH_PIN_FUNC);
+#endif
+#ifdef BSP_USING_PWM_TMR4_1_OVL
+        GPIO_SetFunc(PWM_TMR4_1_OVL_PORT, PWM_TMR4_1_OVL_PIN, PWM_TMR4_1_OVL_PIN_FUNC);
+#endif
+#ifdef BSP_USING_PWM_TMR4_1_OWH
+        GPIO_SetFunc(PWM_TMR4_1_OWH_PORT, PWM_TMR4_1_OWH_PIN, PWM_TMR4_1_OWH_PIN_FUNC);
+#endif
+#ifdef BSP_USING_PWM_TMR4_1_OWL
+        GPIO_SetFunc(PWM_TMR4_1_OWL_PORT, PWM_TMR4_1_OWL_PIN, PWM_TMR4_1_OWL_PIN_FUNC);
+#endif
+        break;
+#endif
+    default:
+        result = -RT_ERROR;
+        break;
+    }
+    return result;
+}
+#endif
+
+#if defined(BSP_USING_PWM_TMR6)
+rt_err_t rt_hw_board_pwm_tmr6_init(CM_TMR6_TypeDef *TMR6x)
+{
+    rt_err_t result = RT_EOK;
+    switch ((rt_uint32_t)TMR6x)
+    {
+#if defined(BSP_USING_PWM_TMR6_1)
+    case (rt_uint32_t)CM_TMR6_1:
+#ifdef BSP_USING_PWM_TMR6_1_A
+        GPIO_SetFunc(PWM_TMR6_1_A_PORT, PWM_TMR6_1_A_PIN, PWM_TMR6_1_A_PIN_FUNC);
+#endif
+#ifdef BSP_USING_PWM_TMR6_1_B
+        GPIO_SetFunc(PWM_TMR6_1_B_PORT, PWM_TMR6_1_B_PIN, PWM_TMR6_1_B_PIN_FUNC);
+#endif
+        break;
+#endif
+    default:
+        result = -RT_ERROR;
+        break;
+    }
+
+    return result;
+}
+#endif
+#endif
+
+#ifdef RT_USING_PM
+#define EFM_ERASE_TIME_MAX_IN_MILLISECOND                   (20)
+#define PLL_SRC                                             ((CM_CMU->PLLHCFGR & CMU_PLLHCFGR_PLLSRC) >> CMU_PLLHCFGR_PLLSRC_POS)
+
+static void _pm_sleep_common_init(rt_bool_t b_disable_unused_clk)
+{
+    CLK_Xtal32Cmd(ENABLE);
+
+    rt_tick_t tick_start = rt_tick_get_millisecond();
+    rt_err_t rt_stat = RT_EOK;
+    //wait flash idle
+    while (SET != EFM_GetStatus(EFM_FLAG_RDY))
+    {
+        if (rt_tick_get_millisecond() - tick_start > EFM_ERASE_TIME_MAX_IN_MILLISECOND)
+        {
+            rt_stat = RT_ERROR;
+            break;
+        }
+    }
+    RT_ASSERT(rt_stat == RT_EOK);
+
+    if (b_disable_unused_clk)
+    {
+        uint32_t cur_clk_src = READ_REG8_BIT(CM_CMU->CKSWR, CMU_CKSWR_CKSW);
+
+        switch (cur_clk_src)
+        {
+        case CLK_SYSCLK_SRC_HRC:
+            CLK_PLLCmd(DISABLE);
+            CLK_MrcCmd(DISABLE);
+            CLK_LrcCmd(DISABLE);
+            CLK_XtalCmd(DISABLE);
+            PWC_LDO_Cmd(PWC_LDO_PLL, DISABLE);
+            break;
+        case CLK_SYSCLK_SRC_MRC:
+            CLK_PLLCmd(DISABLE);
+            CLK_HrcCmd(DISABLE);
+            CLK_LrcCmd(DISABLE);
+            CLK_XtalCmd(DISABLE);
+            PWC_LDO_Cmd(PWC_LDO_PLL | PWC_LDO_HRC, DISABLE);
+
+            break;
+        case CLK_SYSCLK_SRC_XTAL:
+            CLK_PLLCmd(DISABLE);
+            CLK_HrcCmd(DISABLE);
+            CLK_MrcCmd(DISABLE);
+            CLK_LrcCmd(DISABLE);
+            PWC_LDO_Cmd(PWC_LDO_PLL | PWC_LDO_HRC, DISABLE);
+
+            break;
+        case CLK_SYSCLK_SRC_XTAL32:
+            CLK_PLLCmd(DISABLE);
+            CLK_HrcCmd(DISABLE);
+            CLK_MrcCmd(DISABLE);
+            CLK_LrcCmd(DISABLE);
+            CLK_XtalCmd(DISABLE);
+            PWC_LDO_Cmd(PWC_LDO_PLL | PWC_LDO_HRC, DISABLE);
+
+            break;
+        case CLK_SYSCLK_SRC_PLL:
+            if (CLK_PLL_SRC_XTAL == PLL_SRC)
+            {
+                CLK_HrcCmd(DISABLE);
+            }
+            else
+            {
+                CLK_XtalCmd(DISABLE);
+            }
+            CLK_MrcCmd(DISABLE);
+            CLK_LrcCmd(DISABLE);
+            PWC_LDO_Cmd(PWC_LDO_HRC, DISABLE);
+
+            break;
+        default:
+            break;
+        }
+    }
+}
+
+void rt_hw_board_pm_sleep_deep_init(void)
+{
+#if (PM_SLEEP_DEEP_CFG_CLK   == PWC_STOP_CLK_KEEP)
+    _pm_sleep_common_init(RT_TRUE);
+#else
+    _pm_sleep_common_init(RT_FALSE);
+    CLK_PLLCmd(DISABLE);
+    CLK_HrcCmd(DISABLE);
+    CLK_LrcCmd(DISABLE);
+    CLK_XtalCmd(DISABLE);
+    PWC_LDO_Cmd(PWC_LDO_PLL | PWC_LDO_HRC, DISABLE);
+#endif
+}
+
+void rt_hw_board_pm_sleep_shutdown_init(void)
+{
+    _pm_sleep_common_init(RT_TRUE);
+}
+
+void rt_hw_board_pm_sysclk_cfg(uint8_t run_mode)
+{
+    switch (run_mode)
+    {
+    case PM_RUN_MODE_HIGH_SPEED:
+    case PM_RUN_MODE_NORMAL_SPEED:
+        SystemClock_Config();
+        break;
+
+    case PM_RUN_MODE_LOW_SPEED:
+        CLK_SetSysClockSrc(CLK_SYSCLK_SRC_XTAL);
+
+    default:
+        break;
+    }
+}
+#endif
+
+#if defined(BSP_USING_QSPI)
+rt_err_t rt_hw_qspi_board_init(void)
+{
+    stc_gpio_init_t stcGpioInit;
+
+    (void)GPIO_StructInit(&stcGpioInit);
+    stcGpioInit.u16PinDrv = PIN_HIGH_DRV;
+#ifndef BSP_QSPI_USING_SOFT_CS
+    (void)GPIO_Init(QSPI_FLASH_CS_PORT,  QSPI_FLASH_CS_PIN,  &stcGpioInit);
+    GPIO_SetFunc(QSPI_FLASH_CS_PORT,  QSPI_FLASH_CS_PIN,  QSPI_FLASH_CS_FUNC);
+#endif
+    (void)GPIO_Init(QSPI_FLASH_SCK_PORT, QSPI_FLASH_SCK_PIN, &stcGpioInit);
+    (void)GPIO_Init(QSPI_FLASH_IO0_PORT, QSPI_FLASH_IO0_PIN, &stcGpioInit);
+    (void)GPIO_Init(QSPI_FLASH_IO1_PORT, QSPI_FLASH_IO1_PIN, &stcGpioInit);
+    (void)GPIO_Init(QSPI_FLASH_IO2_PORT, QSPI_FLASH_IO2_PIN, &stcGpioInit);
+    (void)GPIO_Init(QSPI_FLASH_IO3_PORT, QSPI_FLASH_IO3_PIN, &stcGpioInit);
+    GPIO_SetFunc(QSPI_FLASH_SCK_PORT, QSPI_FLASH_SCK_PIN, QSPI_FLASH_SCK_FUNC);
+    GPIO_SetFunc(QSPI_FLASH_IO0_PORT, QSPI_FLASH_IO0_PIN, QSPI_FLASH_IO0_FUNC);
+    GPIO_SetFunc(QSPI_FLASH_IO1_PORT, QSPI_FLASH_IO1_PIN, QSPI_FLASH_IO1_FUNC);
+    GPIO_SetFunc(QSPI_FLASH_IO2_PORT, QSPI_FLASH_IO2_PIN, QSPI_FLASH_IO2_FUNC);
+    GPIO_SetFunc(QSPI_FLASH_IO3_PORT, QSPI_FLASH_IO3_PIN, QSPI_FLASH_IO3_FUNC);
+
+    return RT_EOK;
+}
+#endif
+
+#if defined(BSP_USING_TMRA_PULSE_ENCODER)
+rt_err_t rt_hw_board_pulse_encoder_tmra_init(void)
+{
+#if defined(BSP_USING_PULSE_ENCODER_TMRA_1)
+    GPIO_SetFunc(PULSE_ENCODER_TMRA_1_A_PORT, PULSE_ENCODER_TMRA_1_A_PIN, PULSE_ENCODER_TMRA_1_A_PIN_FUNC);
+    GPIO_SetFunc(PULSE_ENCODER_TMRA_1_B_PORT, PULSE_ENCODER_TMRA_1_B_PIN, PULSE_ENCODER_TMRA_1_B_PIN_FUNC);
+#endif
+    return RT_EOK;
+}
+#endif
+
+#if defined(BSP_USING_TMR6_PULSE_ENCODER)
+rt_err_t rt_hw_board_pulse_encoder_tmr6_init(void)
+{
+#if defined(BSP_USING_PULSE_ENCODER_TMR6_1)
+    GPIO_SetFunc(PULSE_ENCODER_TMR6_1_A_PORT, PULSE_ENCODER_TMR6_1_A_PIN, PULSE_ENCODER_TMR6_1_A_PIN_FUNC);
+    GPIO_SetFunc(PULSE_ENCODER_TMR6_1_B_PORT, PULSE_ENCODER_TMR6_1_B_PIN, PULSE_ENCODER_TMR6_1_B_PIN_FUNC);
+#endif
+    return RT_EOK;
+}
+#endif

bsp/hc32/ev_hc32f472_lqfp100/board/board_config.h

@@ -0,0 +1,329 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2024-02-20     CDT          first version
+ */
+
+
+#ifndef __BOARD_CONFIG_H__
+#define __BOARD_CONFIG_H__
+
+#include <rtconfig.h>
+#include "hc32_ll.h"
+#include "drv_config.h"
+
+
+/************************* XTAL port **********************/
+#define XTAL_PORT                       (GPIO_PORT_F)
+#define XTAL_IN_PIN                     (GPIO_PIN_00)
+#define XTAL_OUT_PIN                    (GPIO_PIN_01)
+
+/************************ USART port **********************/
+#if defined(BSP_USING_UART1)
+    #define USART1_RX_PORT                  (GPIO_PORT_E)
+    #define USART1_RX_PIN                   (GPIO_PIN_03)
+    #define USART1_RX_FUNC                  (GPIO_FUNC_33)
+
+    #define USART1_TX_PORT                  (GPIO_PORT_E)
+    #define USART1_TX_PIN                   (GPIO_PIN_04)
+    #define USART1_TX_FUNC                  (GPIO_FUNC_32)
+#endif
+
+#if defined(BSP_USING_UART2)
+    #define USART2_RX_PORT                  (GPIO_PORT_F)
+    #define USART2_RX_PIN                   (GPIO_PIN_02)
+    #define USART2_RX_FUNC                  (GPIO_FUNC_35)
+
+    #define USART2_TX_PORT                  (GPIO_PORT_C)
+    #define USART2_TX_PIN                   (GPIO_PIN_13)
+    #define USART2_TX_FUNC                  (GPIO_FUNC_34)
+#endif
+
+#if defined(BSP_USING_UART5)
+    #define USART5_RX_PORT                  (GPIO_PORT_E)
+    #define USART5_RX_PIN                   (GPIO_PIN_05)
+    #define USART5_RX_FUNC                  (GPIO_FUNC_41)
+
+    #define USART5_TX_PORT                  (GPIO_PORT_E)
+    #define USART5_TX_PIN                   (GPIO_PIN_06)
+    #define USART5_TX_FUNC                  (GPIO_FUNC_40)
+#endif
+
+/************************ I2C port **********************/
+#if defined(BSP_USING_I2C1)
+    #define I2C1_SDA_PORT                   (GPIO_PORT_B)
+    #define I2C1_SDA_PIN                    (GPIO_PIN_09)
+    #define I2C1_SDA_FUNC                   (GPIO_FUNC_54)
+
+    #define I2C1_SCL_PORT                   (GPIO_PORT_B)
+    #define I2C1_SCL_PIN                    (GPIO_PIN_06)
+    #define I2C1_SCL_FUNC                   (GPIO_FUNC_55)
+#endif
+ // TODO, ch2/3 for test only
+#if defined(BSP_USING_I2C2)
+    #define I2C2_SDA_PORT                   (GPIO_PORT_A)
+    #define I2C2_SDA_PIN                    (GPIO_PIN_09)
+    #define I2C2_SDA_FUNC                   (GPIO_FUNC_56)
+
+    #define I2C2_SCL_PORT                   (GPIO_PORT_A)
+    #define I2C2_SCL_PIN                    (GPIO_PIN_10)
+    #define I2C2_SCL_FUNC                   (GPIO_FUNC_57)
+#endif
+
+#if defined(BSP_USING_I2C3)
+    #define I2C3_SDA_PORT                   (GPIO_PORT_A)
+    #define I2C3_SDA_PIN                    (GPIO_PIN_09)
+    #define I2C3_SDA_FUNC                   (GPIO_FUNC_58)
+
+    #define I2C3_SCL_PORT                   (GPIO_PORT_A)
+    #define I2C3_SCL_PIN                    (GPIO_PIN_10)
+    #define I2C3_SCL_FUNC                   (GPIO_FUNC_59)
+#endif
+
+/***********  ADC configure *********/
+#if defined(BSP_USING_ADC1)
+    #define ADC1_CH_PORT                    (GPIO_PORT_A)
+    #define ADC1_CH_PIN                     (GPIO_PIN_06)
+#endif
+
+#if defined(BSP_USING_ADC2)
+    #define ADC2_CH_PORT                    (GPIO_PORT_C)
+    #define ADC2_CH_PIN                     (GPIO_PIN_04)
+#endif
+
+#if defined(BSP_USING_ADC3)
+    #define ADC3_CH_PORT                    (GPIO_PORT_C)
+    #define ADC3_CH_PIN                     (GPIO_PIN_01)
+#endif
+
+/***********  DAC configure *********/
+#if defined(BSP_USING_DAC1)
+    #define DAC1_CH1_PORT                   (GPIO_PORT_A)
+    #define DAC1_CH1_PIN                    (GPIO_PIN_04)
+    #define DAC1_CH2_PORT                   (GPIO_PORT_A)
+    #define DAC1_CH2_PIN                    (GPIO_PIN_05)
+#endif
+
+/***********  CAN configure *********/
+#if defined(BSP_USING_CAN1)
+    #define CAN1_TX_PORT                    (GPIO_PORT_D)
+    #define CAN1_TX_PIN                     (GPIO_PIN_12)
+    #define CAN1_TX_PIN_FUNC                (GPIO_FUNC_60)
+
+    #define CAN1_RX_PORT                    (GPIO_PORT_D)
+    #define CAN1_RX_PIN                     (GPIO_PIN_13)
+    #define CAN1_RX_PIN_FUNC                (GPIO_FUNC_61)
+#endif
+
+#if defined(BSP_USING_CAN2)
+    #define CAN2_TX_PORT                    (GPIO_PORT_C)
+    #define CAN2_TX_PIN                     (GPIO_PIN_07)
+    #define CAN2_TX_PIN_FUNC                (GPIO_FUNC_60)
+
+    #define CAN2_RX_PORT                    (GPIO_PORT_D)
+    #define CAN2_RX_PIN                     (GPIO_PIN_11)
+    #define CAN2_RX_PIN_FUNC                (GPIO_FUNC_61)
+#endif
+
+#if defined(BSP_USING_CAN3)
+    #define CAN3_TX_PORT                    (GPIO_PORT_C)
+    #define CAN3_TX_PIN                     (GPIO_PIN_06)
+    #define CAN3_TX_PIN_FUNC                (GPIO_FUNC_62)
+
+    #define CAN3_RX_PORT                    (GPIO_PORT_A)
+    #define CAN3_RX_PIN                     (GPIO_PIN_05)
+    #define CAN3_RX_PIN_FUNC                (GPIO_FUNC_63)
+#endif
+
+/************************* SPI port ***********************/
+#if defined(BSP_USING_SPI1)
+    #define SPI1_CS_PORT                (GPIO_PORT_B)
+    #define SPI1_CS_PIN                 (GPIO_PIN_12)
+
+    #define SPI1_SCK_PORT               (GPIO_PORT_B)
+    #define SPI1_SCK_PIN                (GPIO_PIN_13)
+    #define SPI1_SCK_FUNC               (GPIO_FUNC_6)
+
+    #define SPI1_MOSI_PORT              (GPIO_PORT_A)
+    #define SPI1_MOSI_PIN               (GPIO_PIN_07)
+    #define SPI1_MOSI_FUNC              (GPIO_FUNC_6)
+
+    #define SPI1_MISO_PORT              (GPIO_PORT_B)
+    #define SPI1_MISO_PIN               (GPIO_PIN_14)
+    #define SPI1_MISO_FUNC              (GPIO_FUNC_6)
+
+    #define SPI1_WP_PORT                (GPIO_PORT_B)
+    #define SPI1_WP_PIN                 (GPIO_PIN_10)
+
+    #define SPI1_HOLD_PORT              (GPIO_PORT_B)
+    #define SPI1_HOLD_PIN               (GPIO_PIN_11)
+#endif
+
+/************************ RTC/PM *****************************/
+#if defined(BSP_USING_RTC) || defined(RT_USING_PM)
+    #if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM)
+        #define XTAL32_PORT                     (GPIO_PORT_C)
+        #define XTAL32_IN_PIN                   (GPIO_PIN_14)
+        #define XTAL32_OUT_PIN                  (GPIO_PIN_15)
+    #endif
+#endif
+
+#if defined(RT_USING_PWM)
+    /***********  PWM_TMRA configure *********/
+    #if defined(BSP_USING_PWM_TMRA_1)
+        #if defined(BSP_USING_PWM_TMRA_1_CH1)
+            #define PWM_TMRA_1_CH1_PORT             (GPIO_PORT_A)
+            #define PWM_TMRA_1_CH1_PIN              (GPIO_PIN_08)
+            #define PWM_TMRA_1_CH1_PIN_FUNC         (GPIO_FUNC_4)
+        #endif
+        #if defined(BSP_USING_PWM_TMRA_1_CH2)
+            #define PWM_TMRA_1_CH2_PORT             (GPIO_PORT_A)
+            #define PWM_TMRA_1_CH2_PIN              (GPIO_PIN_09)
+            #define PWM_TMRA_1_CH2_PIN_FUNC         (GPIO_FUNC_4)
+        #endif
+        #if defined(BSP_USING_PWM_TMRA_1_CH3)
+            #define PWM_TMRA_1_CH3_PORT             (GPIO_PORT_A)
+            #define PWM_TMRA_1_CH3_PIN              (GPIO_PIN_10)
+            #define PWM_TMRA_1_CH3_PIN_FUNC         (GPIO_FUNC_4)
+        #endif
+        #if defined(BSP_USING_PWM_TMRA_1_CH4)
+            #define PWM_TMRA_1_CH4_PORT             (GPIO_PORT_A)
+            #define PWM_TMRA_1_CH4_PIN              (GPIO_PIN_11)
+            #define PWM_TMRA_1_CH4_PIN_FUNC         (GPIO_FUNC_4)
+        #endif
+    #endif
+
+    #if defined(BSP_USING_PWM_TMRA_2)
+        #if defined(BSP_USING_PWM_TMRA_2_CH1)
+            #define PWM_TMRA_2_CH1_PORT             (GPIO_PORT_A)
+            #define PWM_TMRA_2_CH1_PIN              (GPIO_PIN_00)
+            #define PWM_TMRA_2_CH1_PIN_FUNC         (GPIO_FUNC_4)
+        #endif
+        #if defined(BSP_USING_PWM_TMRA_2_CH2)
+            #define PWM_TMRA_2_CH2_PORT             (GPIO_PORT_A)
+            #define PWM_TMRA_2_CH2_PIN              (GPIO_PIN_01)
+            #define PWM_TMRA_2_CH2_PIN_FUNC         (GPIO_FUNC_4)
+        #endif
+        #if defined(BSP_USING_PWM_TMRA_2_CH3)
+            #define PWM_TMRA_2_CH3_PORT             (GPIO_PORT_A)
+            #define PWM_TMRA_2_CH3_PIN              (GPIO_PIN_02)
+            #define PWM_TMRA_2_CH3_PIN_FUNC         (GPIO_FUNC_4)
+        #endif
+        #if defined(BSP_USING_PWM_TMRA_2_CH4)
+            #define PWM_TMRA_2_CH4_PORT             (GPIO_PORT_A)
+            #define PWM_TMRA_2_CH4_PIN              (GPIO_PIN_03)
+            #define PWM_TMRA_2_CH4_PIN_FUNC         (GPIO_FUNC_4)
+        #endif
+    #endif
+
+    /***********  PWM_TMR4 configure *********/
+    #if defined(BSP_USING_PWM_TMR4_1)
+        #if defined(BSP_USING_PWM_TMR4_1_OUH)
+            #define PWM_TMR4_1_OUH_PORT             (GPIO_PORT_A)
+            #define PWM_TMR4_1_OUH_PIN              (GPIO_PIN_08)
+            #define PWM_TMR4_1_OUH_PIN_FUNC         (GPIO_FUNC_2)
+        #endif
+        #if defined(BSP_USING_PWM_TMR4_1_OUL)
+            #define PWM_TMR4_1_OUL_PORT             (GPIO_PORT_A)
+            #define PWM_TMR4_1_OUL_PIN              (GPIO_PIN_07)
+            #define PWM_TMR4_1_OUL_PIN_FUNC         (GPIO_FUNC_2)
+        #endif
+        #if defined(BSP_USING_PWM_TMR4_1_OVH)
+            #define PWM_TMR4_1_OVH_PORT             (GPIO_PORT_A)
+            #define PWM_TMR4_1_OVH_PIN              (GPIO_PIN_09)
+            #define PWM_TMR4_1_OVH_PIN_FUNC         (GPIO_FUNC_2)
+        #endif
+        #if defined(BSP_USING_PWM_TMR4_1_OVL)
+            #define PWM_TMR4_1_OVL_PORT             (GPIO_PORT_B)
+            #define PWM_TMR4_1_OVL_PIN              (GPIO_PIN_00)
+            #define PWM_TMR4_1_OVL_PIN_FUNC         (GPIO_FUNC_2)
+        #endif
+        #if defined(BSP_USING_PWM_TMR4_1_OWH)
+            #define PWM_TMR4_1_OWH_PORT             (GPIO_PORT_A)
+            #define PWM_TMR4_1_OWH_PIN              (GPIO_PIN_10)
+            #define PWM_TMR4_1_OWH_PIN_FUNC         (GPIO_FUNC_2)
+        #endif
+        #if defined(BSP_USING_PWM_TMR4_1_OWL)
+            #define PWM_TMR4_1_OWL_PORT             (GPIO_PORT_B)
+            #define PWM_TMR4_1_OWL_PIN              (GPIO_PIN_01)
+            #define PWM_TMR4_1_OWL_PIN_FUNC         (GPIO_FUNC_2)
+        #endif
+    #endif
+
+    /***********  PWM_TMR6 configure *********/
+    #if defined(BSP_USING_PWM_TMR6_1)
+        #if defined(BSP_USING_PWM_TMR6_1_A)
+            #define PWM_TMR6_1_A_PORT               (GPIO_PORT_A)
+            #define PWM_TMR6_1_A_PIN                (GPIO_PIN_08)
+            #define PWM_TMR6_1_A_PIN_FUNC           (GPIO_FUNC_3)
+        #endif
+        #if defined(BSP_USING_PWM_TMR6_1_B)
+            #define PWM_TMR6_1_B_PORT               (GPIO_PORT_A)
+            #define PWM_TMR6_1_B_PIN                (GPIO_PIN_07)
+            #define PWM_TMR6_1_B_PIN_FUNC           (GPIO_FUNC_3)
+        #endif
+    #endif
+
+#endif
+
+#if defined(BSP_USING_QSPI)
+    #ifndef BSP_QSPI_USING_SOFT_CS
+        /* QSSN */
+        #define QSPI_FLASH_CS_PORT              (GPIO_PORT_B)
+        #define QSPI_FLASH_CS_PIN               (GPIO_PIN_12)
+        #define QSPI_FLASH_CS_FUNC              (GPIO_FUNC_5)
+    #endif
+    /* QSCK */
+    #define QSPI_FLASH_SCK_PORT             (GPIO_PORT_B)
+    #define QSPI_FLASH_SCK_PIN              (GPIO_PIN_13)
+    #define QSPI_FLASH_SCK_FUNC             (GPIO_FUNC_5)
+    /* QSIO0 */
+    #define QSPI_FLASH_IO0_PORT             (GPIO_PORT_A)
+    #define QSPI_FLASH_IO0_PIN              (GPIO_PIN_07)
+    #define QSPI_FLASH_IO0_FUNC             (GPIO_FUNC_5)
+    /* QSIO1 */
+    #define QSPI_FLASH_IO1_PORT             (GPIO_PORT_B)
+    #define QSPI_FLASH_IO1_PIN              (GPIO_PIN_14)
+    #define QSPI_FLASH_IO1_FUNC             (GPIO_FUNC_5)
+    /* QSIO2 */
+    #define QSPI_FLASH_IO2_PORT             (GPIO_PORT_B)
+    #define QSPI_FLASH_IO2_PIN              (GPIO_PIN_10)
+    #define QSPI_FLASH_IO2_FUNC             (GPIO_FUNC_4)
+    /* QSIO3 */
+    #define QSPI_FLASH_IO3_PORT             (GPIO_PORT_B)
+    #define QSPI_FLASH_IO3_PIN              (GPIO_PIN_11)
+    #define QSPI_FLASH_IO3_FUNC             (GPIO_FUNC_4)
+#endif
+
+/*********** TMRA_PULSE_ENCODER configure *********/
+#if defined(RT_USING_PULSE_ENCODER)
+    #if defined(BSP_USING_TMRA_PULSE_ENCODER)
+        #if defined(BSP_USING_PULSE_ENCODER_TMRA_1)
+            #define PULSE_ENCODER_TMRA_1_A_PORT      (GPIO_PORT_A)
+            #define PULSE_ENCODER_TMRA_1_A_PIN       (GPIO_PIN_08)
+            #define PULSE_ENCODER_TMRA_1_A_PIN_FUNC  (GPIO_FUNC_4)
+            #define PULSE_ENCODER_TMRA_1_B_PORT      (GPIO_PORT_A)
+            #define PULSE_ENCODER_TMRA_1_B_PIN       (GPIO_PIN_09)
+            #define PULSE_ENCODER_TMRA_1_B_PIN_FUNC  (GPIO_FUNC_4)
+        #endif /* BSP_USING_PULSE_ENCODER_TMRA_1 */
+    #endif /* BSP_USING_TMRA_PULSE_ENCODER */
+
+    #if defined(BSP_USING_TMR6_PULSE_ENCODER)
+        #if defined(BSP_USING_PULSE_ENCODER_TMR6_1)
+            #define PULSE_ENCODER_TMR6_1_A_PORT      (GPIO_PORT_A)
+            #define PULSE_ENCODER_TMR6_1_A_PIN       (GPIO_PIN_08)
+            #define PULSE_ENCODER_TMR6_1_A_PIN_FUNC  (GPIO_FUNC_3)
+            #define PULSE_ENCODER_TMR6_1_B_PORT      (GPIO_PORT_A)
+            #define PULSE_ENCODER_TMR6_1_B_PIN       (GPIO_PIN_07)
+            #define PULSE_ENCODER_TMR6_1_B_PIN_FUNC  (GPIO_FUNC_3)
+        #endif /* BSP_USING_PULSE_ENCODER_TMR6_1 */
+    #endif /* BSP_USING_TMR6_PULSE_ENCODER */
+#endif /* RT_USING_PULSE_ENCODER */
+
+#endif
+

bsp/hc32/ev_hc32f472_lqfp100/board/config/adc_config.h

@@ -0,0 +1,155 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2024-02-20     CDT          first version
+ */
+
+#ifndef __ADC_CONFIG_H__
+#define __ADC_CONFIG_H__
+
+#include <rtthread.h>
+#include "irq_config.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_ADC1
+#ifndef ADC1_INIT_PARAMS
+#define ADC1_INIT_PARAMS                                                        \
+    {                                                                           \
+       .name                            = "adc1",                               \
+       .vref                            = 3300,                                 \
+       .resolution                      = ADC_RESOLUTION_12BIT,                 \
+       .data_align                      = ADC_DATAALIGN_RIGHT,                  \
+       .eoc_poll_time_max               = 100,                                  \
+       .hard_trig_enable                = RT_FALSE,                             \
+       .hard_trig_src                   = ADC_HARDTRIG_EVT0,                    \
+       .internal_trig0_comtrg0_enable   = RT_FALSE,                             \
+       .internal_trig0_comtrg1_enable   = RT_FALSE,                             \
+       .internal_trig0_sel              = EVT_SRC_TMR0_1_CMP_A,                 \
+       .internal_trig1_comtrg0_enable   = RT_FALSE,                             \
+       .internal_trig1_comtrg1_enable   = RT_FALSE,                             \
+       .internal_trig1_sel              = EVT_SRC_MAX,                          \
+       .continue_conv_mode_enable       = RT_FALSE,                             \
+       .data_reg_auto_clear             = RT_TRUE,                              \
+    }
+#endif /* ADC1_INIT_PARAMS */
+
+#if defined (BSP_ADC1_USING_DMA)
+#ifndef ADC1_EOCA_DMA_CONFIG
+#define ADC1_EOCA_DMA_CONFIG                                                    \
+    {                                                                           \
+        .Instance                       = ADC1_EOCA_DMA_INSTANCE,               \
+        .channel                        = ADC1_EOCA_DMA_CHANNEL,                \
+        .clock                          = ADC1_EOCA_DMA_CLOCK,                  \
+        .trigger_select                 = ADC1_EOCA_DMA_TRIG_SELECT,            \
+        .trigger_event                  = EVT_SRC_ADC1_EOCA,                    \
+        .flag                           = ADC1_EOCA_DMA_TRANS_FLAG,             \
+        .irq_config                     =                                       \
+        {                                                                       \
+            .irq_num                    = ADC1_EOCA_DMA_IRQn,                   \
+            .irq_prio                   = ADC1_EOCA_DMA_INT_PRIO,               \
+            .int_src                    = ADC1_EOCA_DMA_INT_SRC,                \
+        },                                                                      \
+    }
+#endif /* ADC1_EOCA_DMA_CONFIG */
+#endif /* BSP_ADC1_USING_DMA */
+#endif /* BSP_USING_ADC1 */
+
+#ifdef BSP_USING_ADC2
+#ifndef ADC2_INIT_PARAMS
+#define ADC2_INIT_PARAMS                                                        \
+    {                                                                           \
+       .name                            = "adc2",                               \
+       .vref                            = 3300,                                 \
+       .resolution                      = ADC_RESOLUTION_12BIT,                 \
+       .data_align                      = ADC_DATAALIGN_RIGHT,                  \
+       .eoc_poll_time_max               = 100,                                  \
+       .hard_trig_enable                = RT_FALSE,                             \
+       .hard_trig_src                   = ADC_HARDTRIG_EVT0,                    \
+       .internal_trig0_comtrg0_enable   = RT_FALSE,                             \
+       .internal_trig0_comtrg1_enable   = RT_FALSE,                             \
+       .internal_trig0_sel              = EVT_SRC_TMR0_1_CMP_A,                 \
+       .internal_trig1_comtrg0_enable   = RT_FALSE,                             \
+       .internal_trig1_comtrg1_enable   = RT_FALSE,                             \
+       .internal_trig1_sel              = EVT_SRC_MAX,                          \
+       .continue_conv_mode_enable       = RT_FALSE,                             \
+       .data_reg_auto_clear             = RT_TRUE,                              \
+    }
+#endif /* ADC2_INIT_PARAMS */
+
+#if defined (BSP_ADC2_USING_DMA)
+#ifndef ADC2_EOCA_DMA_CONFIG
+#define ADC2_EOCA_DMA_CONFIG                                                    \
+    {                                                                           \
+        .Instance                       = ADC2_EOCA_DMA_INSTANCE,               \
+        .channel                        = ADC2_EOCA_DMA_CHANNEL,                \
+        .clock                          = ADC2_EOCA_DMA_CLOCK,                  \
+        .trigger_select                 = ADC2_EOCA_DMA_TRIG_SELECT,            \
+        .trigger_event                  = EVT_SRC_ADC2_EOCA,                    \
+        .flag                           = ADC2_EOCA_DMA_TRANS_FLAG,             \
+        .irq_config                     =                                       \
+        {                                                                       \
+            .irq_num                    = ADC2_EOCA_DMA_IRQn,                   \
+            .irq_prio                   = ADC2_EOCA_DMA_INT_PRIO,               \
+            .int_src                    = ADC2_EOCA_DMA_INT_SRC,                \
+        },                                                                      \
+    }
+#endif /* ADC2_EOCA_DMA_CONFIG */
+#endif /* BSP_ADC2_USING_DMA */
+#endif /* BSP_USING_ADC2 */
+
+#ifdef BSP_USING_ADC3
+#ifndef ADC3_INIT_PARAMS
+#define ADC3_INIT_PARAMS                                                        \
+    {                                                                           \
+       .name                            = "adc3",                               \
+       .vref                            = 3300,                                 \
+       .resolution                      = ADC_RESOLUTION_12BIT,                 \
+       .data_align                      = ADC_DATAALIGN_RIGHT,                  \
+       .eoc_poll_time_max               = 100,                                  \
+       .hard_trig_enable                = RT_FALSE,                             \
+       .hard_trig_src                   = ADC_HARDTRIG_EVT0,                    \
+       .internal_trig0_comtrg0_enable   = RT_FALSE,                             \
+       .internal_trig0_comtrg1_enable   = RT_FALSE,                             \
+       .internal_trig0_sel              = EVT_SRC_TMR0_1_CMP_A,                 \
+       .internal_trig1_comtrg0_enable   = RT_FALSE,                             \
+       .internal_trig1_comtrg1_enable   = RT_FALSE,                             \
+       .internal_trig1_sel              = EVT_SRC_MAX,                          \
+       .continue_conv_mode_enable       = RT_FALSE,                             \
+       .data_reg_auto_clear             = RT_TRUE,                              \
+    }
+#endif /* ADC3_INIT_PARAMS */
+
+#if defined (BSP_ADC3_USING_DMA)
+#ifndef ADC3_EOCA_DMA_CONFIG
+#define ADC3_EOCA_DMA_CONFIG                                                    \
+    {                                                                           \
+        .Instance                       = ADC3_EOCA_DMA_INSTANCE,               \
+        .channel                        = ADC3_EOCA_DMA_CHANNEL,                \
+        .clock                          = ADC3_EOCA_DMA_CLOCK,                  \
+        .trigger_select                 = ADC3_EOCA_DMA_TRIG_SELECT,            \
+        .trigger_event                  = EVT_SRC_ADC3_EOCA,                    \
+        .flag                           = ADC3_EOCA_DMA_TRANS_FLAG,             \
+        .irq_config                     =                                       \
+        {                                                                       \
+            .irq_num                    = ADC3_EOCA_DMA_IRQn,                   \
+            .irq_prio                   = ADC3_EOCA_DMA_INT_PRIO,               \
+            .int_src                    = ADC3_EOCA_DMA_INT_SRC,                \
+        },                                                                      \
+    }
+#endif /* ADC3_EOCA_DMA_CONFIG */
+#endif /* BSP_ADC3_USING_DMA */
+#endif /* BSP_USING_ADC3 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ADC_CONFIG_H__ */

bsp/hc32/ev_hc32f472_lqfp100/board/config/can_config.h

@@ -0,0 +1,139 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2024-02-20     CDT          first version
+ */
+
+#ifndef __CAN_CONFIG_H__
+#define __CAN_CONFIG_H__
+
+#include <rtthread.h>
+#include "irq_config.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_CAN1
+#define CAN1_CLOCK_SEL                  (CAN_CLOCK_SRC_40M)
+#ifdef RT_CAN_USING_CANFD
+#define CAN1_CANFD_MODE                 (CAN_FD_MD_ISO)
+#endif
+#define CAN1_NAME                       ("can1")
+#ifndef CAN1_INIT_PARAMS
+#define CAN1_INIT_PARAMS                                    \
+    {                                                       \
+       .name = CAN1_NAME,                                   \
+       .single_trans_mode = RT_FALSE                        \
+    }
+#endif /* CAN1_INIT_PARAMS */
+#endif /* BSP_USING_CAN1 */
+
+#ifdef BSP_USING_CAN2
+#define CAN2_CLOCK_SEL                  (CAN_CLOCK_SRC_40M)
+#ifdef RT_CAN_USING_CANFD
+#define CAN2_CANFD_MODE                 (CAN_FD_MD_ISO)
+#endif
+#define CAN2_NAME                       ("can2")
+#ifndef CAN2_INIT_PARAMS
+#define CAN2_INIT_PARAMS                                    \
+    {                                                       \
+       .name = CAN2_NAME,                                   \
+       .single_trans_mode = RT_FALSE                        \
+    }
+#endif /* CAN2_INIT_PARAMS */
+#endif /* BSP_USING_CAN2 */
+
+/* Bit time config
+  Restrictions: u32TimeSeg1 >= u32TimeSeg2 + 1, u32TimeSeg2 >= u32SJW.
+
+  Baudrate = CANClock/(u32Prescaler*(u32TimeSeg1 + u32TimeSeg2))
+  TQ = u32Prescaler / CANClock.
+  Bit time = (u32TimeSeg2 + u32TimeSeg2) x TQ.
+
+  The following bit time configures are based on CAN Clock 40M
+*/
+#define CAN_BIT_TIME_CONFIG_1M_BAUD                         \
+    {                                                       \
+        .u32Prescaler = 2,                                  \
+        .u32TimeSeg1 = 16,                                  \
+        .u32TimeSeg2 = 4,                                   \
+        .u32SJW = 4                                         \
+    }
+
+#define CAN_BIT_TIME_CONFIG_800K_BAUD                       \
+    {                                                       \
+        .u32Prescaler = 2,                                  \
+        .u32TimeSeg1 = 20,                                  \
+        .u32TimeSeg2 = 5,                                   \
+        .u32SJW = 4                                         \
+    }
+
+#define CAN_BIT_TIME_CONFIG_500K_BAUD                       \
+    {                                                       \
+        .u32Prescaler = 4,                                  \
+        .u32TimeSeg1 = 16,                                  \
+        .u32TimeSeg2 = 4,                                   \
+        .u32SJW = 4                                         \
+    }
+
+#define CAN_BIT_TIME_CONFIG_250K_BAUD                       \
+    {                                                       \
+        .u32Prescaler = 8,                                  \
+        .u32TimeSeg1 = 16,                                  \
+        .u32TimeSeg2 = 4,                                   \
+        .u32SJW = 4                                         \
+    }
+
+#define CAN_BIT_TIME_CONFIG_125K_BAUD                       \
+    {                                                       \
+        .u32Prescaler = 16,                                 \
+        .u32TimeSeg1 = 16,                                  \
+        .u32TimeSeg2 = 4,                                   \
+        .u32SJW = 4                                         \
+    }
+
+#define CAN_BIT_TIME_CONFIG_100K_BAUD                       \
+    {                                                       \
+        .u32Prescaler = 20,                                 \
+        .u32TimeSeg1 = 16,                                  \
+        .u32TimeSeg2 = 4,                                   \
+        .u32SJW = 4                                         \
+    }
+
+#define CAN_BIT_TIME_CONFIG_50K_BAUD                        \
+    {                                                       \
+        .u32Prescaler = 40,                                 \
+        .u32TimeSeg1 = 16,                                  \
+        .u32TimeSeg2 = 4,                                   \
+        .u32SJW = 4                                         \
+    }
+
+#define CAN_BIT_TIME_CONFIG_20K_BAUD                        \
+    {                                                       \
+        .u32Prescaler = 100,                                \
+        .u32TimeSeg1 = 16,                                  \
+        .u32TimeSeg2 = 4,                                   \
+        .u32SJW = 4                                         \
+    }
+
+#define CAN_BIT_TIME_CONFIG_10K_BAUD                        \
+    {                                                       \
+        .u32Prescaler = 200,                                \
+        .u32TimeSeg1 = 16,                                  \
+        .u32TimeSeg2 = 4,                                   \
+        .u32SJW = 4                                         \
+    }
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CAN_CONFIG_H__ */
+
+

bsp/hc32/ev_hc32f472_lqfp100/board/config/dac_config.h

@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2024-02-20     CDT          first version
+ */
+
+#ifndef __DAC_CONFIG_H__
+#define __DAC_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_DAC1
+#ifndef DAC1_INIT_PARAMS
+#define DAC1_INIT_PARAMS                                                    \
+    {                                                                       \
+       .name                      = "dac1",                                 \
+    }
+#endif /* DAC1_INIT_PARAMS */
+#endif /* BSP_USING_DAC1 */
+
+#ifdef BSP_USING_DAC2
+#ifndef DAC2_INIT_PARAMS
+#define DAC2_INIT_PARAMS                                                    \
+    {                                                                       \
+       .name                      = "dac2",                                 \
+    }
+#endif /* DAC2_INIT_PARAMS */
+#endif /* BSP_USING_DAC2 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __DAC_CONFIG_H__ */

bsp/hc32/ev_hc32f472_lqfp100/board/config/dma_config.h

@@ -0,0 +1,273 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2024-02-20     CDT          first version
+ */
+
+#ifndef __DMA_CONFIG_H__
+#define __DMA_CONFIG_H__
+
+#include <rtthread.h>
+#include "irq_config.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* DMA1 ch0 */
+#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
+#define SPI1_RX_DMA_INSTANCE            CM_DMA1
+#define SPI1_RX_DMA_CHANNEL             DMA_CH0
+#define SPI1_RX_DMA_CLOCK               (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define SPI1_RX_DMA_TRIG_SELECT         AOS_DMA1_0
+#define SPI1_RX_DMA_TRANS_FLAG          DMA_FLAG_TC_CH0
+#define SPI1_RX_DMA_IRQn                BSP_DMA1_CH0_IRQ_NUM
+#define SPI1_RX_DMA_INT_PRIO            BSP_DMA1_CH0_IRQ_PRIO
+#define SPI1_RX_DMA_INT_SRC             INT_SRC_DMA1_TC0
+
+#elif defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE)
+#define SPI3_RX_DMA_INSTANCE            CM_DMA1
+#define SPI3_RX_DMA_CHANNEL             DMA_CH0
+#define SPI3_RX_DMA_CLOCK               (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define SPI3_RX_DMA_TRIG_SELECT         AOS_DMA1_0
+#define SPI3_RX_DMA_TRANS_FLAG          DMA_FLAG_TC_CH0
+#define SPI3_RX_DMA_IRQn                BSP_DMA1_CH0_IRQ_NUM
+#define SPI3_RX_DMA_INT_PRIO            BSP_DMA1_CH0_IRQ_PRIO
+#define SPI3_RX_DMA_INT_SRC             INT_SRC_DMA1_TC0
+
+#elif defined(BSP_I2C1_TX_USING_DMA) && !defined(I2C1_TX_DMA_INSTANCE)
+#define I2C1_TX_DMA_INSTANCE            CM_DMA1
+#define I2C1_TX_DMA_CHANNEL             DMA_CH0
+#define I2C1_TX_DMA_CLOCK               (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define I2C1_TX_DMA_TRIG_SELECT         AOS_DMA1_0
+#define I2C1_TX_DMA_TRANS_FLAG          DMA_FLAG_TC_CH0
+#define I2C1_TX_DMA_IRQn                BSP_DMA1_CH0_IRQ_NUM
+#define I2C1_TX_DMA_INT_PRIO            BSP_DMA1_CH0_IRQ_PRIO
+#define I2C1_TX_DMA_INT_SRC             INT_SRC_DMA1_TC0
+#endif
+
+/* DMA1 ch1 */
+#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
+#define SPI1_TX_DMA_INSTANCE            CM_DMA1
+#define SPI1_TX_DMA_CHANNEL             DMA_CH1
+#define SPI1_TX_DMA_CLOCK               (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define SPI1_TX_DMA_TRIG_SELECT         AOS_DMA1_1
+#define SPI1_TX_DMA_TRANS_FLAG          DMA_FLAG_TC_CH1
+#define SPI1_TX_DMA_IRQn                BSP_DMA1_CH1_IRQ_NUM
+#define SPI1_TX_DMA_INT_PRIO            BSP_DMA1_CH1_IRQ_PRIO
+#define SPI1_TX_DMA_INT_SRC             INT_SRC_DMA1_TC1
+
+#elif defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE)
+#define SPI3_TX_DMA_INSTANCE            CM_DMA1
+#define SPI3_TX_DMA_CHANNEL             DMA_CH1
+#define SPI3_TX_DMA_CLOCK               (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define SPI3_TX_DMA_TRIG_SELECT         AOS_DMA1_1
+#define SPI3_TX_DMA_TRANS_FLAG          DMA_FLAG_TC_CH1
+#define SPI3_TX_DMA_IRQn                BSP_DMA1_CH1_IRQ_NUM
+#define SPI3_TX_DMA_INT_PRIO            BSP_DMA1_CH1_IRQ_PRIO
+#define SPI3_TX_DMA_INT_SRC             INT_SRC_DMA1_TC1
+
+#elif defined(BSP_I2C1_RX_USING_DMA) && !defined(I2C1_RX_DMA_INSTANCE)
+#define I2C1_RX_DMA_INSTANCE            CM_DMA1
+#define I2C1_RX_DMA_CHANNEL             DMA_CH1
+#define I2C1_RX_DMA_CLOCK               (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define I2C1_RX_DMA_TRIG_SELECT         AOS_DMA1_1
+#define I2C1_RX_DMA_TRANS_FLAG          DMA_FLAG_TC_CH1
+#define I2C1_RX_DMA_IRQn                BSP_DMA1_CH1_IRQ_NUM
+#define I2C1_RX_DMA_INT_PRIO            BSP_DMA1_CH1_IRQ_PRIO
+#define I2C1_RX_DMA_INT_SRC             INT_SRC_DMA1_TC1
+#endif
+
+/* DMA1 ch2 */
+#if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE)
+#define SPI2_RX_DMA_INSTANCE            CM_DMA1
+#define SPI2_RX_DMA_CHANNEL             DMA_CH2
+#define SPI2_RX_DMA_CLOCK               (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define SPI2_RX_DMA_TRIG_SELECT         AOS_DMA1_2
+#define SPI2_RX_DMA_TRANS_FLAG          DMA_FLAG_TC_CH2
+#define SPI2_RX_DMA_IRQn                BSP_DMA1_CH2_IRQ_NUM
+#define SPI2_RX_DMA_INT_PRIO            BSP_DMA1_CH2_IRQ_PRIO
+#define SPI2_RX_DMA_INT_SRC             INT_SRC_DMA1_TC2
+
+#elif defined(BSP_I2C2_TX_USING_DMA) && !defined(I2C2_TX_DMA_INSTANCE)
+#define I2C2_TX_DMA_INSTANCE            CM_DMA1
+#define I2C2_TX_DMA_CHANNEL             DMA_CH2
+#define I2C2_TX_DMA_CLOCK               (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define I2C2_TX_DMA_TRIG_SELECT         AOS_DMA1_2
+#define I2C2_TX_DMA_TRANS_FLAG          DMA_FLAG_TC_CH2
+#define I2C2_TX_DMA_IRQn                BSP_DMA1_CH2_IRQ_NUM
+#define I2C2_TX_DMA_INT_PRIO            BSP_DMA1_CH2_IRQ_PRIO
+#define I2C2_TX_DMA_INT_SRC             INT_SRC_DMA1_TC2
+#endif
+
+/* DMA1 ch3 */
+#if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE)
+#define SPI2_TX_DMA_INSTANCE            CM_DMA1
+#define SPI2_TX_DMA_CHANNEL             DMA_CH3
+#define SPI2_TX_DMA_CLOCK               (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define SPI2_TX_DMA_TRIG_SELECT         AOS_DMA1_3
+#define SPI2_TX_DMA_TRANS_FLAG          DMA_FLAG_TC_CH3
+#define SPI2_TX_DMA_IRQn                BSP_DMA1_CH3_IRQ_NUM
+#define SPI2_TX_DMA_INT_PRIO            BSP_DMA1_CH3_IRQ_PRIO
+#define SPI2_TX_DMA_INT_SRC             INT_SRC_DMA1_TC3
+
+
+#elif defined(BSP_I2C2_RX_USING_DMA) && !defined(I2C2_RX_DMA_INSTANCE)
+#define I2C2_RX_DMA_INSTANCE            CM_DMA1
+#define I2C2_RX_DMA_CHANNEL             DMA_CH3
+#define I2C2_RX_DMA_CLOCK               (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define I2C2_RX_DMA_TRIG_SELECT         AOS_DMA1_3
+#define I2C2_RX_DMA_TRANS_FLAG          DMA_FLAG_TC_CH3
+#define I2C2_RX_DMA_IRQn                BSP_DMA1_CH3_IRQ_NUM
+#define I2C2_RX_DMA_INT_PRIO            BSP_DMA1_CH3_IRQ_PRIO
+#define I2C2_RX_DMA_INT_SRC             INT_SRC_DMA1_TC3
+
+#elif defined(BSP_ADC1_USING_DMA) && !defined(ADC1_EOCA_DMA_INSTANCE)
+#define ADC1_EOCA_DMA_INSTANCE          CM_DMA1
+#define ADC1_EOCA_DMA_CHANNEL           DMA_CH3
+#define ADC1_EOCA_DMA_CLOCK             (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define ADC1_EOCA_DMA_TRIG_SELECT       AOS_DMA1_3
+#define ADC1_EOCA_DMA_TRANS_FLAG        DMA_FLAG_TC_CH3
+#define ADC1_EOCA_DMA_IRQn              BSP_DMA1_CH3_IRQ_NUM
+#define ADC1_EOCA_DMA_INT_PRIO          BSP_DMA1_CH3_IRQ_PRIO
+#define ADC1_EOCA_DMA_INT_SRC           INT_SRC_DMA1_TC3
+
+#endif
+
+/* DMA1 ch4 */
+#if defined(BSP_UART5_RX_USING_DMA) && !defined(UART5_RX_DMA_INSTANCE)
+#define UART5_RX_DMA_INSTANCE           CM_DMA1
+#define UART5_RX_DMA_CHANNEL            DMA_CH4
+#define UART5_RX_DMA_CLOCK              (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define UART5_RX_DMA_TRIG_SELECT        AOS_DMA1_4
+#define UART5_RX_DMA_TRANS_FLAG         DMA_FLAG_TC_CH4
+#define UART5_RX_DMA_IRQn               BSP_DMA1_CH4_IRQ_NUM
+#define UART5_RX_DMA_INT_PRIO           BSP_DMA1_CH4_IRQ_PRIO
+#define UART5_RX_DMA_INT_SRC            INT_SRC_DMA1_TC4
+
+#elif defined(BSP_ADC2_USING_DMA) && !defined(ADC2_EOCA_DMA_INSTANCE)
+#define ADC2_EOCA_DMA_INSTANCE          CM_DMA1
+#define ADC2_EOCA_DMA_CHANNEL           DMA_CH4
+#define ADC2_EOCA_DMA_CLOCK             (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define ADC2_EOCA_DMA_TRIG_SELECT       AOS_DMA1_4
+#define ADC2_EOCA_DMA_TRANS_FLAG        DMA_FLAG_TC_CH4
+#define ADC2_EOCA_DMA_IRQn              BSP_DMA1_CH4_IRQ_NUM
+#define ADC2_EOCA_DMA_INT_PRIO          BSP_DMA1_CH4_IRQ_PRIO
+#define ADC2_EOCA_DMA_INT_SRC           INT_SRC_DMA1_TC4
+#endif
+
+/* DMA1 ch5 */
+#if defined(BSP_UART5_TX_USING_DMA) && !defined(UART5_TX_DMA_INSTANCE)
+#define UART5_TX_DMA_INSTANCE           CM_DMA1
+#define UART5_TX_DMA_CHANNEL            DMA_CH5
+#define UART5_TX_DMA_CLOCK              (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define UART5_TX_DMA_TRIG_SELECT        AOS_DMA1_5
+#define UART5_TX_DMA_TRANS_FLAG         DMA_FLAG_TC_CH5
+#define UART5_TX_DMA_IRQn               BSP_DMA1_CH5_IRQ_NUM
+#define UART5_TX_DMA_INT_PRIO           BSP_DMA1_CH5_IRQ_PRIO
+#define UART5_TX_DMA_INT_SRC            INT_SRC_DMA1_TC5
+
+#elif defined(BSP_ADC3_USING_DMA) && !defined(ADC3_EOCA_DMA_INSTANCE)
+#define ADC3_EOCA_DMA_INSTANCE          CM_DMA1
+#define ADC3_EOCA_DMA_CHANNEL           DMA_CH5
+#define ADC3_EOCA_DMA_CLOCK             (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
+#define ADC3_EOCA_DMA_TRIG_SELECT       AOS_DMA1_5
+#define ADC3_EOCA_DMA_TRANS_FLAG        DMA_FLAG_TC_CH5
+#define ADC3_EOCA_DMA_IRQn              BSP_DMA1_CH5_IRQ_NUM
+#define ADC3_EOCA_DMA_INT_PRIO          BSP_DMA1_CH5_IRQ_PRIO
+#define ADC3_EOCA_DMA_INT_SRC           INT_SRC_DMA1_TC5
+#endif
+
+/* DMA2 ch0 */
+#if defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
+#define UART1_RX_DMA_INSTANCE           CM_DMA2
+#define UART1_RX_DMA_CHANNEL            DMA_CH0
+#define UART1_RX_DMA_CLOCK              (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
+#define UART1_RX_DMA_TRIG_SELECT        AOS_DMA2_0
+#define UART1_RX_DMA_TRANS_FLAG         DMA_FLAG_TC_CH0
+#define UART1_RX_DMA_IRQn               BSP_DMA2_CH0_IRQ_NUM
+#define UART1_RX_DMA_INT_PRIO           BSP_DMA2_CH0_IRQ_PRIO
+#define UART1_RX_DMA_INT_SRC            INT_SRC_DMA2_TC0
+
+#elif defined(BSP_QSPI_USING_DMA) && !defined(QSPI_DMA_INSTANCE)
+#define QSPI_DMA_INSTANCE               CM_DMA2
+#define QSPI_DMA_CHANNEL                DMA_CH0
+#define QSPI_DMA_CLOCK                  (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
+#define QSPI_DMA_TRIG_SELECT            AOS_DMA2_0
+#define QSPI_DMA_TRANS_FLAG             DMA_FLAG_TC_CH0
+#define QSPI_DMA_IRQn                   BSP_DMA2_CH0_IRQ_NUM
+#define QSPI_DMA_INT_PRIO               BSP_DMA2_CH0_IRQ_PRIO
+#define QSPI_DMA_INT_SRC                INT_SRC_DMA2_TC0
+#endif
+
+/* DMA2 ch1 */
+#if defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_INSTANCE)
+#define UART1_TX_DMA_INSTANCE           CM_DMA2
+#define UART1_TX_DMA_CHANNEL            DMA_CH1
+#define UART1_TX_DMA_CLOCK              (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
+#define UART1_TX_DMA_TRIG_SELECT        AOS_DMA2_1
+#define UART1_TX_DMA_TRANS_FLAG         DMA_FLAG_TC_CH1
+#define UART1_TX_DMA_IRQn               BSP_DMA2_CH1_IRQ_NUM
+#define UART1_TX_DMA_INT_PRIO           BSP_DMA2_CH1_IRQ_PRIO
+#define UART1_TX_DMA_INT_SRC            INT_SRC_DMA2_TC1
+#endif
+
+/* DMA2 ch2 */
+#if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE)
+#define UART2_RX_DMA_INSTANCE           CM_DMA2
+#define UART2_RX_DMA_CHANNEL            DMA_CH2
+#define UART2_RX_DMA_CLOCK              (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
+#define UART2_RX_DMA_TRIG_SELECT        AOS_DMA2_2
+#define UART2_RX_DMA_TRANS_FLAG         DMA_FLAG_TC_CH2
+#define UART2_RX_DMA_IRQn               BSP_DMA2_CH2_IRQ_NUM
+#define UART2_RX_DMA_INT_PRIO           BSP_DMA2_CH2_IRQ_PRIO
+#define UART2_RX_DMA_INT_SRC            INT_SRC_DMA2_TC2
+#endif
+
+/* DMA2 ch3 */
+#if defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_INSTANCE)
+#define UART2_TX_DMA_INSTANCE           CM_DMA2
+#define UART2_TX_DMA_CHANNEL            DMA_CH3
+#define UART2_TX_DMA_CLOCK              (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
+#define UART2_TX_DMA_TRIG_SELECT        AOS_DMA2_3
+#define UART2_TX_DMA_TRANS_FLAG         DMA_FLAG_TC_CH3
+#define UART2_TX_DMA_IRQn               BSP_DMA2_CH3_IRQ_NUM
+#define UART2_TX_DMA_INT_PRIO           BSP_DMA2_CH3_IRQ_PRIO
+#define UART2_TX_DMA_INT_SRC            INT_SRC_DMA2_TC3
+#endif
+
+/* DMA2 ch4 */
+#if defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA_INSTANCE)
+#define UART4_RX_DMA_INSTANCE           CM_DMA2
+#define UART4_RX_DMA_CHANNEL            DMA_CH4
+#define UART4_RX_DMA_CLOCK              (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
+#define UART4_RX_DMA_TRIG_SELECT        AOS_DMA2_4
+#define UART4_RX_DMA_TRANS_FLAG         DMA_FLAG_TC_CH4
+#define UART4_RX_DMA_IRQn               BSP_DMA2_CH4_IRQ_NUM
+#define UART4_RX_DMA_INT_PRIO           BSP_DMA2_CH4_IRQ_PRIO
+#define UART4_RX_DMA_INT_SRC            INT_SRC_DMA2_TC4
+#endif
+
+/* DMA2 ch5 */
+#if defined(BSP_UART4_TX_USING_DMA) && !defined(UART4_TX_DMA_INSTANCE)
+#define UART4_TX_DMA_INSTANCE           CM_DMA2
+#define UART4_TX_DMA_CHANNEL            DMA_CH5
+#define UART4_TX_DMA_CLOCK              (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
+#define UART4_TX_DMA_TRIG_SELECT        AOS_DMA2_5
+#define UART4_TX_DMA_TRANS_FLAG         DMA_FLAG_TC_CH5
+#define UART4_TX_DMA_IRQn               BSP_DMA2_CH5_IRQ_NUM
+#define UART4_TX_DMA_INT_PRIO           BSP_DMA2_CH5_IRQ_PRIO
+#define UART4_TX_DMA_INT_SRC            INT_SRC_DMA2_TC5
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __DMA_CONFIG_H__ */

bsp/hc32/ev_hc32f472_lqfp100/board/config/gpio_config.h

@@ -0,0 +1,176 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2024-02-20     CDT          first version
+ */
+
+#ifndef __GPIO_CONFIG_H__
+#define __GPIO_CONFIG_H__
+
+#include <rtthread.h>
+#include "irq_config.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#if defined(RT_USING_PIN)
+
+#ifndef EXTINT0_IRQ_CONFIG
+#define EXTINT0_IRQ_CONFIG                                  \
+    {                                                       \
+        .irq_num    = BSP_EXTINT0_IRQ_NUM,                  \
+        .irq_prio   = BSP_EXTINT0_IRQ_PRIO,                 \
+        .int_src    = INT_SRC_PORT_EIRQ0,                   \
+    }
+#endif /* EXTINT1_IRQ_CONFIG */
+
+#ifndef EXTINT1_IRQ_CONFIG
+#define EXTINT1_IRQ_CONFIG                                  \
+    {                                                       \
+        .irq_num    = BSP_EXTINT1_IRQ_NUM,                  \
+        .irq_prio   = BSP_EXTINT1_IRQ_PRIO,                 \
+        .int_src    = INT_SRC_PORT_EIRQ1,                   \
+    }
+#endif /* EXTINT1_IRQ_CONFIG */
+
+#ifndef EXTINT2_IRQ_CONFIG
+#define EXTINT2_IRQ_CONFIG                                  \
+    {                                                       \
+        .irq_num    = BSP_EXTINT2_IRQ_NUM,                  \
+        .irq_prio   = BSP_EXTINT2_IRQ_PRIO,                 \
+        .int_src    = INT_SRC_PORT_EIRQ2,                   \
+    }
+#endif /* EXTINT2_IRQ_CONFIG */
+
+#ifndef EXTINT3_IRQ_CONFIG
+#define EXTINT3_IRQ_CONFIG                                  \
+    {                                                       \
+        .irq_num    = BSP_EXTINT3_IRQ_NUM,                  \
+        .irq_prio   = BSP_EXTINT3_IRQ_PRIO,                 \
+        .int_src    = INT_SRC_PORT_EIRQ3,                   \
+    }
+#endif /* EXTINT3_IRQ_CONFIG */
+
+#ifndef EXTINT4_IRQ_CONFIG
+#define EXTINT4_IRQ_CONFIG                                  \
+    {                                                       \
+        .irq_num    = BSP_EXTINT4_IRQ_NUM,                  \
+        .irq_prio   = BSP_EXTINT4_IRQ_PRIO,                 \
+        .int_src    = INT_SRC_PORT_EIRQ4,                   \
+    }
+#endif /* EXTINT4_IRQ_CONFIG */
+
+#ifndef EXTINT5_IRQ_CONFIG
+#define EXTINT5_IRQ_CONFIG                                  \
+    {                                                       \
+        .irq_num    = BSP_EXTINT5_IRQ_NUM,                  \
+        .irq_prio   = BSP_EXTINT5_IRQ_PRIO,                 \
+        .int_src    = INT_SRC_PORT_EIRQ5,                   \
+    }
+#endif /* EXTINT5_IRQ_CONFIG */
+
+#ifndef EXTINT6_IRQ_CONFIG
+#define EXTINT6_IRQ_CONFIG                                  \
+    {                                                       \
+        .irq_num    = BSP_EXTINT6_IRQ_NUM,                  \
+        .irq_prio   = BSP_EXTINT6_IRQ_PRIO,                 \
+        .int_src    = INT_SRC_PORT_EIRQ6,                   \
+    }
+#endif /* EXTINT6_IRQ_CONFIG */
+
+#ifndef EXTINT7_IRQ_CONFIG
+#define EXTINT7_IRQ_CONFIG                                  \
+    {                                                       \
+        .irq_num    = BSP_EXTINT7_IRQ_NUM,                  \
+        .irq_prio   = BSP_EXTINT7_IRQ_PRIO,                 \
+        .int_src    = INT_SRC_PORT_EIRQ7,                   \
+    }
+#endif /* EXTINT7_IRQ_CONFIG */
+
+#ifndef EXTINT8_IRQ_CONFIG
+#define EXTINT8_IRQ_CONFIG                                  \
+    {                                                       \
+        .irq_num    = BSP_EXTINT8_IRQ_NUM,                  \
+        .irq_prio   = BSP_EXTINT8_IRQ_PRIO,                 \
+        .int_src    = INT_SRC_PORT_EIRQ8,                   \
+    }
+#endif /* EXTINT8_IRQ_CONFIG */
+
+#ifndef EXTINT9_IRQ_CONFIG
+#define EXTINT9_IRQ_CONFIG                                  \
+    {                                                       \
+        .irq_num    = BSP_EXTINT9_IRQ_NUM,                  \
+        .irq_prio   = BSP_EXTINT9_IRQ_PRIO,                 \
+        .int_src    = INT_SRC_PORT_EIRQ9,                   \
+    }
+#endif /* EXTINT9_IRQ_CONFIG */
+
+#ifndef EXTINT10_IRQ_CONFIG
+#define EXTINT10_IRQ_CONFIG                                 \
+    {                                                       \
+        .irq_num    = BSP_EXTINT10_IRQ_NUM,                 \
+        .irq_prio   = BSP_EXTINT10_IRQ_PRIO,                \
+        .int_src    = INT_SRC_PORT_EIRQ10,                  \
+    }
+#endif /* EXTINT10_IRQ_CONFIG */
+
+#ifndef EXTINT11_IRQ_CONFIG
+#define EXTINT11_IRQ_CONFIG                                 \
+    {                                                       \
+        .irq_num    = BSP_EXTINT11_IRQ_NUM,                 \
+        .irq_prio   = BSP_EXTINT11_IRQ_PRIO,                \
+        .int_src    = INT_SRC_PORT_EIRQ11,                  \
+    }
+#endif /* EXTINT11_IRQ_CONFIG */
+
+#ifndef EXTINT12_IRQ_CONFIG
+#define EXTINT12_IRQ_CONFIG                                 \
+    {                                                       \
+        .irq_num    = BSP_EXTINT12_IRQ_NUM,                 \
+        .irq_prio   = BSP_EXTINT12_IRQ_PRIO,                \
+        .int_src    = INT_SRC_PORT_EIRQ12,                  \
+    }
+#endif /* EXTINT12_IRQ_CONFIG */
+
+#ifndef EXTINT13_IRQ_CONFIG
+#define EXTINT13_IRQ_CONFIG                                 \
+    {                                                       \
+        .irq_num    = BSP_EXTINT13_IRQ_NUM,                 \
+        .irq_prio   = BSP_EXTINT13_IRQ_PRIO,                \
+        .int_src    = INT_SRC_PORT_EIRQ13,                  \
+    }
+#endif /* EXTINT13_IRQ_CONFIG */
+
+#ifndef EXTINT14_IRQ_CONFIG
+#define EXTINT14_IRQ_CONFIG                                 \
+    {                                                       \
+        .irq_num    = BSP_EXTINT14_IRQ_NUM,                 \
+        .irq_prio   = BSP_EXTINT14_IRQ_PRIO,                \
+        .int_src    = INT_SRC_PORT_EIRQ14,                  \
+    }
+#endif /* EXTINT14_IRQ_CONFIG */
+
+#ifndef EXTINT15_IRQ_CONFIG
+#define EXTINT15_IRQ_CONFIG                                 \
+    {                                                       \
+        .irq_num    = BSP_EXTINT15_IRQ_NUM,                 \
+        .irq_prio   = BSP_EXTINT15_IRQ_PRIO,                \
+        .int_src    = INT_SRC_PORT_EIRQ15,                  \
+    }
+#endif /* EXTINT15_IRQ_CONFIG */
+
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __GPIO_CONFIG_H__ */

bsp/hc32/ev_hc32f472_lqfp100/board/config/i2c_config.h

@@ -0,0 +1,332 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2024-02-20     CDT          first version
+ */
+
+#ifndef __I2C_CONFIG_H__
+#define __I2C_CONFIG_H__
+
+#include <rtthread.h>
+#include "irq_config.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(BSP_USING_I2C1)
+#ifndef I2C1_CONFIG
+#define I2C1_CONFIG                                             \
+    {                                                           \
+        .name     = "i2c1",                                     \
+        .Instance = CM_I2C1,                                    \
+        .clock    = FCG1_PERIPH_I2C1,                           \
+        .baudrate = 100000UL,                                   \
+        .timeout  = 10000UL,                                    \
+    }
+#endif /* I2C1_CONFIG */
+#endif
+
+#if defined(BSP_I2C1_USING_DMA)
+#ifndef I2C1_TX_DMA_CONFIG
+#define I2C1_TX_DMA_CONFIG                                      \
+    {                                                           \
+        .Instance       = I2C1_TX_DMA_INSTANCE,                 \
+        .channel        = I2C1_TX_DMA_CHANNEL,                  \
+        .clock          = I2C1_TX_DMA_CLOCK,                    \
+        .trigger_select = I2C1_TX_DMA_TRIG_SELECT,              \
+        .trigger_event  = EVT_SRC_I2C1_TEI,                     \
+        .flag           = I2C1_TX_DMA_TRANS_FLAG,               \
+        .irq_config     =                                       \
+        {                                                       \
+            .irq_num    = I2C1_TX_DMA_IRQn,                     \
+            .irq_prio   = I2C1_TX_DMA_INT_PRIO,                 \
+            .int_src    = I2C1_TX_DMA_INT_SRC,                  \
+        },                                                      \
+    }
+#endif /* I2C1_TX_DMA_CONFIG */
+
+#ifndef I2C1_RX_DMA_CONFIG
+#define I2C1_RX_DMA_CONFIG                                      \
+    {                                                           \
+        .Instance       = I2C1_RX_DMA_INSTANCE,                 \
+        .channel        = I2C1_RX_DMA_CHANNEL,                  \
+        .clock          = I2C1_RX_DMA_CLOCK,                    \
+        .trigger_select = I2C1_RX_DMA_TRIG_SELECT,              \
+        .trigger_event  = EVT_SRC_I2C1_RXI,                     \
+        .flag           = I2C1_RX_DMA_TRANS_FLAG,               \
+        .irq_config     =                                       \
+        {                                                       \
+            .irq_num    = I2C1_RX_DMA_IRQn,                     \
+            .irq_prio   = I2C1_RX_DMA_INT_PRIO,                 \
+            .int_src    = I2C1_RX_DMA_INT_SRC,                  \
+        },                                                      \
+    }
+#endif /* I2C1_RX_DMA_CONFIG */
+#endif /* BSP_I2C1_USING_DMA */
+
+#if defined(BSP_USING_I2C2)
+#ifndef I2C2_CONFIG
+#define I2C2_CONFIG                                             \
+    {                                                           \
+        .name     = "i2c2",                                     \
+        .Instance = CM_I2C2,                                    \
+        .clock    = FCG1_PERIPH_I2C2,                           \
+        .baudrate = 100000UL,                                   \
+        .timeout  = 10000UL,                                    \
+    }
+#endif /* I2C2_CONFIG */
+
+#if defined(BSP_I2C2_USING_DMA)
+#ifndef I2C2_TX_DMA_CONFIG
+#define I2C2_TX_DMA_CONFIG                                      \
+    {                                                           \
+        .Instance       = I2C2_TX_DMA_INSTANCE,                 \
+        .channel        = I2C2_TX_DMA_CHANNEL,                  \
+        .clock          = I2C2_TX_DMA_CLOCK,                    \
+        .trigger_select = I2C2_TX_DMA_TRIG_SELECT,              \
+        .trigger_event  = EVT_SRC_I2C2_TEI,                     \
+        .flag           = I2C2_TX_DMA_TRANS_FLAG,               \
+        .irq_config     =                                       \
+        {                                                       \
+            .irq_num    = I2C2_TX_DMA_IRQn,                     \
+            .irq_prio   = I2C2_TX_DMA_INT_PRIO,                 \
+            .int_src    = I2C2_TX_DMA_INT_SRC,                  \
+        },                                                      \
+    }
+#endif /* I2C2_TX_DMA_CONFIG */
+
+#ifndef I2C2_RX_DMA_CONFIG
+#define I2C2_RX_DMA_CONFIG                                      \
+    {                                                           \
+        .Instance       = I2C2_RX_DMA_INSTANCE,                 \
+        .channel        = I2C2_RX_DMA_CHANNEL,                  \
+        .clock          = I2C2_RX_DMA_CLOCK,                    \
+        .trigger_select = I2C2_RX_DMA_TRIG_SELECT,              \
+        .trigger_event  = EVT_SRC_I2C2_RXI,                     \
+        .flag           = I2C2_RX_DMA_TRANS_FLAG,               \
+        .irq_config     =                                       \
+        {                                                       \
+            .irq_num    = I2C2_RX_DMA_IRQn,                     \
+            .irq_prio   = I2C2_RX_DMA_INT_PRIO,                 \
+            .int_src    = I2C2_RX_DMA_INT_SRC,                  \
+        },                                                      \
+    }
+#endif /* I2C2_RX_DMA_CONFIG */
+#endif /* BSP_I2C2_USING_DMA */
+#endif
+
+#if defined(BSP_USING_I2C3)
+#ifndef I2C3_CONFIG
+#define I2C3_CONFIG                                             \
+    {                                                           \
+        .name     = "i2c3",                                     \
+        .Instance = CM_I2C3,                                    \
+        .clock    = FCG1_PERIPH_I2C3,                           \
+        .baudrate = 100000UL,                                   \
+        .timeout  = 10000UL,                                    \
+    }
+#endif /* I2C3_CONFIG */
+
+#if defined(BSP_I2C3_USING_DMA)
+#ifndef I2C3_TX_DMA_CONFIG
+#define I2C3_TX_DMA_CONFIG                                      \
+    {                                                           \
+        .Instance       = I2C3_TX_DMA_INSTANCE,                 \
+        .channel        = I2C3_TX_DMA_CHANNEL,                  \
+        .clock          = I2C3_TX_DMA_CLOCK,                    \
+        .trigger_select = I2C3_TX_DMA_TRIG_SELECT,              \
+        .trigger_event  = EVT_SRC_I2C3_TEI,                     \
+        .flag           = I2C3_TX_DMA_TRANS_FLAG,               \
+        .irq_config     =                                       \
+        {                                                       \
+            .irq_num    = I2C3_TX_DMA_IRQn,                     \
+            .irq_prio   = I2C3_TX_DMA_INT_PRIO,                 \
+            .int_src    = I2C3_TX_DMA_INT_SRC,                  \
+        },                                                      \
+    }
+#endif /* I2C3_TX_DMA_CONFIG */
+
+#ifndef I2C3_RX_DMA_CONFIG
+#define I2C3_RX_DMA_CONFIG                                      \
+    {                                                           \
+        .Instance       = I2C3_RX_DMA_INSTANCE,                 \
+        .channel        = I2C3_RX_DMA_CHANNEL,                  \
+        .clock          = I2C3_RX_DMA_CLOCK,                    \
+        .trigger_select = I2C3_RX_DMA_TRIG_SELECT,              \
+        .trigger_event  = EVT_SRC_I2C3_RXI,                     \
+        .flag           = I2C3_RX_DMA_TRANS_FLAG,               \
+        .irq_config     =                                       \
+        {                                                       \
+            .irq_num    = I2C3_RX_DMA_IRQn,                     \
+            .irq_prio   = I2C3_RX_DMA_INT_PRIO,                 \
+            .int_src    = I2C3_RX_DMA_INT_SRC,                  \
+        },                                                      \
+    }
+#endif /* I2C3_RX_DMA_CONFIG */
+#endif /* BSP_I2C3_USING_DMA */
+#endif
+
+#if defined(BSP_USING_I2C4)
+#ifndef I2C4_CONFIG
+#define I2C4_CONFIG                                             \
+    {                                                           \
+        .name     = "i2c4",                                     \
+        .Instance = CM_I2C4,                                    \
+        .clock    = FCG1_PERIPH_I2C4,                           \
+        .baudrate = 100000UL,                                   \
+        .timeout  = 10000UL,                                    \
+    }
+#endif /* I2C4_CONFIG */
+
+#if defined(BSP_I2C4_USING_DMA)
+#ifndef I2C4_TX_DMA_CONFIG
+#define I2C4_TX_DMA_CONFIG                                      \
+    {                                                           \
+        .Instance       = I2C4_TX_DMA_INSTANCE,                 \
+        .channel        = I2C4_TX_DMA_CHANNEL,                  \
+        .clock          = I2C4_TX_DMA_CLOCK,                    \
+        .trigger_select = I2C4_TX_DMA_TRIG_SELECT,              \
+        .trigger_event  = EVT_SRC_I2C4_TEI,                     \
+        .flag           = I2C4_TX_DMA_TRANS_FLAG,               \
+        .irq_config     =                                       \
+        {                                                       \
+            .irq_num    = I2C4_TX_DMA_IRQn,                     \
+            .irq_prio   = I2C4_TX_DMA_INT_PRIO,                 \
+            .int_src    = I2C4_TX_DMA_INT_SRC,                  \
+        },                                                      \
+    }
+#endif /* I2C4_TX_DMA_CONFIG */
+
+#ifndef I2C4_RX_DMA_CONFIG
+#define I2C4_RX_DMA_CONFIG                                      \
+    {                                                           \
+        .Instance       = I2C4_RX_DMA_INSTANCE,                 \
+        .channel        = I2C4_RX_DMA_CHANNEL,                  \
+        .clock          = I2C4_RX_DMA_CLOCK,                    \
+        .trigger_select = I2C4_RX_DMA_TRIG_SELECT,              \
+        .trigger_event  = EVT_SRC_I2C4_RXI,                     \
+        .flag           = I2C4_RX_DMA_TRANS_FLAG,               \
+        .irq_config     =                                       \
+        {                                                       \
+            .irq_num    = I2C4_RX_DMA_IRQn,                     \
+            .irq_prio   = I2C4_RX_DMA_INT_PRIO,                 \
+            .int_src    = I2C4_RX_DMA_INT_SRC,                  \
+        },                                                      \
+    }
+#endif /* I2C4_RX_DMA_CONFIG */
+#endif /* BSP_I2C4_USING_DMA */
+#endif
+
+#if defined(BSP_USING_I2C5)
+#ifndef I2C5_CONFIG
+#define I2C5_CONFIG                                             \
+    {                                                           \
+        .name     = "i2c5",                                     \
+        .Instance = CM_I2C5,                                    \
+        .clock    = FCG1_PERIPH_I2C5,                           \
+        .baudrate = 100000UL,                                   \
+        .timeout  = 10000UL,                                    \
+    }
+#endif /* I2C5_CONFIG */
+
+#if defined(BSP_I2C5_USING_DMA)
+#ifndef I2C5_TX_DMA_CONFIG
+#define I2C5_TX_DMA_CONFIG                                      \
+    {                                                           \
+        .Instance       = I2C5_TX_DMA_INSTANCE,                 \
+        .channel        = I2C5_TX_DMA_CHANNEL,                  \
+        .clock          = I2C5_TX_DMA_CLOCK,                    \
+        .trigger_select = I2C5_TX_DMA_TRIG_SELECT,              \
+        .trigger_event  = EVT_SRC_I2C5_TEI,                     \
+        .flag           = I2C5_TX_DMA_TRANS_FLAG,               \
+        .irq_config     =                                       \
+        {                                                       \
+            .irq_num    = I2C5_TX_DMA_IRQn,                     \
+            .irq_prio   = I2C5_TX_DMA_INT_PRIO,                 \
+            .int_src    = I2C5_TX_DMA_INT_SRC,                  \
+        },                                                      \
+    }
+#endif /* I2C5_TX_DMA_CONFIG */
+
+#ifndef I2C5_RX_DMA_CONFIG
+#define I2C5_RX_DMA_CONFIG                                      \
+    {                                                           \
+        .Instance       = I2C5_RX_DMA_INSTANCE,                 \
+        .channel        = I2C5_RX_DMA_CHANNEL,                  \
+        .clock          = I2C5_RX_DMA_CLOCK,                    \
+        .trigger_select = I2C5_RX_DMA_TRIG_SELECT,              \
+        .trigger_event  = EVT_SRC_I2C5_RXI,                     \
+        .flag           = I2C5_RX_DMA_TRANS_FLAG,               \
+        .irq_config     =                                       \
+        {                                                       \
+            .irq_num    = I2C5_RX_DMA_IRQn,                     \
+            .irq_prio   = I2C5_RX_DMA_INT_PRIO,                 \
+            .int_src    = I2C5_RX_DMA_INT_SRC,                  \
+        },                                                      \
+    }
+#endif /* I2C5_RX_DMA_CONFIG */
+#endif /* BSP_I2C5_USING_DMA */
+#endif
+
+#if defined(BSP_USING_I2C6)
+#ifndef I2C6_CONFIG
+#define I2C6_CONFIG                                             \
+    {                                                           \
+        .name     = "i2c6",                                     \
+        .Instance = CM_I2C6,                                    \
+        .clock    = FCG1_PERIPH_I2C6,                           \
+        .baudrate = 100000UL,                                   \
+        .timeout  = 10000UL,                                    \
+    }
+#endif /* I2C6_CONFIG */
+
+#if defined(BSP_I2C6_USING_DMA)
+#ifndef I2C6_TX_DMA_CONFIG
+#define I2C6_TX_DMA_CONFIG                                      \
+    {                                                           \
+        .Instance       = I2C6_TX_DMA_INSTANCE,                 \
+        .channel        = I2C6_TX_DMA_CHANNEL,                  \
+        .clock          = I2C6_TX_DMA_CLOCK,                    \
+        .trigger_select = I2C6_TX_DMA_TRIG_SELECT,              \
+        .trigger_event  = EVT_SRC_I2C6_TEI,                     \
+        .flag           = I2C6_TX_DMA_TRANS_FLAG,               \
+        .irq_config     =                                       \
+        {                                                       \
+            .irq_num    = I2C6_TX_DMA_IRQn,                     \
+            .irq_prio   = I2C6_TX_DMA_INT_PRIO,                 \
+            .int_src    = I2C6_TX_DMA_INT_SRC,                  \
+        },                                                      \
+    }
+#endif /* I2C6_TX_DMA_CONFIG */
+
+#ifndef I2C6_RX_DMA_CONFIG
+#define I2C6_RX_DMA_CONFIG                                      \
+    {                                                           \
+        .Instance       = I2C6_RX_DMA_INSTANCE,                 \
+        .channel        = I2C6_RX_DMA_CHANNEL,                  \
+        .clock          = I2C6_RX_DMA_CLOCK,                    \
+        .trigger_select = I2C6_RX_DMA_TRIG_SELECT,              \
+        .trigger_event  = EVT_SRC_I2C6_RXI,                     \
+        .flag           = I2C6_RX_DMA_TRANS_FLAG,               \
+        .irq_config     =                                       \
+        {                                                       \
+            .irq_num    = I2C6_RX_DMA_IRQn,                     \
+            .irq_prio   = I2C6_RX_DMA_INT_PRIO,                 \
+            .int_src    = I2C6_RX_DMA_INT_SRC,                  \
+        },                                                      \
+    }
+#endif /* I2C6_RX_DMA_CONFIG */
+#endif /* BSP_I2C6_USING_DMA */
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

bsp/hc32/ev_hc32f472_lqfp100/board/config/irq_config.h

@@ -0,0 +1,215 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2024-02-20     CDT          first version
+ */
+
+#ifndef __IRQ_CONFIG_H__
+#define __IRQ_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define BSP_EXTINT0_IRQ_NUM             EXTINT_PORT_EIRQ0_IRQn
+#define BSP_EXTINT0_IRQ_PRIO            DDL_IRQ_PRIO_DEFAULT
+#define BSP_EXTINT1_IRQ_NUM             EXTINT_PORT_EIRQ1_IRQn
+#define BSP_EXTINT1_IRQ_PRIO            DDL_IRQ_PRIO_DEFAULT
+#define BSP_EXTINT2_IRQ_NUM             EXTINT_PORT_EIRQ2_IRQn
+#define BSP_EXTINT2_IRQ_PRIO            DDL_IRQ_PRIO_DEFAULT
+#define BSP_EXTINT3_IRQ_NUM             EXTINT_PORT_EIRQ3_IRQn
+#define BSP_EXTINT3_IRQ_PRIO            DDL_IRQ_PRIO_DEFAULT
+#define BSP_EXTINT4_IRQ_NUM             EXTINT_PORT_EIRQ4_IRQn
+#define BSP_EXTINT4_IRQ_PRIO            DDL_IRQ_PRIO_DEFAULT
+#define BSP_EXTINT5_IRQ_NUM             EXTINT_PORT_EIRQ5_IRQn
+#define BSP_EXTINT5_IRQ_PRIO            DDL_IRQ_PRIO_DEFAULT
+#define BSP_EXTINT6_IRQ_NUM             EXTINT_PORT_EIRQ6_IRQn
+#define BSP_EXTINT6_IRQ_PRIO            DDL_IRQ_PRIO_DEFAULT
+#define BSP_EXTINT7_IRQ_NUM             EXTINT_PORT_EIRQ7_IRQn
+#define BSP_EXTINT7_IRQ_PRIO            DDL_IRQ_PRIO_DEFAULT
+#define BSP_EXTINT8_IRQ_NUM             EXTINT_PORT_EIRQ8_IRQn
+#define BSP_EXTINT8_IRQ_PRIO            DDL_IRQ_PRIO_DEFAULT
+#define BSP_EXTINT9_IRQ_NUM             EXTINT_PORT_EIRQ9_IRQn
+#define BSP_EXTINT9_IRQ_PRIO            DDL_IRQ_PRIO_DEFAULT
+#define BSP_EXTINT10_IRQ_NUM            EXTINT_PORT_EIRQ10_IRQn
+#define BSP_EXTINT10_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+#define BSP_EXTINT11_IRQ_NUM            EXTINT_PORT_EIRQ11_IRQn
+#define BSP_EXTINT11_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+#define BSP_EXTINT12_IRQ_NUM            EXTINT_PORT_EIRQ12_IRQn
+#define BSP_EXTINT12_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+#define BSP_EXTINT13_IRQ_NUM            EXTINT_PORT_EIRQ13_IRQn
+#define BSP_EXTINT13_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+#define BSP_EXTINT14_IRQ_NUM            EXTINT_PORT_EIRQ14_IRQn
+#define BSP_EXTINT14_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+#define BSP_EXTINT15_IRQ_NUM            EXTINT_PORT_EIRQ15_IRQn
+#define BSP_EXTINT15_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+
+/* DMA1 ch0 */
+#define BSP_DMA1_CH0_IRQ_NUM            INT000_IRQn
+#define BSP_DMA1_CH0_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+/* DMA1 ch1 */
+#define BSP_DMA1_CH1_IRQ_NUM            INT001_IRQn
+#define BSP_DMA1_CH1_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+/* DMA1 ch2 */
+#define BSP_DMA1_CH2_IRQ_NUM            INT002_IRQn
+#define BSP_DMA1_CH2_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+/* DMA1 ch3 */
+#define BSP_DMA1_CH3_IRQ_NUM            INT003_IRQn
+#define BSP_DMA1_CH3_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+/* DMA1 ch4 */
+#define BSP_DMA1_CH4_IRQ_NUM            INT004_IRQn
+#define BSP_DMA1_CH4_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+/* DMA1 ch5 */
+#define BSP_DMA1_CH5_IRQ_NUM            INT005_IRQn
+#define BSP_DMA1_CH5_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+
+/* DMA2 ch0 */
+#define BSP_DMA2_CH0_IRQ_NUM            INT006_IRQn
+#define BSP_DMA2_CH0_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+/* DMA2 ch1 */
+#define BSP_DMA2_CH1_IRQ_NUM            INT007_IRQn
+#define BSP_DMA2_CH1_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+/* DMA2 ch2 */
+#define BSP_DMA2_CH2_IRQ_NUM            INT008_IRQn
+#define BSP_DMA2_CH2_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+/* DMA2 ch3 */
+#define BSP_DMA2_CH3_IRQ_NUM            INT009_IRQn
+#define BSP_DMA2_CH3_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+/* DMA2 ch4 */
+#define BSP_DMA2_CH4_IRQ_NUM            INT010_IRQn
+#define BSP_DMA2_CH4_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+/* DMA2 ch5 */
+#define BSP_DMA2_CH5_IRQ_NUM            INT011_IRQn
+#define BSP_DMA2_CH5_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+
+#if defined(BSP_USING_UART1)
+#define BSP_UART1_IRQ_NUM               USART1_IRQn
+#define BSP_UART1_IRQ_PRIO              DDL_IRQ_PRIO_DEFAULT
+
+#if (defined(RT_USING_SERIAL_V1) && defined(BSP_UART1_TX_USING_DMA)) || \
+    defined(RT_USING_SERIAL_V2)
+#define BSP_UART1_TX_CPLT_IRQ_NUM       USART1_TCI_IRQn
+#define BSP_UART1_TX_CPLT_IRQ_PRIO      DDL_IRQ_PRIO_DEFAULT
+#endif
+#endif /* BSP_USING_UART1 */
+
+#if defined(BSP_USING_UART2)
+#define BSP_UART2_IRQ_NUM               USART2_IRQn
+#define BSP_UART2_IRQ_PRIO              DDL_IRQ_PRIO_DEFAULT
+
+#if (defined(RT_USING_SERIAL_V1) && defined(BSP_UART2_TX_USING_DMA)) || \
+    defined(RT_USING_SERIAL_V2)
+#define BSP_UART2_TX_CPLT_IRQ_NUM       USART2_TCI_IRQn
+#define BSP_UART2_TX_CPLT_IRQ_PRIO      DDL_IRQ_PRIO_DEFAULT
+#endif
+#endif /* BSP_USING_UART2 */
+
+#if defined(BSP_USING_UART3)
+#define BSP_UART3_IRQ_NUM               USART3_IRQn
+#define BSP_UART3_IRQ_PRIO              DDL_IRQ_PRIO_DEFAULT
+#endif /* BSP_USING_UART3 */
+
+#if defined(BSP_USING_UART4)
+#define BSP_UART4_IRQ_NUM               USART4_IRQn
+#define BSP_UART4_IRQ_PRIO              DDL_IRQ_PRIO_DEFAULT
+
+#if (defined(RT_USING_SERIAL_V1) && defined(BSP_UART4_TX_USING_DMA)) || \
+    defined(RT_USING_SERIAL_V2)
+#define BSP_UART4_TX_CPLT_IRQ_NUM       USART4_TCI_IRQn
+#define BSP_UART4_TX_CPLT_IRQ_PRIO      DDL_IRQ_PRIO_DEFAULT
+#endif
+#endif /* BSP_USING_UART4 */
+
+#if defined(BSP_USING_UART5)
+#define BSP_UART5_IRQ_NUM               USART5_IRQn
+#define BSP_UART5_IRQ_PRIO              DDL_IRQ_PRIO_DEFAULT
+
+#if (defined(RT_USING_SERIAL_V1) && defined(BSP_UART5_TX_USING_DMA)) || \
+    defined(RT_USING_SERIAL_V2)
+#define BSP_UART5_TX_CPLT_IRQ_NUM       USART5_TCI_IRQn
+#define BSP_UART5_TX_CPLT_IRQ_PRIO      DDL_IRQ_PRIO_DEFAULT
+#endif
+#endif /* BSP_USING_UART5 */
+
+#if defined(BSP_USING_UART6)
+#define BSP_UART6_IRQ_NUM               USART6_IRQn
+#define BSP_UART6_IRQ_PRIO              DDL_IRQ_PRIO_DEFAULT
+#endif /* BSP_USING_UART6 */
+
+#if defined(BSP_USING_SPI1)
+#define BSP_SPI1_ERR_IRQ_NUM            SPI1_IRQn
+#define BSP_SPI1_ERR_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+#endif
+
+#if defined(BSP_USING_SPI2)
+#define BSP_SPI2_ERR_IRQ_NUM            SPI2_IRQn
+#define BSP_SPI2_ERR_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+#endif
+
+#if defined(BSP_USING_SPI3)
+#define BSP_SPI3_ERR_IRQ_NUM            SPI3_IRQn
+#define BSP_SPI3_ERR_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+#endif
+
+#if defined(BSP_USING_SPI4)
+#define BSP_SPI4_ERR_IRQ_NUM            SPI4_IRQn
+#define BSP_SPI4_ERR_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+#endif
+
+#if defined (BSP_USING_QSPI)
+#define BSP_QSPI_ERR_IRQ_NUM            QSPI_IRQn
+#define BSP_QSPI_ERR_IRQ_PRIO           DDL_IRQ_PRIO_DEFAULT
+#endif /* BSP_USING_QSPI */
+
+#if defined(BSP_USING_TMRA_1)
+#define BSP_USING_TMRA_1_IRQ_NUM        TMRA_1_OVF_UDF_IRQn
+#define BSP_USING_TMRA_1_IRQ_PRIO       DDL_IRQ_PRIO_DEFAULT
+#endif/* BSP_USING_TMRA_1 */
+
+#if defined(BSP_USING_TMRA_2)
+#define BSP_USING_TMRA_2_IRQ_NUM        TMRA_2_OVF_UDF_IRQn
+#define BSP_USING_TMRA_2_IRQ_PRIO       DDL_IRQ_PRIO_DEFAULT
+#endif/* BSP_USING_TMRA_2 */
+
+#if defined(BSP_USING_TMRA_3)
+#define BSP_USING_TMRA_3_IRQ_NUM        TMRA_3_OVF_UDF_IRQn
+#define BSP_USING_TMRA_3_IRQ_PRIO       DDL_IRQ_PRIO_DEFAULT
+#endif/* BSP_USING_TMRA_3 */
+
+#if defined(BSP_USING_TMRA_4)
+#define BSP_USING_TMRA_4_IRQ_NUM        TMRA_4_OVF_UDF_IRQn
+#define BSP_USING_TMRA_4_IRQ_PRIO       DDL_IRQ_PRIO_DEFAULT
+#endif/* BSP_USING_TMRA_4 */
+
+#if defined(BSP_USING_TMRA_5)
+#define BSP_USING_TMRA_5_IRQ_NUM        TMRA_5_OVF_UDF_IRQn
+#define BSP_USING_TMRA_5_IRQ_PRIO       DDL_IRQ_PRIO_DEFAULT
+#endif/* BSP_USING_TMRA_5 */
+
+#if defined(BSP_USING_TMRA_6)
+#define BSP_USING_TMRA_6_IRQ_NUM        TMRA_6_OVF_UDF_IRQn
+#define BSP_USING_TMRA_6_IRQ_PRIO       DDL_IRQ_PRIO_DEFAULT
+#endif/* BSP_USING_TMRA_6 */
+
+#if defined(BSP_USING_CAN1)
+#define BSP_CAN1_IRQ_NUM                MCAN1_INT0_IRQn
+#define BSP_CAN1_IRQ_PRIO               DDL_IRQ_PRIO_DEFAULT
+#endif/* BSP_USING_CAN1 */
+
+#if defined(RT_USING_ALARM)
+#define BSP_RTC_ALARM_IRQ_NUM           RTC_IRQn
+#define BSP_RTC_ALARM_IRQ_PRIO          DDL_IRQ_PRIO_DEFAULT
+#endif/* RT_USING_ALARM */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __IRQ_CONFIG_H__ */

bsp/hc32/ev_hc32f472_lqfp100/board/config/pm_config.h

@@ -0,0 +1,100 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2024-02-20     CDT          first version
+ */
+
+#ifndef __PM_CONFIG_H__
+#define __PM_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_PM
+extern void rt_hw_board_pm_sysclk_cfg(uint8_t run_mode);
+
+#ifndef PM_TICKLESS_TIMER_ENABLE_MASK
+#define PM_TICKLESS_TIMER_ENABLE_MASK                                          \
+(   (1UL << PM_SLEEP_MODE_IDLE)  |                                             \
+    (1UL << PM_SLEEP_MODE_DEEP))
+#endif
+
+/**
+ * @brief  run mode config @ref pm_run_mode_config structure
+ */
+#ifndef PM_RUN_MODE_CFG
+#define PM_RUN_MODE_CFG                                                        \
+    {                                                                          \
+       .sys_clk_cfg = rt_hw_board_pm_sysclk_cfg                                \
+    }
+#endif /* PM_RUN_MODE_CFG */
+
+/**
+ * @brief  sleep idle config @ref pm_sleep_mode_idle_config structure
+ */
+#ifndef PM_SLEEP_IDLE_CFG
+#define PM_SLEEP_IDLE_CFG                                                      \
+{                                                                              \
+    .pwc_sleep_type = PWC_SLEEP_WFE_INT,                                       \
+}
+#endif /*PM_SLEEP_IDLE_CFG*/
+
+/**
+ * @brief  sleep deep config @ref pm_sleep_mode_deep_config structure
+ */
+#ifndef PM_SLEEP_DEEP_CFG
+#define PM_SLEEP_DEEP_CFG                                                      \
+{                                                                              \
+    {                                                                          \
+        .u16Clock = PWC_STOP_CLK_KEEP,                                         \
+        .u8StopDrv = PWC_STOP_DRV_HIGH,                                        \
+        .u16ExBusHold = PWC_STOP_EXBUS_HIZ,                                    \
+        .u16FlashWait = PWC_STOP_FLASH_WAIT_ON,                                \
+    },                                                                         \
+    .pwc_stop_type = PWC_STOP_WFE_INT,                                         \
+}
+#endif /*PM_SLEEP_DEEP_CFG*/
+
+/**
+ * @brief  sleep standby config @ref pm_sleep_mode_standby_config structure
+ */
+#ifndef PM_SLEEP_STANDBY_CFG
+#define PM_SLEEP_STANDBY_CFG                                                   \
+{                                                                              \
+    {                                                                          \
+        .u8Mode = PWC_PD_MD1,                                                  \
+        .u8IOState = PWC_PD_IO_KEEP1,                                          \
+        .u8VcapCtrl = PWC_PD_VCAP_0P047UF,                                     \
+    },                                                                         \
+}
+#endif /*PM_SLEEP_STANDBY_CFG*/
+
+/**
+ * @brief  sleep shutdown config @ref pm_sleep_mode_shutdown_config structure
+ */
+#ifndef PM_SLEEP_SHUTDOWN_CFG
+#define PM_SLEEP_SHUTDOWN_CFG                                                  \
+{                                                                              \
+    {                                                                          \
+        .u8Mode = PWC_PD_MD3,                                                  \
+        .u8IOState = PWC_PD_IO_KEEP1,                                          \
+        .u8VcapCtrl = PWC_PD_VCAP_0P047UF,                                     \
+    },                                                                         \
+}
+#endif /*PM_SLEEP_SHUTDOWN_CFG*/
+
+#endif /* BSP_USING_PM */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __PM_CONFIG_H__ */

bsp/hc32/ev_hc32f472_lqfp100/board/config/pulse_encoder_config.h

@@ -0,0 +1,545 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2024-02-20     CDT          first version
+ */
+
+#ifndef __PULSE_ENCODER_CONFIG_H__
+#define __PULSE_ENCODER_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(RT_USING_PULSE_ENCODER)
+
+#ifdef BSP_USING_PULSE_ENCODER_TMRA_1
+#ifndef PULSE_ENCODER_TMRA_1_CONFIG
+#define PULSE_ENCODER_TMRA_1_CONFIG                                             \
+    {                                                                           \
+       .tmr_handler     = CM_TMRA_1,                                            \
+       .u32Fcg2Periph   = FCG2_PERIPH_TMRA_1,                                   \
+       .hw_count =                                                              \
+       {                                                                        \
+            .u16CountUpCond     = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING,       \
+            .u16CountDownCond   = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING,     \
+       },                                                                       \
+       .isr =                                                                   \
+       {                                                                        \
+            .enIntSrc_OVF   = INT_SRC_TMRA_1_OVF,                               \
+            .enIRQn_OVF     = BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_NUM,             \
+            .u8Int_Prio_OVF = BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_PRIO,            \
+            .enIntSrc_UDF   = INT_SRC_TMRA_1_UDF,                               \
+            .enIRQn_UDF     = BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_NUM,             \
+            .u8Int_Prio_UDF = BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_PRIO,            \
+       },                                                                       \
+       .u32PeriodValue      = 1000UL,                                           \
+       .name                = "pulse_a1"                                        \
+    }
+#endif /* PULSE_ENCODER_TMRA_1_CONFIG */
+#endif /* BSP_USING_PULSE_ENCODER_TMRA_1 */
+
+#ifdef BSP_USING_PULSE_ENCODER_TMRA_2
+#ifndef PULSE_ENCODER_TMRA_2_CONFIG
+#define PULSE_ENCODER_TMRA_2_CONFIG                                             \
+    {                                                                           \
+       .tmr_handler     = CM_TMRA_2,                                            \
+       .u32Fcg2Periph   = FCG2_PERIPH_TMRA_2,                                   \
+       .hw_count =                                                              \
+       {                                                                        \
+            .u16CountUpCond     = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING,       \
+            .u16CountDownCond   = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING,     \
+       },                                                                       \
+       .isr =                                                                   \
+       {                                                                        \
+            .enIntSrc_OVF   = INT_SRC_TMRA_2_OVF,                               \
+            .enIRQn_OVF     = BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_NUM,             \
+            .u8Int_Prio_OVF = BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_PRIO,            \
+            .enIntSrc_UDF   = INT_SRC_TMRA_2_UDF,                               \
+            .enIRQn_UDF     = BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_NUM,             \
+            .u8Int_Prio_UDF = BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_PRIO,            \
+       },                                                                       \
+       .u32PeriodValue  = 1000UL,                                               \
+       .name            = "pulse_a2"                                            \
+    }
+#endif /* PULSE_ENCODER_TMRA_2_CONFIG */
+#endif /* BSP_USING_PULSE_ENCODER_TMRA_2 */
+
+#ifdef BSP_USING_PULSE_ENCODER_TMRA_3
+#ifndef PULSE_ENCODER_TMRA_3_CONFIG
+#define PULSE_ENCODER_TMRA_3_CONFIG                                             \
+    {                                                                           \
+       .tmr_handler     = CM_TMRA_3,                                            \
+       .u32Fcg2Periph   = FCG2_PERIPH_TMRA_3,                                   \
+       .hw_count =                                                              \
+       {                                                                        \
+            .u16CountUpCond     = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING,       \
+            .u16CountDownCond   = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING,     \
+       },                                                                       \
+       .isr =                                                                   \
+       {                                                                        \
+            .enIntSrc_OVF   = INT_SRC_TMRA_3_OVF,                               \
+            .enIRQn_OVF     = BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_NUM,             \
+            .u8Int_Prio_OVF = BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_PRIO,            \
+            .enIntSrc_UDF   = INT_SRC_TMRA_3_UDF,                               \
+            .enIRQn_UDF     = BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_NUM,             \
+            .u8Int_Prio_UDF = BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_PRIO,            \
+       },                                                                       \
+       .u32PeriodValue  = 1000UL,                                               \
+       .name            = "pulse_a3"                                            \
+    }
+#endif /* PULSE_ENCODER_TMRA_3_CONFIG */
+#endif /* BSP_USING_PULSE_ENCODER_TMRA_3 */
+
+#ifdef BSP_USING_PULSE_ENCODER_TMRA_4
+#ifndef PULSE_ENCODER_TMRA_4_CONFIG
+#define PULSE_ENCODER_TMRA_4_CONFIG                                             \
+    {                                                                           \
+       .tmr_handler     = CM_TMRA_4,                                            \
+       .u32Fcg2Periph   = FCG2_PERIPH_TMRA_4,                                   \
+       .hw_count =                                                              \
+       {                                                                        \
+            .u16CountUpCond     = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING,       \
+            .u16CountDownCond   = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING,     \
+       },                                                                       \
+       .isr =                                                                   \
+       {                                                                        \
+            .enIntSrc_OVF   = INT_SRC_TMRA_4_OVF,                               \
+            .enIRQn_OVF     = BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_NUM,             \
+            .u8Int_Prio_OVF = BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_PRIO,            \
+            .enIntSrc_UDF   = INT_SRC_TMRA_4_UDF,                               \
+            .enIRQn_UDF     = BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_NUM,             \
+            .u8Int_Prio_UDF = BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_PRIO,            \
+       },                                                                       \
+       .u32PeriodValue  = 1000UL,                                               \
+       .name            = "pulse_a4"                                            \
+    }
+#endif /* PULSE_ENCODER_TMRA_4_CONFIG */
+#endif /* BSP_USING_PULSE_ENCODER_TMRA_4 */
+
+#ifdef BSP_USING_PULSE_ENCODER_TMRA_5
+#ifndef PULSE_ENCODER_TMRA_5_CONFIG
+#define PULSE_ENCODER_TMRA_5_CONFIG                                             \
+    {                                                                           \
+       .tmr_handler     = CM_TMRA_5,                                            \
+       .u32Fcg2Periph   = FCG2_PERIPH_TMRA_5,                                   \
+       .hw_count =                                                              \
+        {                                                                       \
+            .u16CountUpCond     = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING,       \
+            .u16CountDownCond   = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING,     \
+       },                                                                       \
+       .isr =                                                                   \
+       {                                                                        \
+            .enIntSrc_OVF   = INT_SRC_TMRA_5_OVF,                               \
+            .enIRQn_OVF     = BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_NUM,             \
+            .u8Int_Prio_OVF = BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_PRIO,            \
+            .enIntSrc_UDF   = INT_SRC_TMRA_5_UDF,                               \
+            .enIRQn_UDF     = BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_NUM,             \
+            .u8Int_Prio_UDF = BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_PRIO,            \
+       },                                                                       \
+       .u32PeriodValue  = 1000UL,                                               \
+       .name            = "pulse_a5"                                            \
+    }
+#endif /* PULSE_ENCODER_TMRA_5_CONFIG */
+#endif /* BSP_USING_PULSE_ENCODER_TMRA_5 */
+
+#ifdef BSP_USING_PULSE_ENCODER_TMRA_6
+#ifndef PULSE_ENCODER_TMRA_6_CONFIG
+#define PULSE_ENCODER_TMRA_6_CONFIG                                             \
+    {                                                                           \
+       .tmr_handler     = CM_TMRA_6,                                            \
+       .u32Fcg2Periph   = FCG2_PERIPH_TMRA_6,                                   \
+       .hw_count =                                                              \
+       {                                                                        \
+            .u16CountUpCond     = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING,       \
+            .u16CountDownCond   = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING,     \
+       },                                                                       \
+       .isr =                                                                   \
+       {                                                                        \
+            .enIntSrc_OVF   = INT_SRC_TMRA_6_OVF,                               \
+            .enIRQn_OVF     = BSP_PULSE_ENCODER_TMRA_6_OVF_IRQ_NUM,             \
+            .u8Int_Prio_OVF = BSP_PULSE_ENCODER_TMRA_6_OVF_IRQ_PRIO,            \
+            .enIntSrc_UDF   = INT_SRC_TMRA_6_UDF,                               \
+            .enIRQn_UDF     = BSP_PULSE_ENCODER_TMRA_6_UDF_IRQ_NUM,             \
+            .u8Int_Prio_UDF = BSP_PULSE_ENCODER_TMRA_6_UDF_IRQ_PRIO,            \
+       },                                                                       \
+       .u32PeriodValue  = 1000UL,                                               \
+       .name            = "pulse_a6"                                            \
+    }
+#endif /* PULSE_ENCODER_TMRA_6_CONFIG */
+#endif /* BSP_USING_PULSE_ENCODER_TMRA_6 */
+
+#ifdef BSP_USING_PULSE_ENCODER_TMRA_7
+#ifndef PULSE_ENCODER_TMRA_7_CONFIG
+#define PULSE_ENCODER_TMRA_7_CONFIG                                             \
+    {                                                                           \
+       .tmr_handler     = CM_TMRA_7,                                            \
+       .u32Fcg2Periph   = FCG2_PERIPH_TMRA_7,                                   \
+       .hw_count =                                                              \
+       {                                                                        \
+            .u16CountUpCond     = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING,       \
+            .u16CountDownCond   = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING,     \
+       },                                                                       \
+       .isr =                                                                   \
+       {                                                                        \
+            .enIntSrc_OVF   = INT_SRC_TMRA_7_OVF,                               \
+            .enIRQn_OVF     = BSP_PULSE_ENCODER_TMRA_7_OVF_IRQ_NUM,             \
+            .u8Int_Prio_OVF = BSP_PULSE_ENCODER_TMRA_7_OVF_IRQ_PRIO,            \
+            .enIntSrc_UDF   = INT_SRC_TMRA_7_UDF,                               \
+            .enIRQn_UDF     = BSP_PULSE_ENCODER_TMRA_7_UDF_IRQ_NUM,             \
+            .u8Int_Prio_UDF = BSP_PULSE_ENCODER_TMRA_7_UDF_IRQ_PRIO,            \
+       },                                                                       \
+       .u32PeriodValue  = 1000UL,                                               \
+       .name            = "pulse_a7"                                            \
+    }
+#endif /* PULSE_ENCODER_TMRA_7_CONFIG */
+#endif /* BSP_USING_PULSE_ENCODER_TMRA_7 */
+
+#ifdef BSP_USING_PULSE_ENCODER_TMRA_8
+#ifndef PULSE_ENCODER_TMRA_8_CONFIG
+#define PULSE_ENCODER_TMRA_8_CONFIG                                             \
+    {                                                                           \
+       .tmr_handler     = CM_TMRA_8,                                            \
+       .u32Fcg2Periph   = FCG2_PERIPH_TMRA_8,                                   \
+       .hw_count =                                                              \
+        {                                                                       \
+            .u16CountUpCond     = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING,       \
+            .u16CountDownCond   = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING,     \
+       },                                                                       \
+       .isr =                                                                   \
+       {                                                                        \
+            .enIntSrc_OVF   = INT_SRC_TMRA_8_OVF,                               \
+            .enIRQn_OVF     = BSP_PULSE_ENCODER_TMRA_8_OVF_IRQ_NUM,             \
+            .u8Int_Prio_OVF = BSP_PULSE_ENCODER_TMRA_8_OVF_IRQ_PRIO,            \
+            .enIntSrc_UDF   = INT_SRC_TMRA_8_UDF,                               \
+            .enIRQn_UDF     = BSP_PULSE_ENCODER_TMRA_8_UDF_IRQ_NUM,             \
+            .u8Int_Prio_UDF = BSP_PULSE_ENCODER_TMRA_8_UDF_IRQ_PRIO,            \
+       },                                                                       \
+       .u32PeriodValue  = 1000UL,                                               \
+       .name            = "pulse_a8"                                            \
+    }
+#endif /* PULSE_ENCODER_TMRA_8_CONFIG */
+#endif /* BSP_USING_PULSE_ENCODER_TMRA_8 */
+
+#ifdef BSP_USING_PULSE_ENCODER_TMRA_9
+#ifndef PULSE_ENCODER_TMRA_9_CONFIG
+#define PULSE_ENCODER_TMRA_9_CONFIG                                             \
+    {                                                                           \
+       .tmr_handler     = CM_TMRA_9,                                            \
+       .u32Fcg2Periph   = FCG2_PERIPH_TMRA_9,                                   \
+       .hw_count =                                                              \
+       {                                                                        \
+            .u16CountUpCond     = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING,       \
+            .u16CountDownCond   = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING,     \
+       },                                                                       \
+       .isr =                                                                   \
+       {                                                                        \
+            .enIntSrc_OVF   = INT_SRC_TMRA_9_OVF,                               \
+            .enIRQn_OVF     = BSP_PULSE_ENCODER_TMRA_9_OVF_IRQ_NUM,             \
+            .u8Int_Prio_OVF = BSP_PULSE_ENCODER_TMRA_9_OVF_IRQ_PRIO,            \
+            .enIntSrc_UDF   = INT_SRC_TMRA_9_UDF,                               \
+            .enIRQn_UDF     = BSP_PULSE_ENCODER_TMRA_9_UDF_IRQ_NUM,             \
+            .u8Int_Prio_UDF = BSP_PULSE_ENCODER_TMRA_9_UDF_IRQ_PRIO,            \
+       },                                                                       \
+       .u32PeriodValue  = 1000UL,                                               \
+       .name            = "pulse_a9"                                            \
+    }
+#endif /* PULSE_ENCODER_TMRA_9_CONFIG */
+#endif /* BSP_USING_PULSE_ENCODER_TMRA_9 */
+
+#ifdef BSP_USING_PULSE_ENCODER_TMRA_10
+#ifndef PULSE_ENCODER_TMRA_10_CONFIG
+#define PULSE_ENCODER_TMRA_10_CONFIG                                            \
+    {                                                                           \
+       .tmr_handler     = CM_TMRA_10,                                           \
+       .u32Fcg2Periph   = FCG2_PERIPH_TMRA_10,                                  \
+       .hw_count =                                                              \
+       {                                                                        \
+            .u16CountUpCond     = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING,       \
+            .u16CountDownCond   = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING,     \
+       },                                                                       \
+       .isr =                                                                   \
+       {                                                                        \
+            .enIntSrc_OVF   = INT_SRC_TMRA_10_OVF,                              \
+            .enIRQn_OVF     = BSP_PULSE_ENCODER_TMRA_10_OVF_IRQ_NUM,            \
+            .u8Int_Prio_OVF = BSP_PULSE_ENCODER_TMRA_10_OVF_IRQ_PRIO,           \
+            .enIntSrc_UDF   = INT_SRC_TMRA_10_UDF,                              \
+            .enIRQn_UDF     = BSP_PULSE_ENCODER_TMRA_10_UDF_IRQ_NUM,            \
+            .u8Int_Prio_UDF = BSP_PULSE_ENCODER_TMRA_10_UDF_IRQ_PRIO,           \
+       },                                                                       \
+       .u32PeriodValue  = 1000UL,                                               \
+       .name            = "pulse_a10"                                           \
+    }
+#endif /* PULSE_ENCODER_TMRA_10_CONFIG */
+#endif /* BSP_USING_PULSE_ENCODER_TMRA_10 */
+
+#ifdef BSP_USING_PULSE_ENCODER_TMRA_11
+#ifndef PULSE_ENCODER_TMRA_11_CONFIG
+#define PULSE_ENCODER_TMRA_11_CONFIG                                            \
+    {                                                                           \
+       .tmr_handler     = CM_TMRA_11,                                           \
+       .u32Fcg2Periph   = FCG2_PERIPH_TMRA_11,                                  \
+       .hw_count =                                                              \
+       {                                                                        \
+            .u16CountUpCond     = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING,       \
+            .u16CountDownCond   = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING,     \
+       },                                                                       \
+       .isr =                                                                   \
+       {                                                                        \
+            .enIntSrc_OVF   = INT_SRC_TMRA_11_OVF,                              \
+            .enIRQn_OVF     = BSP_PULSE_ENCODER_TMRA_11_OVF_IRQ_NUM,            \
+            .u8Int_Prio_OVF = BSP_PULSE_ENCODER_TMRA_11_OVF_IRQ_PRIO,           \
+            .enIntSrc_UDF   = INT_SRC_TMRA_11_UDF,                              \
+            .enIRQn_UDF     = BSP_PULSE_ENCODER_TMRA_11_UDF_IRQ_NUM,            \
+            .u8Int_Prio_UDF = BSP_PULSE_ENCODER_TMRA_11_UDF_IRQ_PRIO,           \
+       },                                                                       \
+       .u32PeriodValue  = 1000UL,                                               \
+       .name            = "pulse_a11"                                           \
+    }
+#endif /* PULSE_ENCODER_TMRA_11_CONFIG */
+#endif /* BSP_USING_PULSE_ENCODER_TMRA_11 */
+
+#ifdef BSP_USING_PULSE_ENCODER_TMRA_12
+#ifndef PULSE_ENCODER_TMRA_12_CONFIG
+#define PULSE_ENCODER_TMRA_12_CONFIG                                            \
+    {                                                                           \
+       .tmr_handler     = CM_TMRA_12,                                           \
+       .u32Fcg2Periph   = FCG2_PERIPH_TMRA_12,                                  \
+       .hw_count =                                                              \
+       {                                                                        \
+            .u16CountUpCond     = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING,       \
+            .u16CountDownCond   = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING,     \
+       },                                                                       \
+       .isr =                                                                   \
+       {                                                                        \
+            .enIntSrc_OVF   = INT_SRC_TMRA_12_OVF,                              \
+            .enIRQn_OVF     = BSP_PULSE_ENCODER_TMRA_12_OVF_IRQ_NUM,            \
+            .u8Int_Prio_OVF = BSP_PULSE_ENCODER_TMRA_12_OVF_IRQ_PRIO,           \
+            .enIntSrc_UDF   = INT_SRC_TMRA_12_UDF,                              \
+            .enIRQn_UDF     = BSP_PULSE_ENCODER_TMRA_12_UDF_IRQ_NUM,            \
+            .u8Int_Prio_UDF = BSP_PULSE_ENCODER_TMRA_12_UDF_IRQ_PRIO,           \
+       },                                                                       \
+       .u32PeriodValue  = 1000UL,                                               \
+       .name            = "pulse_a12"                                           \
+    }
+#endif /* PULSE_ENCODER_TMRA_12_CONFIG */
+#endif /* BSP_USING_PULSE_ENCODER_TMRA_12 */
+
+#ifdef BSP_USING_PULSE_ENCODER_TMR6_1
+#ifndef PULSE_ENCODER_TMR6_1_CONFIG
+#define PULSE_ENCODER_TMR6_1_CONFIG                                             \
+    {                                                                           \
+       .tmr_handler     = CM_TMR6_1,                                            \
+       .u32Fcg2Periph   = FCG2_PERIPH_TMR6_1,                                   \
+       .hw_count =                                                              \
+       {                                                                        \
+            .u32CountUpCond     = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING,       \
+            .u32CountDownCond   = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING,     \
+       },                                                                       \
+       .isr =                                                                   \
+       {                                                                        \
+            .enIntSrc_OVF   = INT_SRC_TMR6_1_OVF,                               \
+            .enIRQn_OVF     = BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_NUM,             \
+            .u8Int_Prio_OVF = BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_PRIO,            \
+            .enIntSrc_UDF   = INT_SRC_TMR6_1_UDF,                               \
+            .enIRQn_UDF     = BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_NUM,             \
+            .u8Int_Prio_UDF = BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_PRIO,            \
+       },                                                                       \
+       .u32PeriodValue  = 1000UL,                                               \
+       .name            = "pulse_61"                                            \
+    }
+#endif /* PULSE_ENCODER_TMR6_1_CONFIG */
+#endif /* BSP_USING_PULSE_ENCODER_TMR6_1 */
+
+#ifdef BSP_USING_PULSE_ENCODER_TMR6_2
+#ifndef PULSE_ENCODER_TMR6_2_CONFIG
+#define PULSE_ENCODER_TMR6_2_CONFIG                                             \
+    {                                                                           \
+       .tmr_handler     = CM_TMR6_2,                                            \
+       .u32Fcg2Periph   = FCG2_PERIPH_TMR6_2,                                   \
+       .hw_count =                                                              \
+       {                                                                        \
+            .u32CountUpCond     = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING,       \
+            .u32CountDownCond   = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING,     \
+       },                                                                       \
+       .isr =                                                                   \
+       {                                                                        \
+            .enIntSrc_OVF   = INT_SRC_TMR6_2_OVF,                               \
+            .enIRQn_OVF     = BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_NUM,             \
+            .u8Int_Prio_OVF = BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_PRIO,            \
+            .enIntSrc_UDF   = INT_SRC_TMR6_2_UDF,                               \
+            .enIRQn_UDF     = BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_NUM,             \
+            .u8Int_Prio_UDF = BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_PRIO,            \
+       },                                                                       \
+       .u32PeriodValue  = 1000UL,                                               \
+       .name            = "pulse_62"                                            \
+    }
+#endif /* PULSE_ENCODER_TMR6_2_CONFIG */
+#endif /* BSP_USING_PULSE_ENCODER_TMR6_2 */
+
+#ifdef BSP_USING_PULSE_ENCODER_TMR6_3
+#ifndef PULSE_ENCODER_TMR6_3_CONFIG
+#define PULSE_ENCODER_TMR6_3_CONFIG                                             \
+    {                                                                           \
+       .tmr_handler     = CM_TMR6_3,                                            \
+       .u32Fcg2Periph   = FCG2_PERIPH_TMR6_3,                                   \
+       .hw_count =                                                              \
+       {                                                                        \
+            .u32CountUpCond     = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING,       \
+            .u32CountDownCond   = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING,     \
+       },                                                                       \
+       .isr =                                                                   \
+       {                                                                        \
+            .enIntSrc_OVF   = INT_SRC_TMR6_3_OVF,                               \
+            .enIRQn_OVF     = BSP_PULSE_ENCODER_TMR6_3_OVF_IRQ_NUM,             \
+            .u8Int_Prio_OVF = BSP_PULSE_ENCODER_TMR6_3_OVF_IRQ_PRIO,            \
+            .enIntSrc_UDF   = INT_SRC_TMR6_3_UDF,                               \
+            .enIRQn_UDF     = BSP_PULSE_ENCODER_TMR6_3_UDF_IRQ_NUM,             \
+            .u8Int_Prio_UDF = BSP_PULSE_ENCODER_TMR6_3_UDF_IRQ_PRIO,            \
+       },                                                                       \
+       .u32PeriodValue  = 1000UL,                                               \
+       .name            = "pulse_63"                                            \
+    }
+#endif /* PULSE_ENCODER_TMR6_3_CONFIG */
+#endif /* BSP_USING_PULSE_ENCODER_TMR6_3 */
+
+#ifdef BSP_USING_PULSE_ENCODER_TMR6_4
+#ifndef PULSE_ENCODER_TMR6_4_CONFIG
+#define PULSE_ENCODER_TMR6_4_CONFIG                                             \
+    {                                                                           \
+       .tmr_handler     = CM_TMR6_4,                                            \
+       .u32Fcg2Periph   = FCG2_PERIPH_TMR6_4,                                   \
+       .hw_count =                                                              \
+       {                                                                        \
+            .u32CountUpCond     = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING,       \
+            .u32CountDownCond   = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING,     \
+       },                                                                       \
+       .isr =                                                                   \
+       {                                                                        \
+            .enIntSrc_OVF   = INT_SRC_TMR6_4_OVF,                               \
+            .enIRQn_OVF     = BSP_PULSE_ENCODER_TMR6_4_OVF_IRQ_NUM,             \
+            .u8Int_Prio_OVF = BSP_PULSE_ENCODER_TMR6_4_OVF_IRQ_PRIO,            \
+            .enIntSrc_UDF   = INT_SRC_TMR6_4_UDF,                               \
+            .enIRQn_UDF     = BSP_PULSE_ENCODER_TMR6_4_UDF_IRQ_NUM,             \
+            .u8Int_Prio_UDF = BSP_PULSE_ENCODER_TMR6_4_UDF_IRQ_PRIO,            \
+       },                                                                       \
+       .u32PeriodValue  = 1000UL,                                               \
+       .name            = "pulse_64"                                            \
+    }
+#endif /* PULSE_ENCODER_TMR6_4_CONFIG */
+#endif /* BSP_USING_PULSE_ENCODER_TMR6_4 */
+
+#ifdef BSP_USING_PULSE_ENCODER_TMR6_5
+#ifndef PULSE_ENCODER_TMR6_5_CONFIG
+#define PULSE_ENCODER_TMR6_5_CONFIG                                             \
+    {                                                                           \
+       .tmr_handler     = CM_TMR6_5,                                            \
+       .u32Fcg2Periph   = FCG2_PERIPH_TMR6_5,                                   \
+       .hw_count =                                                              \
+       {                                                                        \
+            .u32CountUpCond     = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING,       \
+            .u32CountDownCond   = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING,     \
+       },                                                                       \
+       .isr =                                                                   \
+       {                                                                        \
+            .enIntSrc_OVF   = INT_SRC_TMR6_5_OVF,                               \
+            .enIRQn_OVF     = BSP_PULSE_ENCODER_TMR6_5_OVF_IRQ_NUM,             \
+            .u8Int_Prio_OVF = BSP_PULSE_ENCODER_TMR6_5_OVF_IRQ_PRIO,            \
+            .enIntSrc_UDF   = INT_SRC_TMR6_5_UDF,                               \
+            .enIRQn_UDF     = BSP_PULSE_ENCODER_TMR6_5_UDF_IRQ_NUM,             \
+            .u8Int_Prio_UDF = BSP_PULSE_ENCODER_TMR6_5_UDF_IRQ_PRIO,            \
+       },                                                                       \
+       .u32PeriodValue  = 1000UL,                                               \
+       .name            = "pulse_65"                                            \
+    }
+#endif /* PULSE_ENCODER_TMR6_5_CONFIG */
+#endif /* BSP_USING_PULSE_ENCODER_TMR6_5 */
+
+#ifdef BSP_USING_PULSE_ENCODER_TMR6_6
+#ifndef PULSE_ENCODER_TMR6_6_CONFIG
+#define PULSE_ENCODER_TMR6_6_CONFIG                                             \
+    {                                                                           \
+       .tmr_handler     = CM_TMR6_6,                                            \
+       .u32Fcg2Periph   = FCG2_PERIPH_TMR6_6,                                   \
+       .hw_count =                                                              \
+       {                                                                        \
+            .u32CountUpCond     = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING,       \
+            .u32CountDownCond   = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING,     \
+       },                                                                       \
+       .isr =                                                                   \
+       {                                                                        \
+            .enIntSrc_OVF   = INT_SRC_TMR6_6_OVF,                               \
+            .enIRQn_OVF     = BSP_PULSE_ENCODER_TMR6_6_OVF_IRQ_NUM,             \
+            .u8Int_Prio_OVF = BSP_PULSE_ENCODER_TMR6_6_OVF_IRQ_PRIO,            \
+            .enIntSrc_UDF   = INT_SRC_TMR6_6_UDF,                               \
+            .enIRQn_UDF     = BSP_PULSE_ENCODER_TMR6_6_UDF_IRQ_NUM,             \
+            .u8Int_Prio_UDF = BSP_PULSE_ENCODER_TMR6_6_UDF_IRQ_PRIO,            \
+       },                                                                       \
+       .u32PeriodValue  = 1000UL,                                               \
+       .name            = "pulse_66"                                            \
+    }
+#endif /* PULSE_ENCODER_TMR6_6_CONFIG */
+#endif /* BSP_USING_PULSE_ENCODER_TMR6_6 */
+
+#ifdef BSP_USING_PULSE_ENCODER_TMR6_7
+#ifndef PULSE_ENCODER_TMR6_7_CONFIG
+#define PULSE_ENCODER_TMR6_7_CONFIG                                             \
+    {                                                                           \
+       .tmr_handler     = CM_TMR6_7,                                            \
+       .u32Fcg2Periph   = FCG2_PERIPH_TMR6_7,                                   \
+       .hw_count =                                                              \
+       {                                                                        \
+            .u32CountUpCond     = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING,       \
+            .u32CountDownCond   = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING,     \
+       },                                                                       \
+       .isr =                                                                   \
+       {                                                                        \
+            .enIntSrc_OVF   = INT_SRC_TMR6_7_OVF,                               \
+            .enIRQn_OVF     = BSP_PULSE_ENCODER_TMR6_7_OVF_IRQ_NUM,             \
+            .u8Int_Prio_OVF = BSP_PULSE_ENCODER_TMR6_7_OVF_IRQ_PRIO,            \
+            .enIntSrc_UDF   = INT_SRC_TMR6_7_UDF,                               \
+            .enIRQn_UDF     = BSP_PULSE_ENCODER_TMR6_7_UDF_IRQ_NUM,             \
+            .u8Int_Prio_UDF = BSP_PULSE_ENCODER_TMR6_7_UDF_IRQ_PRIO,            \
+       },                                                                       \
+       .u32PeriodValue  = 1000UL,                                               \
+       .name            = "pulse_67"                                            \
+    }
+#endif /* PULSE_ENCODER_TMR6_7_CONFIG */
+#endif /* BSP_USING_PULSE_ENCODER_TMR6_7 */
+
+#ifdef BSP_USING_PULSE_ENCODER_TMR6_8
+#ifndef PULSE_ENCODER_TMR6_8_CONFIG
+#define PULSE_ENCODER_TMR6_8_CONFIG                                             \
+    {                                                                           \
+       .tmr_handler     = CM_TMR6_8,                                            \
+       .u32Fcg2Periph   = FCG2_PERIPH_TMR6_8,                                   \
+       .hw_count =                                                              \
+       {                                                                        \
+            .u32CountUpCond     = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING,       \
+            .u32CountDownCond   = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING,     \
+       },                                                                       \
+       .isr =                                                                   \
+       {                                                                        \
+            .enIntSrc_OVF   = INT_SRC_TMR6_8_OVF,                               \
+            .enIRQn_OVF     = BSP_PULSE_ENCODER_TMR6_8_OVF_IRQ_NUM,             \
+            .u8Int_Prio_OVF = BSP_PULSE_ENCODER_TMR6_8_OVF_IRQ_PRIO,            \
+            .enIntSrc_UDF   = INT_SRC_TMR6_8_UDF,                               \
+            .enIRQn_UDF     = BSP_PULSE_ENCODER_TMR6_8_UDF_IRQ_NUM,             \
+            .u8Int_Prio_UDF = BSP_PULSE_ENCODER_TMR6_8_UDF_IRQ_PRIO,            \
+       },                                                                       \
+       .u32PeriodValue  = 1000UL,                                               \
+       .name            = "pulse_68"                                            \
+    }
+#endif /* PULSE_ENCODER_TMR6_8_CONFIG */
+#endif /* BSP_USING_PULSE_ENCODER_TMR6_8 */
+
+#endif /* RT_USING_PULSE_ENCODER */
+
+#endif /* __PULSE_ENCODER_CONFIG_H__ */

bsp/hc32/ev_hc32f472_lqfp100/board/config/pwm_tmr_config.h

@@ -0,0 +1,882 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2024-02-20     CDT          first version
+ */
+
+#ifndef __PWM_TMR_CONFIG_H__
+#define __PWM_TMR_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_PWM_TMRA
+
+#ifdef BSP_USING_PWM_TMRA_1
+#ifndef PWM_TMRA_1_CONFIG
+#define PWM_TMRA_1_CONFIG                                       \
+    {                                                           \
+        .name                           = "pwm_a1",             \
+        .instance                       = CM_TMRA_1,            \
+        .channel                        = 0,                    \
+        .stcTmraInit =                                          \
+        {                                                       \
+            .u8CountSrc                 = TMRA_CNT_SRC_SW,      \
+            .u32PeriodValue             = 0xFFFF,               \
+            .sw_count =                                         \
+            {                                                   \
+                .u8ClockDiv             = TMRA_CLK_DIV1,        \
+                .u8CountMode            = TMRA_MD_SAWTOOTH,     \
+                .u8CountDir             = TMRA_DIR_DOWN,        \
+            },                                                  \
+            .u8CountReload              = TMRA_CNT_RELOAD_ENABLE\
+        },                                                      \
+        .stcPwmInit =                                           \
+        {                                                       \
+            .u32CompareValue            = 0x0000,               \
+            .u16StartPolarity           = TMRA_PWM_LOW,         \
+            .u16StopPolarity            = TMRA_PWM_LOW,         \
+            .u16CompareMatchPolarity    = TMRA_PWM_HIGH,        \
+            .u16PeriodMatchPolarity     = TMRA_PWM_LOW,         \
+        },                                                      \
+    }
+#endif /* PWM_TMRA_1_CONFIG */
+#endif /* BSP_USING_PWM_TMRA_1 */
+
+#ifdef BSP_USING_PWM_TMRA_2
+#ifndef PWM_TMRA_2_CONFIG
+#define PWM_TMRA_2_CONFIG                                       \
+    {                                                           \
+        .name                           = "pwm_a2",             \
+        .instance                       = CM_TMRA_2,            \
+        .channel                        = 0,                    \
+        .stcTmraInit =                                          \
+        {                                                       \
+            .u8CountSrc                 = TMRA_CNT_SRC_SW,      \
+            .u32PeriodValue             = 0xFFFF,               \
+            .sw_count =                                         \
+            {                                                   \
+                .u8ClockDiv             = TMRA_CLK_DIV1,        \
+                .u8CountMode            = TMRA_MD_SAWTOOTH,     \
+                .u8CountDir             = TMRA_DIR_DOWN,        \
+            },                                                  \
+            .u8CountReload              = TMRA_CNT_RELOAD_ENABLE\
+        },                                                      \
+        .stcPwmInit =                                           \
+        {                                                       \
+            .u32CompareValue            = 0x0000,               \
+            .u16StartPolarity           = TMRA_PWM_LOW,         \
+            .u16StopPolarity            = TMRA_PWM_LOW,         \
+            .u16CompareMatchPolarity    = TMRA_PWM_HIGH,        \
+            .u16PeriodMatchPolarity     = TMRA_PWM_LOW,         \
+        },                                                      \
+    }
+#endif /* PWM_TMRA_2_CONFIG */
+#endif /* BSP_USING_PWM_TMRA_2 */
+
+#ifdef BSP_USING_PWM_TMRA_3
+#ifndef PWM_TMRA_3_CONFIG
+#define PWM_TMRA_3_CONFIG                                       \
+    {                                                           \
+        .name                           = "pwm_a3",             \
+        .instance                       = CM_TMRA_3,            \
+        .channel                        = 0,                    \
+        .stcTmraInit =                                          \
+        {                                                       \
+            .u8CountSrc                 = TMRA_CNT_SRC_SW,      \
+            .u32PeriodValue             = 0xFFFF,               \
+            .sw_count =                                         \
+            {                                                   \
+                .u8ClockDiv             = TMRA_CLK_DIV1,        \
+                .u8CountMode            = TMRA_MD_SAWTOOTH,     \
+                .u8CountDir             = TMRA_DIR_DOWN,        \
+            },                                                  \
+            .u8CountReload              = TMRA_CNT_RELOAD_ENABLE\
+        },                                                      \
+        .stcPwmInit =                                           \
+        {                                                       \
+            .u32CompareValue            = 0x0000,               \
+            .u16StartPolarity           = TMRA_PWM_LOW,         \
+            .u16StopPolarity            = TMRA_PWM_LOW,         \
+            .u16CompareMatchPolarity    = TMRA_PWM_HIGH,        \
+            .u16PeriodMatchPolarity     = TMRA_PWM_LOW,         \
+        },                                                      \
+    }
+#endif /* PWM_TMRA_3_CONFIG */
+#endif /* BSP_USING_PWM_TMRA_3 */
+
+#ifdef BSP_USING_PWM_TMRA_4
+#ifndef PWM_TMRA_4_CONFIG
+#define PWM_TMRA_4_CONFIG                                       \
+    {                                                           \
+        .name                           = "pwm_a4",             \
+        .instance                       = CM_TMRA_4,            \
+        .channel                        = 0,                    \
+        .stcTmraInit =                                          \
+        {                                                       \
+            .u8CountSrc                 = TMRA_CNT_SRC_SW,      \
+            .u32PeriodValue             = 0xFFFF,               \
+            .sw_count =                                         \
+            {                                                   \
+                .u8ClockDiv             = TMRA_CLK_DIV1,        \
+                .u8CountMode            = TMRA_MD_SAWTOOTH,     \
+                .u8CountDir             = TMRA_DIR_DOWN,        \
+            },                                                  \
+            .u8CountReload              = TMRA_CNT_RELOAD_ENABLE\
+        },                                                      \
+        .stcPwmInit =                                           \
+        {                                                       \
+            .u32CompareValue            = 0x0000,               \
+            .u16StartPolarity           = TMRA_PWM_LOW,         \
+            .u16StopPolarity            = TMRA_PWM_LOW,         \
+            .u16CompareMatchPolarity    = TMRA_PWM_HIGH,        \
+            .u16PeriodMatchPolarity     = TMRA_PWM_LOW,         \
+        },                                                      \
+    }
+#endif /* PWM_TMRA_4_CONFIG */
+#endif /* BSP_USING_PWM_TMRA_4 */
+
+#ifdef BSP_USING_PWM_TMRA_5
+#ifndef PWM_TMRA_5_CONFIG
+#define PWM_TMRA_5_CONFIG                                       \
+    {                                                           \
+        .name                           = "pwm_a5",             \
+        .instance                       = CM_TMRA_5,            \
+        .channel                        = 0,                    \
+        .stcTmraInit =                                          \
+        {                                                       \
+            .u8CountSrc                 = TMRA_CNT_SRC_SW,      \
+            .u32PeriodValue             = 0xFFFF,               \
+            .sw_count =                                         \
+            {                                                   \
+                .u8ClockDiv             = TMRA_CLK_DIV1,        \
+                .u8CountMode            = TMRA_MD_SAWTOOTH,     \
+                .u8CountDir             = TMRA_DIR_DOWN,        \
+            },                                                  \
+            .u8CountReload              = TMRA_CNT_RELOAD_ENABLE\
+        },                                                      \
+        .stcPwmInit =                                           \
+        {                                                       \
+            .u32CompareValue            = 0x0000,               \
+            .u16StartPolarity           = TMRA_PWM_LOW,         \
+            .u16StopPolarity            = TMRA_PWM_LOW,         \
+            .u16CompareMatchPolarity    = TMRA_PWM_HIGH,        \
+            .u16PeriodMatchPolarity     = TMRA_PWM_LOW,         \
+        },                                                      \
+    }
+#endif /* PWM_TMRA_5_CONFIG */
+#endif /* BSP_USING_PWM_TMRA_5 */
+
+#ifdef BSP_USING_PWM_TMRA_6
+#ifndef PWM_TMRA_6_CONFIG
+#define PWM_TMRA_6_CONFIG                                       \
+    {                                                           \
+        .name                           = "pwm_a6",             \
+        .instance                       = CM_TMRA_6,            \
+        .channel                        = 0,                    \
+        .stcTmraInit =                                          \
+        {                                                       \
+            .u8CountSrc                 = TMRA_CNT_SRC_SW,      \
+            .u32PeriodValue             = 0xFFFF,               \
+            .sw_count =                                         \
+            {                                                   \
+                .u8ClockDiv             = TMRA_CLK_DIV1,        \
+                .u8CountMode            = TMRA_MD_SAWTOOTH,     \
+                .u8CountDir             = TMRA_DIR_DOWN,        \
+            },                                                  \
+            .u8CountReload              = TMRA_CNT_RELOAD_ENABLE\
+        },                                                      \
+        .stcPwmInit =                                           \
+        {                                                       \
+            .u32CompareValue            = 0x0000,               \
+            .u16StartPolarity           = TMRA_PWM_LOW,         \
+            .u16StopPolarity            = TMRA_PWM_LOW,         \
+            .u16CompareMatchPolarity    = TMRA_PWM_HIGH,        \
+            .u16PeriodMatchPolarity     = TMRA_PWM_LOW,         \
+        },                                                      \
+    }
+#endif /* PWM_TMRA_6_CONFIG */
+#endif /* BSP_USING_PWM_TMRA_6 */
+
+#ifdef BSP_USING_PWM_TMRA_7
+#ifndef PWM_TMRA_7_CONFIG
+#define PWM_TMRA_7_CONFIG                                       \
+    {                                                           \
+        .name                           = "pwm_a7",             \
+        .instance                       = CM_TMRA_7,            \
+        .channel                        = 0,                    \
+        .stcTmraInit =                                          \
+        {                                                       \
+            .u8CountSrc                 = TMRA_CNT_SRC_SW,      \
+            .u32PeriodValue             = 0xFFFF,               \
+            .sw_count =                                         \
+            {                                                   \
+                .u8ClockDiv             = TMRA_CLK_DIV1,        \
+                .u8CountMode            = TMRA_MD_SAWTOOTH,     \
+                .u8CountDir             = TMRA_DIR_DOWN,        \
+            },                                                  \
+            .u8CountReload              = TMRA_CNT_RELOAD_ENABLE\
+        },                                                      \
+        .stcPwmInit =                                           \
+        {                                                       \
+            .u32CompareValue            = 0x0000,               \
+            .u16StartPolarity           = TMRA_PWM_LOW,         \
+            .u16StopPolarity            = TMRA_PWM_LOW,         \
+            .u16CompareMatchPolarity    = TMRA_PWM_HIGH,        \
+            .u16PeriodMatchPolarity     = TMRA_PWM_LOW,         \
+        },                                                      \
+    }
+#endif /* PWM_TMRA_7_CONFIG */
+#endif /* BSP_USING_PWM_TMRA_7 */
+
+#ifdef BSP_USING_PWM_TMRA_8
+#ifndef PWM_TMRA_8_CONFIG
+#define PWM_TMRA_8_CONFIG                                       \
+    {                                                           \
+        .name                           = "pwm_a8",             \
+        .instance                       = CM_TMRA_8,            \
+        .channel                        = 0,                    \
+        .stcTmraInit =                                          \
+        {                                                       \
+            .u8CountSrc                 = TMRA_CNT_SRC_SW,      \
+            .u32PeriodValue             = 0xFFFF,               \
+            .sw_count =                                         \
+            {                                                   \
+                .u8ClockDiv             = TMRA_CLK_DIV1,        \
+                .u8CountMode            = TMRA_MD_SAWTOOTH,     \
+                .u8CountDir             = TMRA_DIR_DOWN,        \
+            },                                                  \
+            .u8CountReload              = TMRA_CNT_RELOAD_ENABLE\
+        },                                                      \
+        .stcPwmInit =                                           \
+        {                                                       \
+            .u32CompareValue            = 0x0000,               \
+            .u16StartPolarity           = TMRA_PWM_LOW,         \
+            .u16StopPolarity            = TMRA_PWM_LOW,         \
+            .u16CompareMatchPolarity    = TMRA_PWM_HIGH,        \
+            .u16PeriodMatchPolarity     = TMRA_PWM_LOW,         \
+        },                                                      \
+    }
+#endif /* PWM_TMRA_8_CONFIG */
+#endif /* BSP_USING_PWM_TMRA_8 */
+
+#ifdef BSP_USING_PWM_TMRA_9
+#ifndef PWM_TMRA_9_CONFIG
+#define PWM_TMRA_9_CONFIG                                       \
+    {                                                           \
+        .name                           = "pwm_a9",             \
+        .instance                       = CM_TMRA_9,            \
+        .channel                        = 0,                    \
+        .stcTmraInit =                                          \
+        {                                                       \
+            .u8CountSrc                 = TMRA_CNT_SRC_SW,      \
+            .u32PeriodValue             = 0xFFFF,               \
+            .sw_count =                                         \
+            {                                                   \
+                .u8ClockDiv             = TMRA_CLK_DIV1,        \
+                .u8CountMode            = TMRA_MD_SAWTOOTH,     \
+                .u8CountDir             = TMRA_DIR_DOWN,        \
+            },                                                  \
+            .u8CountReload              = TMRA_CNT_RELOAD_ENABLE\
+        },                                                      \
+        .stcPwmInit =                                           \
+        {                                                       \
+            .u32CompareValue            = 0x0000,               \
+            .u16StartPolarity           = TMRA_PWM_LOW,         \
+            .u16StopPolarity            = TMRA_PWM_LOW,         \
+            .u16CompareMatchPolarity    = TMRA_PWM_HIGH,        \
+            .u16PeriodMatchPolarity     = TMRA_PWM_LOW,         \
+        },                                                      \
+    }
+#endif /* PWM_TMRA_9_CONFIG */
+#endif /* BSP_USING_PWM_TMRA_9 */
+
+#ifdef BSP_USING_PWM_TMRA_10
+#ifndef PWM_TMRA_10_CONFIG
+#define PWM_TMRA_10_CONFIG                                      \
+    {                                                           \
+        .name                           = "pwm_a10",            \
+        .instance                       = CM_TMRA_10,           \
+        .channel                        = 0,                    \
+        .stcTmraInit =                                          \
+        {                                                       \
+            .u8CountSrc                 = TMRA_CNT_SRC_SW,      \
+            .u32PeriodValue             = 0xFFFF,               \
+            .sw_count =                                         \
+            {                                                   \
+                .u8ClockDiv             = TMRA_CLK_DIV1,        \
+                .u8CountMode            = TMRA_MD_SAWTOOTH,     \
+                .u8CountDir             = TMRA_DIR_DOWN,        \
+            },                                                  \
+            .u8CountReload              = TMRA_CNT_RELOAD_ENABLE\
+        },                                                      \
+        .stcPwmInit =                                           \
+        {                                                       \
+            .u32CompareValue            = 0x0000,               \
+            .u16StartPolarity           = TMRA_PWM_LOW,         \
+            .u16StopPolarity            = TMRA_PWM_LOW,         \
+            .u16CompareMatchPolarity    = TMRA_PWM_HIGH,        \
+            .u16PeriodMatchPolarity     = TMRA_PWM_LOW,         \
+        },                                                      \
+    }
+#endif /* PWM_TMRA_10_CONFIG */
+#endif /* BSP_USING_PWM_TMRA_10 */
+
+#ifdef BSP_USING_PWM_TMRA_11
+#ifndef PWM_TMRA_11_CONFIG
+#define PWM_TMRA_11_CONFIG                                      \
+    {                                                           \
+        .name                           = "pwm_a11",            \
+        .instance                       = CM_TMRA_11,           \
+        .channel                        = 0,                    \
+        .stcTmraInit =                                          \
+        {                                                       \
+            .u8CountSrc                 = TMRA_CNT_SRC_SW,      \
+            .u32PeriodValue             = 0xFFFF,               \
+            .sw_count =                                         \
+            {                                                   \
+                .u8ClockDiv             = TMRA_CLK_DIV1,        \
+                .u8CountMode            = TMRA_MD_SAWTOOTH,     \
+                .u8CountDir             = TMRA_DIR_DOWN,        \
+            },                                                  \
+            .u8CountReload              = TMRA_CNT_RELOAD_ENABLE\
+        },                                                      \
+        .stcPwmInit =                                           \
+        {                                                       \
+            .u32CompareValue            = 0x0000,               \
+            .u16StartPolarity           = TMRA_PWM_LOW,         \
+            .u16StopPolarity            = TMRA_PWM_LOW,         \
+            .u16CompareMatchPolarity    = TMRA_PWM_HIGH,        \
+            .u16PeriodMatchPolarity     = TMRA_PWM_LOW,         \
+        },                                                      \
+    }
+#endif /* PWM_TMRA_11_CONFIG */
+#endif /* BSP_USING_PWM_TMRA_11 */
+
+#ifdef BSP_USING_PWM_TMRA_12
+#ifndef PWM_TMRA_12_CONFIG
+#define PWM_TMRA_12_CONFIG                                      \
+    {                                                           \
+        .name                           = "pwm_a12",            \
+        .instance                       = CM_TMRA_12,           \
+        .channel                        = 0,                    \
+        .stcTmraInit =                                          \
+        {                                                       \
+            .u8CountSrc                 = TMRA_CNT_SRC_SW,      \
+            .u32PeriodValue             = 0xFFFF,               \
+            .sw_count =                                         \
+            {                                                   \
+                .u8ClockDiv             = TMRA_CLK_DIV1,        \
+                .u8CountMode            = TMRA_MD_SAWTOOTH,     \
+                .u8CountDir             = TMRA_DIR_DOWN,        \
+            },                                                  \
+            .u8CountReload              = TMRA_CNT_RELOAD_ENABLE\
+        },                                                      \
+        .stcPwmInit =                                           \
+        {                                                       \
+            .u32CompareValue            = 0x0000,               \
+            .u16StartPolarity           = TMRA_PWM_LOW,         \
+            .u16StopPolarity            = TMRA_PWM_LOW,         \
+            .u16CompareMatchPolarity    = TMRA_PWM_HIGH,        \
+            .u16PeriodMatchPolarity     = TMRA_PWM_LOW,         \
+        },                                                      \
+    }
+#endif /* PWM_TMRA_12_CONFIG */
+#endif /* BSP_USING_PWM_TMRA_12 */
+
+#endif /* BSP_USING_PWM_TMRA */
+
+#ifdef BSP_USING_PWM_TMR4
+
+#ifdef BSP_USING_PWM_TMR4_1
+#ifndef PWM_TMR4_1_CONFIG
+#define PWM_TMR4_1_CONFIG                                       \
+    {                                                           \
+        .name                           = "pwm_t41",            \
+        .instance                       = CM_TMR4_1,            \
+        .channel                        = 0,                    \
+        .stcTmr4Init =                                          \
+        {                                                       \
+            .u16ClockDiv                = TMR4_CLK_DIV1,        \
+            .u16PeriodValue             = 0xFFFFU,              \
+            .u16CountMode               = TMR4_MD_SAWTOOTH,     \
+            .u16ClockSrc               = TMR4_CLK_SRC_INTERNCLK,\
+        },                                                      \
+        .stcTmr4OcInit =                                        \
+        {                                                       \
+            .u16CompareValue            = 0x0000,               \
+            .u16OcInvalidPolarity       = TMR4_OC_INVD_LOW,     \
+            .u16CompareModeBufCond     = TMR4_OC_BUF_COND_IMMED,\
+            .u16CompareValueBufCond    = TMR4_OC_BUF_COND_PEAK, \
+            .u16BufLinkTransObject      = 0U,                   \
+        },                                                      \
+        .stcTmr4PwmInit =                                       \
+        {                                                       \
+            .u16Mode                    = TMR4_PWM_MD_THROUGH,  \
+            .u16ClockDiv                = TMR4_PWM_CLK_DIV1,    \
+            .u16Polarity           = TMR4_PWM_OXH_HOLD_OXL_HOLD,\
+        },                                                      \
+    }
+#endif /* PWM_TMR4_1_CONFIG */
+#endif /* BSP_USING_PWM_TMR4_1 */
+
+#ifdef BSP_USING_PWM_TMR4_2
+#ifndef PWM_TMR4_2_CONFIG
+#define PWM_TMR4_2_CONFIG                                       \
+    {                                                           \
+        .name                           = "pwm_t42",            \
+        .instance                       = CM_TMR4_2,            \
+        .channel                        = 0,                    \
+        .stcTmr4Init =                                          \
+        {                                                       \
+            .u16ClockDiv                = TMR4_CLK_DIV1,        \
+            .u16PeriodValue             = 0xFFFFU,              \
+            .u16CountMode               = TMR4_MD_SAWTOOTH,     \
+            .u16ClockSrc               = TMR4_CLK_SRC_INTERNCLK,\
+        },                                                      \
+        .stcTmr4OcInit =                                        \
+        {                                                       \
+            .u16CompareValue            = 0x0000,               \
+            .u16OcInvalidPolarity       = TMR4_OC_INVD_LOW,     \
+            .u16CompareModeBufCond     = TMR4_OC_BUF_COND_IMMED,\
+            .u16CompareValueBufCond    = TMR4_OC_BUF_COND_PEAK, \
+            .u16BufLinkTransObject      = 0U,                   \
+        },                                                      \
+        .stcTmr4PwmInit =                                       \
+        {                                                       \
+            .u16Mode                    = TMR4_PWM_MD_THROUGH,  \
+            .u16ClockDiv                = TMR4_PWM_CLK_DIV1,    \
+            .u16Polarity           = TMR4_PWM_OXH_HOLD_OXL_HOLD,\
+        },                                                      \
+    }
+#endif /* PWM_TMR4_2_CONFIG */
+#endif /* BSP_USING_PWM_TMR4_2 */
+
+#ifdef BSP_USING_PWM_TMR4_3
+#ifndef PWM_TMR4_3_CONFIG
+#define PWM_TMR4_3_CONFIG                                       \
+    {                                                           \
+        .name                           = "pwm_t43",            \
+        .instance                       = CM_TMR4_3,            \
+        .channel                        = 0,                    \
+        .stcTmr4Init =                                          \
+        {                                                       \
+            .u16ClockDiv                = TMR4_CLK_DIV1,        \
+            .u16PeriodValue             = 0xFFFFU,              \
+            .u16CountMode               = TMR4_MD_SAWTOOTH,     \
+            .u16ClockSrc               = TMR4_CLK_SRC_INTERNCLK,\
+        },                                                      \
+        .stcTmr4OcInit =                                        \
+        {                                                       \
+            .u16CompareValue            = 0x0000,               \
+            .u16OcInvalidPolarity       = TMR4_OC_INVD_LOW,     \
+            .u16CompareModeBufCond     = TMR4_OC_BUF_COND_IMMED,\
+            .u16CompareValueBufCond    = TMR4_OC_BUF_COND_PEAK, \
+            .u16BufLinkTransObject      = 0U,                   \
+        },                                                      \
+        .stcTmr4PwmInit =                                       \
+        {                                                       \
+            .u16Mode                    = TMR4_PWM_MD_THROUGH,  \
+            .u16ClockDiv                = TMR4_PWM_CLK_DIV1,    \
+            .u16Polarity           = TMR4_PWM_OXH_HOLD_OXL_HOLD,\
+        },                                                      \
+    }
+#endif /* PWM_TMR4_3_CONFIG */
+#endif /* BSP_USING_PWM_TMR4_3 */
+
+#endif /* BSP_USING_PWM_TMR4 */
+
+#ifdef BSP_USING_PWM_TMR6
+
+#ifdef BSP_USING_PWM_TMR6_1
+#ifndef PWM_TMR6_1_CONFIG
+#define PWM_TMR6_1_CONFIG                                       \
+    {                                                           \
+        .name                           = "pwm_t61",            \
+        .instance                       = CM_TMR6_1,            \
+        .channel                        = 0,                    \
+        .stcTmr6Init =                                          \
+        {                                                       \
+            .u8CountSrc                 = TMR6_CNT_SRC_SW,      \
+            .sw_count =                                         \
+            {                                                   \
+                .u32ClockDiv            = TMR6_CLK_DIV1,        \
+                .u32CountMode           = TMR6_MD_SAWTOOTH,     \
+                .u32CountDir            = TMR6_CNT_DOWN,        \
+            },                                                  \
+            .u32PeriodValue             = 0xFFFF,               \
+            .u32CountReload             = TMR6_CNT_RELOAD_ON,   \
+        },                                                      \
+        .stcPwmInit =                                           \
+        {                                                       \
+            {                                                   \
+                .u32CompareValue            = 0x0000,           \
+                .u32StartPolarity           = TMR6_PWM_LOW,     \
+                .u32StopPolarity            = TMR6_PWM_LOW,     \
+                .u32CountUpMatchAPolarity   = TMR6_PWM_HIGH,    \
+                .u32CountDownMatchAPolarity = TMR6_PWM_HIGH,    \
+                .u32CountUpMatchBPolarity   = TMR6_PWM_HOLD,    \
+                .u32CountDownMatchBPolarity = TMR6_PWM_HOLD,    \
+                .u32UdfPolarity             = TMR6_PWM_LOW,     \
+                .u32OvfPolarity             = TMR6_PWM_LOW,     \
+            },                                                  \
+            {                                                   \
+                .u32CompareValue            = 0x0000,           \
+                .u32StartPolarity           = TMR6_PWM_LOW,     \
+                .u32StopPolarity            = TMR6_PWM_LOW,     \
+                .u32CountUpMatchAPolarity   = TMR6_PWM_HOLD,    \
+                .u32CountDownMatchAPolarity = TMR6_PWM_HOLD,    \
+                .u32CountUpMatchBPolarity   = TMR6_PWM_HIGH,    \
+                .u32CountDownMatchBPolarity = TMR6_PWM_HIGH,    \
+                .u32UdfPolarity             = TMR6_PWM_LOW,     \
+                .u32OvfPolarity             = TMR6_PWM_LOW,     \
+            }                                                   \
+        },                                                      \
+    }
+#endif /* PWM_TMR6_1_CONFIG */
+#endif /* BSP_USING_PWM_TMR6_1 */
+#ifdef BSP_USING_PWM_TMR6_2
+#ifndef PWM_TMR6_2_CONFIG
+#define PWM_TMR6_2_CONFIG                                       \
+    {                                                           \
+        .name                           = "pwm_t61",            \
+        .instance                       = CM_TMR6_2,            \
+        .channel                        = 0,                    \
+        .stcTmr6Init =                                          \
+        {                                                       \
+            .u8CountSrc                 = TMR6_CNT_SRC_SW,      \
+            .sw_count =                                         \
+            {                                                   \
+                .u32ClockDiv            = TMR6_CLK_DIV1,        \
+                .u32CountMode           = TMR6_MD_SAWTOOTH,     \
+                .u32CountDir            = TMR6_CNT_DOWN,        \
+            },                                                  \
+            .u32PeriodValue             = 0xFFFF,               \
+            .u32CountReload             = TMR6_CNT_RELOAD_ON,   \
+        },                                                      \
+        .stcPwmInit =                                           \
+        {                                                       \
+            {                                                   \
+                .u32CompareValue            = 0x0000,           \
+                .u32StartPolarity           = TMR6_PWM_LOW,     \
+                .u32StopPolarity            = TMR6_PWM_LOW,     \
+                .u32CountUpMatchAPolarity   = TMR6_PWM_HIGH,    \
+                .u32CountDownMatchAPolarity = TMR6_PWM_HIGH,    \
+                .u32CountUpMatchBPolarity   = TMR6_PWM_HOLD,    \
+                .u32CountDownMatchBPolarity = TMR6_PWM_HOLD,    \
+                .u32UdfPolarity             = TMR6_PWM_LOW,     \
+                .u32OvfPolarity             = TMR6_PWM_LOW,     \
+            },                                                  \
+            {                                                   \
+                .u32CompareValue            = 0x0000,           \
+                .u32StartPolarity           = TMR6_PWM_LOW,     \
+                .u32StopPolarity            = TMR6_PWM_LOW,     \
+                .u32CountUpMatchAPolarity   = TMR6_PWM_HOLD,    \
+                .u32CountDownMatchAPolarity = TMR6_PWM_HOLD,    \
+                .u32CountUpMatchBPolarity   = TMR6_PWM_HIGH,    \
+                .u32CountDownMatchBPolarity = TMR6_PWM_HIGH,    \
+                .u32UdfPolarity             = TMR6_PWM_LOW,     \
+                .u32OvfPolarity             = TMR6_PWM_LOW,     \
+            }                                                   \
+        },                                                      \
+    }
+#endif /* PWM_TMR6_2_CONFIG */
+#endif /* BSP_USING_PWM_TMR6_2 */
+#ifdef BSP_USING_PWM_TMR6_3
+#ifndef PWM_TMR6_3_CONFIG
+#define PWM_TMR6_3_CONFIG                                       \
+    {                                                           \
+        .name                           = "pwm_t61",            \
+        .instance                       = CM_TMR6_3,            \
+        .channel                        = 0,                    \
+        .stcTmr6Init =                                          \
+        {                                                       \
+            .u8CountSrc                 = TMR6_CNT_SRC_SW,      \
+            .sw_count =                                         \
+            {                                                   \
+                .u32ClockDiv            = TMR6_CLK_DIV1,        \
+                .u32CountMode           = TMR6_MD_SAWTOOTH,     \
+                .u32CountDir            = TMR6_CNT_DOWN,        \
+            },                                                  \
+            .u32PeriodValue             = 0xFFFF,               \
+            .u32CountReload             = TMR6_CNT_RELOAD_ON,   \
+        },                                                      \
+        .stcPwmInit =                                           \
+        {                                                       \
+            {                                                   \
+                .u32CompareValue            = 0x0000,           \
+                .u32StartPolarity           = TMR6_PWM_LOW,     \
+                .u32StopPolarity            = TMR6_PWM_LOW,     \
+                .u32CountUpMatchAPolarity   = TMR6_PWM_HIGH,    \
+                .u32CountDownMatchAPolarity = TMR6_PWM_HIGH,    \
+                .u32CountUpMatchBPolarity   = TMR6_PWM_HOLD,    \
+                .u32CountDownMatchBPolarity = TMR6_PWM_HOLD,    \
+                .u32UdfPolarity             = TMR6_PWM_LOW,     \
+                .u32OvfPolarity             = TMR6_PWM_LOW,     \
+            },                                                  \
+            {                                                   \
+                .u32CompareValue            = 0x0000,           \
+                .u32StartPolarity           = TMR6_PWM_LOW,     \
+                .u32StopPolarity            = TMR6_PWM_LOW,     \
+                .u32CountUpMatchAPolarity   = TMR6_PWM_HOLD,    \
+                .u32CountDownMatchAPolarity = TMR6_PWM_HOLD,    \
+                .u32CountUpMatchBPolarity   = TMR6_PWM_HIGH,    \
+                .u32CountDownMatchBPolarity = TMR6_PWM_HIGH,    \
+                .u32UdfPolarity             = TMR6_PWM_LOW,     \
+                .u32OvfPolarity             = TMR6_PWM_LOW,     \
+            }                                                   \
+        },                                                      \
+    }
+#endif /* PWM_TMR6_3_CONFIG */
+#endif /* BSP_USING_PWM_TMR6_3 */
+#ifdef BSP_USING_PWM_TMR6_4
+#ifndef PWM_TMR6_4_CONFIG
+#define PWM_TMR6_4_CONFIG                                       \
+    {                                                           \
+        .name                           = "pwm_t61",            \
+        .instance                       = CM_TMR6_4,            \
+        .channel                        = 0,                    \
+        .stcTmr6Init =                                          \
+        {                                                       \
+            .u8CountSrc                 = TMR6_CNT_SRC_SW,      \
+            .sw_count =                                         \
+            {                                                   \
+                .u32ClockDiv            = TMR6_CLK_DIV1,        \
+                .u32CountMode           = TMR6_MD_SAWTOOTH,     \
+                .u32CountDir            = TMR6_CNT_DOWN,        \
+            },                                                  \
+            .u32PeriodValue             = 0xFFFF,               \
+            .u32CountReload             = TMR6_CNT_RELOAD_ON,   \
+        },                                                      \
+        .stcPwmInit =                                           \
+        {                                                       \
+            {                                                   \
+                .u32CompareValue            = 0x0000,           \
+                .u32StartPolarity           = TMR6_PWM_LOW,     \
+                .u32StopPolarity            = TMR6_PWM_LOW,     \
+                .u32CountUpMatchAPolarity   = TMR6_PWM_HIGH,    \
+                .u32CountDownMatchAPolarity = TMR6_PWM_HIGH,    \
+                .u32CountUpMatchBPolarity   = TMR6_PWM_HOLD,    \
+                .u32CountDownMatchBPolarity = TMR6_PWM_HOLD,    \
+                .u32UdfPolarity             = TMR6_PWM_LOW,     \
+                .u32OvfPolarity             = TMR6_PWM_LOW,     \
+            },                                                  \
+            {                                                   \
+                .u32CompareValue            = 0x0000,           \
+                .u32StartPolarity           = TMR6_PWM_LOW,     \
+                .u32StopPolarity            = TMR6_PWM_LOW,     \
+                .u32CountUpMatchAPolarity   = TMR6_PWM_HOLD,    \
+                .u32CountDownMatchAPolarity = TMR6_PWM_HOLD,    \
+                .u32CountUpMatchBPolarity   = TMR6_PWM_HIGH,    \
+                .u32CountDownMatchBPolarity = TMR6_PWM_HIGH,    \
+                .u32UdfPolarity             = TMR6_PWM_LOW,     \
+                .u32OvfPolarity             = TMR6_PWM_LOW,     \
+            }                                                   \
+        },                                                      \
+    }
+#endif /* PWM_TMR6_4_CONFIG */
+#endif /* BSP_USING_PWM_TMR6_4 */
+#ifdef BSP_USING_PWM_TMR6_5
+#ifndef PWM_TMR6_5_CONFIG
+#define PWM_TMR6_5_CONFIG                                       \
+    {                                                           \
+        .name                           = "pwm_t61",            \
+        .instance                       = CM_TMR6_5,            \
+        .channel                        = 0,                    \
+        .stcTmr6Init =                                          \
+        {                                                       \
+            .u8CountSrc                 = TMR6_CNT_SRC_SW,      \
+            .sw_count =                                         \
+            {                                                   \
+                .u32ClockDiv            = TMR6_CLK_DIV1,        \
+                .u32CountMode           = TMR6_MD_SAWTOOTH,     \
+                .u32CountDir            = TMR6_CNT_DOWN,        \
+            },                                                  \
+            .u32PeriodValue             = 0xFFFF,               \
+            .u32CountReload             = TMR6_CNT_RELOAD_ON,   \
+        },                                                      \
+        .stcPwmInit =                                           \
+        {                                                       \
+            {                                                   \
+                .u32CompareValue            = 0x0000,           \
+                .u32StartPolarity           = TMR6_PWM_LOW,     \
+                .u32StopPolarity            = TMR6_PWM_LOW,     \
+                .u32CountUpMatchAPolarity   = TMR6_PWM_HIGH,    \
+                .u32CountDownMatchAPolarity = TMR6_PWM_HIGH,    \
+                .u32CountUpMatchBPolarity   = TMR6_PWM_HOLD,    \
+                .u32CountDownMatchBPolarity = TMR6_PWM_HOLD,    \
+                .u32UdfPolarity             = TMR6_PWM_LOW,     \
+                .u32OvfPolarity             = TMR6_PWM_LOW,     \
+            },                                                  \
+            {                                                   \
+                .u32CompareValue            = 0x0000,           \
+                .u32StartPolarity           = TMR6_PWM_LOW,     \
+                .u32StopPolarity            = TMR6_PWM_LOW,     \
+                .u32CountUpMatchAPolarity   = TMR6_PWM_HOLD,    \
+                .u32CountDownMatchAPolarity = TMR6_PWM_HOLD,    \
+                .u32CountUpMatchBPolarity   = TMR6_PWM_HIGH,    \
+                .u32CountDownMatchBPolarity = TMR6_PWM_HIGH,    \
+                .u32UdfPolarity             = TMR6_PWM_LOW,     \
+                .u32OvfPolarity             = TMR6_PWM_LOW,     \
+            }                                                   \
+        },                                                      \
+    }
+#endif /* PWM_TMR6_5_CONFIG */
+#endif /* BSP_USING_PWM_TMR6_5 */
+#ifdef BSP_USING_PWM_TMR6_6
+#ifndef PWM_TMR6_6_CONFIG
+#define PWM_TMR6_6_CONFIG                                       \
+    {                                                           \
+        .name                           = "pwm_t61",            \
+        .instance                       = CM_TMR6_6,            \
+        .channel                        = 0,                    \
+        .stcTmr6Init =                                          \
+        {                                                       \
+            .u8CountSrc                 = TMR6_CNT_SRC_SW,      \
+            .sw_count =                                         \
+            {                                                   \
+                .u32ClockDiv            = TMR6_CLK_DIV1,        \
+                .u32CountMode           = TMR6_MD_SAWTOOTH,     \
+                .u32CountDir            = TMR6_CNT_DOWN,        \
+            },                                                  \
+            .u32PeriodValue             = 0xFFFF,               \
+            .u32CountReload             = TMR6_CNT_RELOAD_ON,   \
+        },                                                      \
+        .stcPwmInit =                                           \
+        {                                                       \
+            {                                                   \
+                .u32CompareValue            = 0x0000,           \
+                .u32StartPolarity           = TMR6_PWM_LOW,     \
+                .u32StopPolarity            = TMR6_PWM_LOW,     \
+                .u32CountUpMatchAPolarity   = TMR6_PWM_HIGH,    \
+                .u32CountDownMatchAPolarity = TMR6_PWM_HIGH,    \
+                .u32CountUpMatchBPolarity   = TMR6_PWM_HOLD,    \
+                .u32CountDownMatchBPolarity = TMR6_PWM_HOLD,    \
+                .u32UdfPolarity             = TMR6_PWM_LOW,     \
+                .u32OvfPolarity             = TMR6_PWM_LOW,     \
+            },                                                  \
+            {                                                   \
+                .u32CompareValue            = 0x0000,           \
+                .u32StartPolarity           = TMR6_PWM_LOW,     \
+                .u32StopPolarity            = TMR6_PWM_LOW,     \
+                .u32CountUpMatchAPolarity   = TMR6_PWM_HOLD,    \
+                .u32CountDownMatchAPolarity = TMR6_PWM_HOLD,    \
+                .u32CountUpMatchBPolarity   = TMR6_PWM_HIGH,    \
+                .u32CountDownMatchBPolarity = TMR6_PWM_HIGH,    \
+                .u32UdfPolarity             = TMR6_PWM_LOW,     \
+                .u32OvfPolarity             = TMR6_PWM_LOW,     \
+            }                                                   \
+        },                                                      \
+    }
+#endif /* PWM_TMR6_6_CONFIG */
+#endif /* BSP_USING_PWM_TMR6_6 */
+#ifdef BSP_USING_PWM_TMR6_7
+#ifndef PWM_TMR6_7_CONFIG
+#define PWM_TMR6_7_CONFIG                                       \
+    {                                                           \
+        .name                           = "pwm_t61",            \
+        .instance                       = CM_TMR6_7,            \
+        .channel                        = 0,                    \
+        .stcTmr6Init =                                          \
+        {                                                       \
+            .u8CountSrc                 = TMR6_CNT_SRC_SW,      \
+            .sw_count =                                         \
+            {                                                   \
+                .u32ClockDiv            = TMR6_CLK_DIV1,        \
+                .u32CountMode           = TMR6_MD_SAWTOOTH,     \
+                .u32CountDir            = TMR6_CNT_DOWN,        \
+            },                                                  \
+            .u32PeriodValue             = 0xFFFF,               \
+            .u32CountReload             = TMR6_CNT_RELOAD_ON,   \
+        },                                                      \
+        .stcPwmInit =                                           \
+        {                                                       \
+            {                                                   \
+                .u32CompareValue            = 0x0000,           \
+                .u32StartPolarity           = TMR6_PWM_LOW,     \
+                .u32StopPolarity            = TMR6_PWM_LOW,     \
+                .u32CountUpMatchAPolarity   = TMR6_PWM_HIGH,    \
+                .u32CountDownMatchAPolarity = TMR6_PWM_HIGH,    \
+                .u32CountUpMatchBPolarity   = TMR6_PWM_HOLD,    \
+                .u32CountDownMatchBPolarity = TMR6_PWM_HOLD,    \
+                .u32UdfPolarity             = TMR6_PWM_LOW,     \
+                .u32OvfPolarity             = TMR6_PWM_LOW,     \
+            },                                                  \
+            {                                                   \
+                .u32CompareValue            = 0x0000,           \
+                .u32StartPolarity           = TMR6_PWM_LOW,     \
+                .u32StopPolarity            = TMR6_PWM_LOW,     \
+                .u32CountUpMatchAPolarity   = TMR6_PWM_HOLD,    \
+                .u32CountDownMatchAPolarity = TMR6_PWM_HOLD,    \
+                .u32CountUpMatchBPolarity   = TMR6_PWM_HIGH,    \
+                .u32CountDownMatchBPolarity = TMR6_PWM_HIGH,    \
+                .u32UdfPolarity             = TMR6_PWM_LOW,     \
+                .u32OvfPolarity             = TMR6_PWM_LOW,     \
+            }                                                   \
+        },                                                      \
+    }
+#endif /* PWM_TMR6_7_CONFIG */
+#endif /* BSP_USING_PWM_TMR6_7 */
+#ifdef BSP_USING_PWM_TMR6_8
+#ifndef PWM_TMR6_8_CONFIG
+#define PWM_TMR6_8_CONFIG                                       \
+    {                                                           \
+        .name                           = "pwm_t61",            \
+        .instance                       = CM_TMR6_8,            \
+        .channel                        = 0,                    \
+        .stcTmr6Init =                                          \
+        {                                                       \
+            .u8CountSrc                 = TMR6_CNT_SRC_SW,      \
+            .sw_count =                                         \
+            {                                                   \
+                .u32ClockDiv            = TMR6_CLK_DIV1,        \
+                .u32CountMode           = TMR6_MD_SAWTOOTH,     \
+                .u32CountDir            = TMR6_CNT_DOWN,        \
+            },                                                  \
+            .u32PeriodValue             = 0xFFFF,               \
+            .u32CountReload             = TMR6_CNT_RELOAD_ON,   \
+        },                                                      \
+        .stcPwmInit =                                           \
+        {                                                       \
+            {                                                   \
+                .u32CompareValue            = 0x0000,           \
+                .u32StartPolarity           = TMR6_PWM_LOW,     \
+                .u32StopPolarity            = TMR6_PWM_LOW,     \
+                .u32CountUpMatchAPolarity   = TMR6_PWM_HIGH,    \
+                .u32CountDownMatchAPolarity = TMR6_PWM_HIGH,    \
+                .u32CountUpMatchBPolarity   = TMR6_PWM_HOLD,    \
+                .u32CountDownMatchBPolarity = TMR6_PWM_HOLD,    \
+                .u32UdfPolarity             = TMR6_PWM_LOW,     \
+                .u32OvfPolarity             = TMR6_PWM_LOW,     \
+            },                                                  \
+            {                                                   \
+                .u32CompareValue            = 0x0000,           \
+                .u32StartPolarity           = TMR6_PWM_LOW,     \
+                .u32StopPolarity            = TMR6_PWM_LOW,     \
+                .u32CountUpMatchAPolarity   = TMR6_PWM_HOLD,    \
+                .u32CountDownMatchAPolarity = TMR6_PWM_HOLD,    \
+                .u32CountUpMatchBPolarity   = TMR6_PWM_HIGH,    \
+                .u32CountDownMatchBPolarity = TMR6_PWM_HIGH,    \
+                .u32UdfPolarity             = TMR6_PWM_LOW,     \
+                .u32OvfPolarity             = TMR6_PWM_LOW,     \
+            }                                                   \
+        },                                                      \
+    }
+#endif /* PWM_TMR6_8_CONFIG */
+#endif /* BSP_USING_PWM_TMR6_8 */
+
+#endif /* BSP_USING_PWM_TMR6 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __PWM_TMRA_CONFIG_H__ */

bsp/hc32/ev_hc32f472_lqfp100/board/config/qspi_config.h

@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2024-04-18     CDT          first version
+ */
+
+#ifndef __QSPI_CONFIG_H__
+#define __QSPI_CONFIG_H__
+
+#include <rtthread.h>
+#include "irq_config.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_QSPI
+#ifndef QSPI_BUS_CONFIG
+#define QSPI_BUS_CONFIG                                     \
+    {                                                       \
+        .Instance = CM_QSPI,                                \
+        .clock    = FCG1_PERIPH_QSPI,                       \
+        .timeout  = 5000UL,                                 \
+        .err_irq.irq_config =                               \
+        {                                                   \
+            .irq_num    = BSP_QSPI_ERR_IRQ_NUM,             \
+            .irq_prio   = BSP_QSPI_ERR_IRQ_PRIO,            \
+            .int_src    = INT_SRC_QSPI_INTR,                \
+        },                                                  \
+    }
+#endif /* QSPI_BUS_CONFIG */
+
+#ifndef QSPI_INIT_PARAMS
+#define QSPI_INIT_PARAMS                                        \
+    {                                                           \
+        .u32PrefetchMode   = QSPI_PREFETCH_MD_INVD,             \
+        .u32SetupTime      = QSPI_QSSN_SETUP_ADVANCE_QSCK0P5,   \
+        .u32ReleaseTime    = QSPI_QSSN_RELEASE_DELAY_QSCK32,    \
+        .u32IntervalTime   = QSPI_QSSN_INTERVAL_QSCK1,          \
+    }
+#endif /* QSPI_INIT_PARAMS */
+
+#define QSPI_WP_PIN_LEVEL               QSPI_WP_PIN_HIGH
+
+#ifdef BSP_QSPI_USING_DMA
+#ifndef QSPI_DMA_CONFIG
+#define QSPI_DMA_CONFIG                                     \
+    {                                                       \
+        .Instance       = QSPI_DMA_INSTANCE,                \
+        .channel        = QSPI_DMA_CHANNEL,                 \
+        .clock          = QSPI_DMA_CLOCK,                   \
+        .trigger_select = QSPI_DMA_TRIG_SELECT,             \
+        .trigger_event  = EVT_SRC_AOS_STRG,                 \
+        .flag           = QSPI_DMA_TRANS_FLAG,              \
+        .irq_config     =                                   \
+        {                                                   \
+            .irq_num    = QSPI_DMA_IRQn,                    \
+            .irq_prio   = QSPI_DMA_INT_PRIO,                \
+            .int_src    = QSPI_DMA_INT_SRC,                 \
+        }                                                   \
+    }
+#endif /* QSPI_DMA_CONFIG */
+#endif /* BSP_QSPI_USING_DMA */
+#endif /* BSP_USING_QSPI */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__QSPI_CONFIG_H__ */

bsp/hc32/ev_hc32f472_lqfp100/board/config/spi_config.h

@@ -0,0 +1,377 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2024-02-20     CDT          first version
+ */
+
+#ifndef __SPI_CONFIG_H__
+#define __SPI_CONFIG_H__
+
+#include <rtthread.h>
+#include "irq_config.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#ifdef BSP_USING_SPI1
+#ifndef SPI1_BUS_CONFIG
+#define SPI1_BUS_CONFIG                                     \
+    {                                                       \
+        .Instance = CM_SPI1,                                \
+        .bus_name = "spi1",                                 \
+        .clock    = FCG1_PERIPH_SPI1,                       \
+        .timeout  = 5000UL,                                 \
+        .err_irq.irq_config =                               \
+        {                                                   \
+            .irq_num    = BSP_SPI1_ERR_IRQ_NUM,             \
+            .irq_prio   = BSP_SPI1_ERR_IRQ_PRIO,            \
+            .int_src    = INT_SRC_SPI1_SPEI,                \
+        },                                                  \
+    }
+#endif /* SPI1_BUS_CONFIG */
+#endif /* BSP_USING_SPI1 */
+
+#ifdef BSP_SPI1_TX_USING_DMA
+#ifndef SPI1_TX_DMA_CONFIG
+#define SPI1_TX_DMA_CONFIG                                  \
+    {                                                       \
+        .Instance       = SPI1_TX_DMA_INSTANCE,             \
+        .channel        = SPI1_TX_DMA_CHANNEL,              \
+        .clock          = SPI1_TX_DMA_CLOCK,                \
+        .trigger_select = SPI1_TX_DMA_TRIG_SELECT,          \
+        .trigger_event  = EVT_SRC_SPI1_SPTI,                \
+        .flag           = SPI1_TX_DMA_TRANS_FLAG,           \
+        .irq_config     =                                   \
+        {                                                   \
+            .irq_num    = SPI1_TX_DMA_IRQn,                 \
+            .irq_prio   = SPI1_TX_DMA_INT_PRIO,             \
+            .int_src    = SPI1_TX_DMA_INT_SRC,              \
+        }                                                   \
+    }
+#endif /* SPI1_TX_DMA_CONFIG */
+#endif /* BSP_SPI1_TX_USING_DMA */
+
+#ifdef BSP_SPI1_RX_USING_DMA
+#ifndef SPI1_RX_DMA_CONFIG
+#define SPI1_RX_DMA_CONFIG                                  \
+    {                                                       \
+        .Instance       = SPI1_RX_DMA_INSTANCE,             \
+        .channel        = SPI1_RX_DMA_CHANNEL,              \
+        .clock          = SPI1_RX_DMA_CLOCK,                \
+        .trigger_select = SPI1_RX_DMA_TRIG_SELECT,          \
+        .trigger_event  = EVT_SRC_SPI1_SPRI,                \
+        .flag           = SPI1_RX_DMA_TRANS_FLAG,           \
+        .irq_config     =                                   \
+        {                                                   \
+            .irq_num    = SPI1_RX_DMA_IRQn,                 \
+            .irq_prio   = SPI1_RX_DMA_INT_PRIO,             \
+            .int_src    = SPI1_RX_DMA_INT_SRC,              \
+        }                                                   \
+    }
+#endif /* SPI1_RX_DMA_CONFIG */
+#endif /* BSP_SPI1_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI2
+#ifndef SPI2_BUS_CONFIG
+#define SPI2_BUS_CONFIG                                     \
+    {                                                       \
+        .Instance = CM_SPI2,                                \
+        .bus_name = "spi2",                                 \
+        .clock    = FCG1_PERIPH_SPI2,                       \
+        .timeout  = 5000UL,                                 \
+        .err_irq.irq_config =                               \
+        {                                                   \
+            .irq_num    = BSP_SPI2_ERR_IRQ_NUM,             \
+            .irq_prio   = BSP_SPI2_ERR_IRQ_PRIO,            \
+            .int_src    = INT_SRC_SPI2_SPEI,                \
+        },                                                  \
+    }
+#endif /* SPI2_BUS_CONFIG */
+#endif /* BSP_USING_SPI2 */
+
+#ifdef BSP_SPI2_TX_USING_DMA
+#ifndef SPI2_TX_DMA_CONFIG
+#define SPI2_TX_DMA_CONFIG                                  \
+    {                                                       \
+        .Instance       = SPI2_TX_DMA_INSTANCE,             \
+        .channel        = SPI2_TX_DMA_CHANNEL,              \
+        .clock          = SPI2_TX_DMA_CLOCK,                \
+        .trigger_select = SPI2_TX_DMA_TRIG_SELECT,          \
+        .trigger_event  = EVT_SRC_SPI2_SPTI,                \
+        .flag           = SPI2_TX_DMA_TRANS_FLAG,           \
+        .irq_config     =                                   \
+        {                                                   \
+            .irq_num    = SPI2_TX_DMA_IRQn,                 \
+            .irq_prio   = SPI2_TX_DMA_INT_PRIO,             \
+            .int_src    = SPI2_TX_DMA_INT_SRC,              \
+        }                                                   \
+    }
+#endif /* SPI2_TX_DMA_CONFIG */
+#endif /* BSP_SPI2_TX_USING_DMA */
+
+#ifdef BSP_SPI2_RX_USING_DMA
+#ifndef SPI2_RX_DMA_CONFIG
+#define SPI2_RX_DMA_CONFIG                                  \
+    {                                                       \
+        .Instance       = SPI2_RX_DMA_INSTANCE,             \
+        .channel        = SPI2_RX_DMA_CHANNEL,              \
+        .clock          = SPI2_RX_DMA_CLOCK,                \
+        .trigger_select = SPI2_RX_DMA_TRIG_SELECT,          \
+        .trigger_event  = EVT_SRC_SPI2_SPRI,                \
+        .flag           = SPI2_RX_DMA_TRANS_FLAG,           \
+        .irq_config     =                                   \
+        {                                                   \
+            .irq_num    = SPI2_RX_DMA_IRQn,                 \
+            .irq_prio   = SPI2_RX_DMA_INT_PRIO,             \
+            .int_src    = SPI2_RX_DMA_INT_SRC,              \
+        }                                                   \
+    }
+#endif /* SPI2_RX_DMA_CONFIG */
+#endif /* BSP_SPI2_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI3
+#ifndef SPI3_BUS_CONFIG
+#define SPI3_BUS_CONFIG                                     \
+    {                                                       \
+        .Instance = CM_SPI3,                                \
+        .bus_name = "spi3",                                 \
+        .clock    = FCG1_PERIPH_SPI3,                       \
+        .timeout  = 5000UL,                                 \
+        .err_irq.irq_config =                               \
+        {                                                   \
+            .irq_num    = BSP_SPI3_ERR_IRQ_NUM,             \
+            .irq_prio   = BSP_SPI3_ERR_IRQ_PRIO,            \
+            .int_src    = INT_SRC_SPI3_SPEI,                \
+        },                                                  \
+    }
+#endif /* SPI3_BUS_CONFIG */
+#endif /* BSP_USING_SPI3 */
+
+
+#ifdef BSP_SPI3_TX_USING_DMA
+#ifndef SPI3_TX_DMA_CONFIG
+#define SPI3_TX_DMA_CONFIG                                  \
+    {                                                       \
+        .Instance       = SPI3_TX_DMA_INSTANCE,             \
+        .channel        = SPI3_TX_DMA_CHANNEL,              \
+        .clock          = SPI3_TX_DMA_CLOCK,                \
+        .trigger_select = SPI3_TX_DMA_TRIG_SELECT,          \
+        .trigger_event  = EVT_SRC_SPI3_SPTI,                \
+        .flag           = SPI3_TX_DMA_TRANS_FLAG,           \
+        .irq_config     =                                   \
+        {                                                   \
+            .irq_num    = SPI3_TX_DMA_IRQn,                 \
+            .irq_prio   = SPI3_TX_DMA_INT_PRIO,             \
+            .int_src    = SPI3_TX_DMA_INT_SRC,              \
+        }                                                   \
+    }
+#endif /* SPI3_TX_DMA_CONFIG */
+#endif /* BSP_SPI3_TX_USING_DMA */
+
+#ifdef BSP_SPI3_RX_USING_DMA
+#ifndef SPI3_RX_DMA_CONFIG
+#define SPI3_RX_DMA_CONFIG                                  \
+    {                                                       \
+        .Instance       = SPI3_RX_DMA_INSTANCE,             \
+        .channel        = SPI3_RX_DMA_CHANNEL,              \
+        .clock          = SPI3_RX_DMA_CLOCK,                \
+        .trigger_select = SPI3_RX_DMA_TRIG_SELECT,          \
+        .trigger_event  = EVT_SRC_SPI3_SPRI,                \
+        .flag           = SPI3_RX_DMA_TRANS_FLAG,           \
+        .irq_config     =                                   \
+        {                                                   \
+            .irq_num    = SPI3_RX_DMA_IRQn,                 \
+            .irq_prio   = SPI3_RX_DMA_INT_PRIO,             \
+            .int_src    = SPI3_RX_DMA_INT_SRC,              \
+        }                                                   \
+    }
+#endif /* SPI3_RX_DMA_CONFIG */
+#endif /* BSP_SPI3_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI4
+#ifndef SPI4_BUS_CONFIG
+#define SPI4_BUS_CONFIG                                     \
+    {                                                       \
+        .Instance = CM_SPI4,                                \
+        .bus_name = "spi4",                                 \
+        .clock    = FCG1_PERIPH_SPI4,                       \
+        .timeout  = 5000UL,                                 \
+        .err_irq.irq_config =                               \
+        {                                                   \
+            .irq_num    = BSP_SPI4_ERR_IRQ_NUM,             \
+            .irq_prio   = BSP_SPI4_ERR_IRQ_PRIO,            \
+            .int_src    = INT_SRC_SPI4_SPEI,                \
+        },                                                  \
+    }
+#endif /* SPI4_BUS_CONFIG */
+#endif /* BSP_USING_SPI4 */
+
+#ifdef BSP_SPI4_TX_USING_DMA
+#ifndef SPI4_TX_DMA_CONFIG
+#define SPI4_TX_DMA_CONFIG                                  \
+    {                                                       \
+        .Instance       = SPI4_TX_DMA_INSTANCE,             \
+        .channel        = SPI4_TX_DMA_CHANNEL,              \
+        .clock          = SPI4_TX_DMA_CLOCK,                \
+        .trigger_select = SPI4_TX_DMA_TRIG_SELECT,          \
+        .trigger_event  = EVT_SRC_SPI4_SPTI,                \
+        .flag           = SPI4_TX_DMA_TRANS_FLAG,           \
+        .irq_config     =                                   \
+        {                                                   \
+            .irq_num    = SPI4_TX_DMA_IRQn,                 \
+            .irq_prio   = SPI4_TX_DMA_INT_PRIO,             \
+            .int_src    = SPI4_TX_DMA_INT_SRC,              \
+        }                                                   \
+    }
+#endif /* SPI4_TX_DMA_CONFIG */
+#endif /* BSP_SPI4_TX_USING_DMA */
+
+#ifdef BSP_SPI4_RX_USING_DMA
+#ifndef SPI4_RX_DMA_CONFIG
+#define SPI4_RX_DMA_CONFIG                                  \
+    {                                                       \
+        .Instance       = SPI4_RX_DMA_INSTANCE,             \
+        .channel        = SPI4_RX_DMA_CHANNEL,              \
+        .clock          = SPI4_RX_DMA_CLOCK,                \
+        .trigger_select = SPI4_RX_DMA_TRIG_SELECT,          \
+        .trigger_event  = EVT_SRC_SPI4_SPRI,                \
+        .flag           = SPI4_RX_DMA_TRANS_FLAG,           \
+        .irq_config     =                                   \
+        {                                                   \
+            .irq_num    = SPI4_RX_DMA_IRQn,                 \
+            .irq_prio   = SPI4_RX_DMA_INT_PRIO,             \
+            .int_src    = SPI4_RX_DMA_INT_SRC,              \
+        }                                                   \
+    }
+#endif /* SPI4_RX_DMA_CONFIG */
+#endif /* BSP_SPI4_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI5
+#ifndef SPI5_BUS_CONFIG
+#define SPI5_BUS_CONFIG                                     \
+    {                                                       \
+        .Instance = CM_SPI5,                                \
+        .bus_name = "spi5",                                 \
+        .clock    = FCG1_PERIPH_SPI5,                       \
+        .timeout  = 5000UL,                                 \
+        .err_irq.irq_config =                               \
+        {                                                   \
+            .irq_num    = BSP_SPI5_ERR_IRQ_NUM,             \
+            .irq_prio   = BSP_SPI5_ERR_IRQ_PRIO,            \
+            .int_src    = INT_SRC_SPI5_SPEI,                \
+        },                                                  \
+    }
+#endif /* SPI5_BUS_CONFIG */
+#endif /* BSP_USING_SPI5 */
+
+#ifdef BSP_SPI5_TX_USING_DMA
+#ifndef SPI5_TX_DMA_CONFIG
+#define SPI5_TX_DMA_CONFIG                                  \
+    {                                                       \
+        .Instance       = SPI5_TX_DMA_INSTANCE,             \
+        .channel        = SPI5_TX_DMA_CHANNEL,              \
+        .clock          = SPI5_TX_DMA_CLOCK,                \
+        .trigger_select = SPI5_TX_DMA_TRIG_SELECT,          \
+        .trigger_event  = EVT_SRC_SPI5_SPTI,                \
+        .flag           = SPI5_TX_DMA_TRANS_FLAG,           \
+        .irq_config     =                                   \
+        {                                                   \
+            .irq_num    = SPI5_TX_DMA_IRQn,                 \
+            .irq_prio   = SPI5_TX_DMA_INT_PRIO,             \
+            .int_src    = SPI5_TX_DMA_INT_SRC,              \
+        }                                                   \
+    }
+#endif /* SPI5_TX_DMA_CONFIG */
+#endif /* BSP_SPI5_TX_USING_DMA */
+
+#ifdef BSP_SPI5_RX_USING_DMA
+#ifndef SPI5_RX_DMA_CONFIG
+#define SPI5_RX_DMA_CONFIG                                  \
+    {                                                       \
+        .Instance       = SPI5_RX_DMA_INSTANCE,             \
+        .channel        = SPI5_RX_DMA_CHANNEL,              \
+        .clock          = SPI5_RX_DMA_CLOCK,                \
+        .trigger_select = SPI5_RX_DMA_TRIG_SELECT,          \
+        .trigger_event  = EVT_SRC_SPI5_SPRI,                \
+        .flag           = SPI5_RX_DMA_TRANS_FLAG,           \
+        .irq_config     =                                   \
+        {                                                   \
+            .irq_num    = SPI5_RX_DMA_IRQn,                 \
+            .irq_prio   = SPI5_RX_DMA_INT_PRIO,             \
+            .int_src    = SPI5_RX_DMA_INT_SRC,              \
+        }                                                   \
+    }
+#endif /* SPI5_RX_DMA_CONFIG */
+#endif /* BSP_SPI5_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI6
+#ifndef SPI6_BUS_CONFIG
+#define SPI6_BUS_CONFIG                                     \
+    {                                                       \
+        .Instance = CM_SPI6,                                \
+        .bus_name = "spi6",                                 \
+        .clock    = FCG1_PERIPH_SPI6,                       \
+        .timeout  = 5000UL,                                 \
+        .err_irq.irq_config =                               \
+        {                                                   \
+            .irq_num    = BSP_SPI6_ERR_IRQ_NUM,             \
+            .irq_prio   = BSP_SPI6_ERR_IRQ_PRIO,            \
+            .int_src    = INT_SRC_SPI6_SPEI,                \
+        },                                                  \
+    }
+#endif /* SPI6_BUS_CONFIG */
+#endif /* BSP_USING_SPI6 */
+
+#ifdef BSP_SPI6_TX_USING_DMA
+#ifndef SPI6_TX_DMA_CONFIG
+#define SPI6_TX_DMA_CONFIG                                  \
+    {                                                       \
+        .Instance       = SPI6_TX_DMA_INSTANCE,             \
+        .channel        = SPI6_TX_DMA_CHANNEL,              \
+        .clock          = SPI6_TX_DMA_CLOCK,                \
+        .trigger_select = SPI6_TX_DMA_TRIG_SELECT,          \
+        .trigger_event  = EVT_SRC_SPI6_SPTI,                \
+        .flag           = SPI6_TX_DMA_TRANS_FLAG,           \
+        .irq_config     =                                   \
+        {                                                   \
+            .irq_num    = SPI6_TX_DMA_IRQn,                 \
+            .irq_prio   = SPI6_TX_DMA_INT_PRIO,             \
+            .int_src    = SPI6_TX_DMA_INT_SRC,              \
+        }                                                   \
+    }
+#endif /* SPI6_TX_DMA_CONFIG */
+#endif /* BSP_SPI6_TX_USING_DMA */
+
+#ifdef BSP_SPI6_RX_USING_DMA
+#ifndef SPI6_RX_DMA_CONFIG
+#define SPI6_RX_DMA_CONFIG                                  \
+    {                                                       \
+        .Instance       = SPI6_RX_DMA_INSTANCE,             \
+        .channel        = SPI6_RX_DMA_CHANNEL,              \
+        .clock          = SPI6_RX_DMA_CLOCK,                \
+        .trigger_select = SPI6_RX_DMA_TRIG_SELECT,          \
+        .trigger_event  = EVT_SRC_SPI6_SPRI,                \
+        .flag           = SPI6_RX_DMA_TRANS_FLAG,           \
+        .irq_config     =                                   \
+        {                                                   \
+            .irq_num    = SPI6_RX_DMA_IRQn,                 \
+            .irq_prio   = SPI6_RX_DMA_INT_PRIO,             \
+            .int_src    = SPI6_RX_DMA_INT_SRC,              \
+        }                                                   \
+    }
+#endif /* SPI6_RX_DMA_CONFIG */
+#endif /* BSP_SPI6_RX_USING_DMA */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SPI_CONFIG_H__ */

bsp/hc32/ev_hc32f472_lqfp100/board/config/timer_config.h

@@ -0,0 +1,115 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2024-02-20     CDT          first version
+ */
+
+#ifndef __TMR_CONFIG_H__
+#define __TMR_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_TMRA_1
+#ifndef TMRA_1_CONFIG
+#define TMRA_1_CONFIG                                       \
+    {                                                       \
+       .tmr_handle      = CM_TMRA_1,                        \
+       .clock_source    = CLK_BUS_PCLK0,                    \
+       .clock           = FCG2_PERIPH_TMRA_1,               \
+       .flag            = TMRA_FLAG_OVF,                    \
+       .isr             =                                   \
+       {                                                    \
+            .enIntSrc   = INT_SRC_TMRA_1_OVF,               \
+            .enIRQn     = BSP_USING_TMRA_1_IRQ_NUM,         \
+            .u8Int_Prio = BSP_USING_TMRA_1_IRQ_PRIO,        \
+       },                                                   \
+       .name            = "tmra_1"                          \
+    }
+#endif /* TMRA_1_CONFIG */
+#endif /* BSP_USING_TMRA_1 */
+
+#ifdef BSP_USING_TMRA_2
+#ifndef TMRA_2_CONFIG
+#define TMRA_2_CONFIG                                       \
+    {                                                       \
+       .tmr_handle      = CM_TMRA_2,                        \
+       .clock_source    = CLK_BUS_PCLK0,                    \
+       .clock           = FCG2_PERIPH_TMRA_2,               \
+       .flag            = TMRA_FLAG_OVF,                    \
+       .isr             =                                   \
+       {                                                    \
+            .enIntSrc   = INT_SRC_TMRA_2_OVF,               \
+            .enIRQn     = BSP_USING_TMRA_2_IRQ_NUM,         \
+            .u8Int_Prio = BSP_USING_TMRA_2_IRQ_PRIO,        \
+       },                                                   \
+       .name            = "tmra_2"                          \
+    }
+#endif /* TMRA_2_CONFIG */
+#endif /* BSP_USING_TMRA_2 */
+
+#ifdef BSP_USING_TMRA_3
+#ifndef TMRA_3_CONFIG
+#define TMRA_3_CONFIG                                       \
+    {                                                       \
+       .tmr_handle      = CM_TMRA_3,                        \
+       .clock_source    = CLK_BUS_PCLK0,                    \
+       .clock           = FCG2_PERIPH_TMRA_3,               \
+       .flag            = TMRA_FLAG_OVF,                    \
+       .isr             =                                   \
+       {                                                    \
+            .enIntSrc   = INT_SRC_TMRA_3_OVF,               \
+            .enIRQn     = BSP_USING_TMRA_3_IRQ_NUM,         \
+            .u8Int_Prio = BSP_USING_TMRA_3_IRQ_PRIO,        \
+       },                                                   \
+       .name            = "tmra_3"                          \
+    }
+#endif /* TMRA_3_CONFIG */
+#endif /* BSP_USING_TMRA_3 */
+
+#ifdef BSP_USING_TMRA_4
+#ifndef TMRA_4_CONFIG
+#define TMRA_4_CONFIG                                       \
+    {                                                       \
+       .tmr_handle      = CM_TMRA_4,                        \
+       .clock_source    = CLK_BUS_PCLK0,                    \
+       .clock           = FCG2_PERIPH_TMRA_4,               \
+       .flag            = TMRA_FLAG_OVF,                    \
+       .isr             =                                   \
+       {                                                    \
+            .enIntSrc   = INT_SRC_TMRA_4_OVF,               \
+            .enIRQn     = BSP_USING_TMRA_4_IRQ_NUM,         \
+            .u8Int_Prio = BSP_USING_TMRA_4_IRQ_PRIO,        \
+       },                                                   \
+       .name            = "tmra_4"                          \
+    }
+#endif /* TMRA_4_CONFIG */
+#endif /* BSP_USING_TMRA_4 */
+
+#ifdef BSP_USING_TMRA_5
+#ifndef TMRA_5_CONFIG
+#define TMRA_5_CONFIG                                       \
+    {                                                       \
+       .tmr_handle      = CM_TMRA_5,                        \
+       .clock_source    = CLK_BUS_PCLK1,                    \
+       .clock           = FCG2_PERIPH_TMRA_5,               \
+       .flag            = TMRA_FLAG_OVF,                    \
+       .isr             =                                   \
+       {                                                    \
+            .enIntSrc   = INT_SRC_TMRA_5_OVF,               \
+            .enIRQn     = BSP_USING_TMRA_5_IRQ_NUM,         \
+            .u8Int_Prio = BSP_USING_TMRA_5_IRQ_PRIO,        \
+       },                                                   \
+       .name            = "tmra_5"                          \
+    }
+#endif /* TMRA_5_CONFIG */
+#endif /* BSP_USING_TMRA_5 */
+#endif /* __TMR_CONFIG_H__ */

bsp/hc32/ev_hc32f472_lqfp100/board/config/uart_config.h

@@ -0,0 +1,449 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2024-02-20     CDT          first version
+ */
+
+#ifndef __UART_CONFIG_H__
+#define __UART_CONFIG_H__
+
+#include <rtthread.h>
+#include "irq_config.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#if defined(BSP_USING_UART1)
+#ifndef UART1_CONFIG
+#define UART1_CONFIG                                            \
+    {                                                           \
+        .name     = "uart1",                                    \
+        .Instance = CM_USART1,                                  \
+        .clock    = FCG3_PERIPH_USART1,                         \
+        .irq_num  = BSP_UART1_IRQ_NUM,                          \
+        .rxerr_int_src = INT_SRC_USART1_EI,                     \
+        .rx_int_src    = INT_SRC_USART1_RI,                     \
+        .tx_int_src    = INT_SRC_USART1_TI,                     \
+    }
+#endif /* UART1_CONFIG */
+
+#if defined(BSP_UART1_RX_USING_DMA)
+#ifndef UART1_DMA_RX_CONFIG
+#define UART1_DMA_RX_CONFIG                                     \
+    {                                                           \
+        .Instance       = UART1_RX_DMA_INSTANCE,                \
+        .channel        = UART1_RX_DMA_CHANNEL,                 \
+        .clock          = UART1_RX_DMA_CLOCK,                   \
+        .trigger_select = UART1_RX_DMA_TRIG_SELECT,             \
+        .trigger_event  = EVT_SRC_USART1_RI,                    \
+        .flag           = UART1_RX_DMA_TRANS_FLAG,              \
+        .irq_config     =                                       \
+        {                                                       \
+            .irq_num    = UART1_RX_DMA_IRQn,                    \
+            .irq_prio   = UART1_RX_DMA_INT_PRIO,                \
+            .int_src    = UART1_RX_DMA_INT_SRC,                 \
+        },                                                      \
+    }
+#endif /* UART1_DMA_RX_CONFIG */
+
+#ifndef UART1_RXTO_CONFIG
+#define UART1_RXTO_CONFIG                                       \
+    {                                                           \
+        .TMR0_Instance = CM_TMR0_1,                             \
+        .channel       = TMR0_CH_A,                             \
+        .clock         = FCG2_PERIPH_TMR0_1,                    \
+        .timeout_bits  = 20UL,                                  \
+    }
+#endif /* UART1_RXTO_CONFIG */
+#endif /* BSP_UART1_RX_USING_DMA */
+
+#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART1_TX_USING_DMA)
+#ifndef UART1_TX_CPLT_CONFIG
+#define UART1_TX_CPLT_CONFIG                                    \
+    {                                                           \
+        .irq_config     =                                       \
+        {                                                       \
+            .irq_num    = BSP_UART1_TX_CPLT_IRQ_NUM,            \
+            .irq_prio   = BSP_UART1_TX_CPLT_IRQ_PRIO,           \
+            .int_src    = INT_SRC_USART1_TCI,                   \
+        },                                                      \
+    }
+#endif
+#elif defined(RT_USING_SERIAL_V2)
+#ifndef UART1_TX_CPLT_CONFIG
+#define UART1_TX_CPLT_CONFIG                                    \
+    {                                                           \
+        .irq_config     =                                       \
+        {                                                       \
+            .irq_num    = BSP_UART1_TX_CPLT_IRQ_NUM,            \
+            .irq_prio   = BSP_UART1_TX_CPLT_IRQ_PRIO,           \
+            .int_src    = INT_SRC_USART1_TCI,                   \
+        },                                                      \
+    }
+#endif
+#endif /* UART1_TX_CPLT_CONFIG */
+
+#if defined(BSP_UART1_TX_USING_DMA)
+#ifndef UART1_DMA_TX_CONFIG
+#define UART1_DMA_TX_CONFIG                                     \
+    {                                                           \
+        .Instance       = UART1_TX_DMA_INSTANCE,                \
+        .channel        = UART1_TX_DMA_CHANNEL,                 \
+        .clock          = UART1_TX_DMA_CLOCK,                   \
+        .trigger_select = UART1_TX_DMA_TRIG_SELECT,             \
+        .trigger_event  = EVT_SRC_USART1_TI,                    \
+        .flag           = UART1_TX_DMA_TRANS_FLAG,              \
+        .irq_config     =                                       \
+        {                                                       \
+            .irq_num    = UART1_TX_DMA_IRQn,                    \
+            .irq_prio   = UART1_TX_DMA_INT_PRIO,                \
+            .int_src    = UART1_TX_DMA_INT_SRC,                 \
+        },                                                      \
+    }
+#endif /* UART1_DMA_TX_CONFIG */
+#endif /* BSP_UART1_TX_USING_DMA */
+#endif /* BSP_USING_UART1 */
+
+#if defined(BSP_USING_UART2)
+#ifndef UART2_CONFIG
+#define UART2_CONFIG                                            \
+    {                                                           \
+        .name     = "uart2",                                    \
+        .Instance = CM_USART2,                                  \
+        .clock    = FCG3_PERIPH_USART2,                         \
+        .irq_num  = BSP_UART2_IRQ_NUM,                          \
+        .rxerr_int_src = INT_SRC_USART2_EI,                     \
+        .rx_int_src    = INT_SRC_USART2_RI,                     \
+        .tx_int_src    = INT_SRC_USART2_TI,                     \
+    }
+#endif /* UART2_CONFIG */
+
+#if defined(BSP_UART2_RX_USING_DMA)
+#ifndef UART2_DMA_RX_CONFIG
+#define UART2_DMA_RX_CONFIG                                     \
+    {                                                           \
+        .Instance       = UART2_RX_DMA_INSTANCE,                \
+        .channel        = UART2_RX_DMA_CHANNEL,                 \
+        .clock          = UART2_RX_DMA_CLOCK,                   \
+        .trigger_select = UART2_RX_DMA_TRIG_SELECT,             \
+        .trigger_event  = EVT_SRC_USART2_RI,                    \
+        .flag           = UART2_RX_DMA_TRANS_FLAG,              \
+        .irq_config     =                                       \
+        {                                                       \
+            .irq_num    = UART2_RX_DMA_IRQn,                    \
+            .irq_prio   = UART2_RX_DMA_INT_PRIO,                \
+            .int_src    = UART2_RX_DMA_INT_SRC,                 \
+        },                                                      \
+    }
+#endif /* UART2_DMA_RX_CONFIG */
+
+#ifndef UART2_RXTO_CONFIG
+#define UART2_RXTO_CONFIG                                       \
+    {                                                           \
+        .TMR0_Instance = CM_TMR0_1,                             \
+        .channel       = TMR0_CH_B,                             \
+        .clock         = FCG2_PERIPH_TMR0_1,                    \
+        .timeout_bits  = 20UL,                                  \
+    }
+#endif /* UART2_RXTO_CONFIG */
+#endif /* BSP_UART2_RX_USING_DMA */
+
+#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART2_TX_USING_DMA)
+#ifndef UART2_TX_CPLT_CONFIG
+#define UART2_TX_CPLT_CONFIG                                    \
+    {                                                           \
+        .irq_config     =                                       \
+        {                                                       \
+            .irq_num    = BSP_UART2_TX_CPLT_IRQ_NUM,            \
+            .irq_prio   = BSP_UART2_TX_CPLT_IRQ_PRIO,           \
+            .int_src    = INT_SRC_USART2_TCI,                   \
+        },                                                      \
+    }
+#endif
+#elif defined(RT_USING_SERIAL_V2)
+#ifndef UART2_TX_CPLT_CONFIG
+#define UART2_TX_CPLT_CONFIG                                    \
+    {                                                           \
+        .irq_config     =                                       \
+        {                                                       \
+            .irq_num    = BSP_UART2_TX_CPLT_IRQ_NUM,            \
+            .irq_prio   = BSP_UART2_TX_CPLT_IRQ_PRIO,           \
+            .int_src    = INT_SRC_USART2_TCI,                   \
+        },                                                      \
+    }
+#endif
+#endif /* UART2_TX_CPLT_CONFIG */
+
+#if defined(BSP_UART2_TX_USING_DMA)
+#ifndef UART2_DMA_TX_CONFIG
+#define UART2_DMA_TX_CONFIG                                     \
+    {                                                           \
+        .Instance       = UART2_TX_DMA_INSTANCE,                \
+        .channel        = UART2_TX_DMA_CHANNEL,                 \
+        .clock          = UART2_TX_DMA_CLOCK,                   \
+        .trigger_select = UART2_TX_DMA_TRIG_SELECT,             \
+        .trigger_event  = EVT_SRC_USART2_TI,                    \
+        .flag           = UART2_TX_DMA_TRANS_FLAG,              \
+        .irq_config     =                                       \
+        {                                                       \
+            .irq_num    = UART2_TX_DMA_IRQn,                    \
+            .irq_prio   = UART2_TX_DMA_INT_PRIO,                \
+            .int_src    = UART2_TX_DMA_INT_SRC,                 \
+        },                                                      \
+    }
+#endif /* UART2_DMA_TX_CONFIG */
+#endif /* BSP_UART2_TX_USING_DMA */
+#endif /* BSP_USING_UART2 */
+
+#if defined(BSP_USING_UART3)
+#ifndef UART3_CONFIG
+#define UART3_CONFIG                                            \
+    {                                                           \
+        .name     = "uart3",                                    \
+        .Instance = CM_USART3,                                  \
+        .clock    = FCG3_PERIPH_USART3,                         \
+        .irq_num  = BSP_UART3_IRQ_NUM,                          \
+        .rxerr_int_src = INT_SRC_USART3_EI,                     \
+        .rx_int_src    = INT_SRC_USART3_RI,                     \
+        .tx_int_src    = INT_SRC_USART3_TI,                     \
+    }
+#endif /* UART3_CONFIG */
+
+#if defined(RT_USING_SERIAL_V2)
+#ifndef UART3_TX_CPLT_CONFIG
+#define UART3_TX_CPLT_CONFIG                                    \
+    {                                                           \
+        .irq_config     =                                       \
+        {                                                       \
+            .irq_num    = BSP_UART3_TX_CPLT_IRQ_NUM,            \
+            .irq_prio   = BSP_UART3_TX_CPLT_IRQ_PRIO,           \
+            .int_src    = INT_SRC_USART3_TCI,                   \
+        },                                                      \
+    }
+#endif
+#endif /* UART3_TX_CPLT_CONFIG */
+#endif /* BSP_USING_UART3 */
+
+#if defined(BSP_USING_UART4)
+#ifndef UART4_CONFIG
+#define UART4_CONFIG                                            \
+    {                                                           \
+        .name     = "uart4",                                    \
+        .Instance = CM_USART4,                                  \
+        .clock    = FCG3_PERIPH_USART4,                         \
+        .irq_num  = BSP_UART4_IRQ_NUM,                          \
+        .rxerr_int_src = INT_SRC_USART4_EI,                     \
+        .rx_int_src    = INT_SRC_USART4_RI,                     \
+        .tx_int_src    = INT_SRC_USART4_TI,                     \
+    }
+#endif /* UART4_CONFIG */
+
+#if defined(BSP_UART4_RX_USING_DMA)
+#ifndef UART4_DMA_RX_CONFIG
+#define UART4_DMA_RX_CONFIG                                     \
+    {                                                           \
+        .Instance       = UART4_RX_DMA_INSTANCE,                \
+        .channel        = UART4_RX_DMA_CHANNEL,                 \
+        .clock          = UART4_RX_DMA_CLOCK,                   \
+        .trigger_select = UART4_RX_DMA_TRIG_SELECT,             \
+        .trigger_event  = EVT_SRC_USART4_RI,                    \
+        .flag           = UART4_RX_DMA_TRANS_FLAG,              \
+        .irq_config     =                                       \
+        {                                                       \
+            .irq_num    = UART4_RX_DMA_IRQn,                    \
+            .irq_prio   = UART4_RX_DMA_INT_PRIO,                \
+            .int_src    = UART4_RX_DMA_INT_SRC,                 \
+        },                                                      \
+    }
+#endif /* UART4_DMA_RX_CONFIG */
+
+#ifndef UART4_RXTO_CONFIG
+#define UART4_RXTO_CONFIG                                       \
+    {                                                           \
+        .TMR0_Instance = CM_TMR0_2,                             \
+        .channel       = TMR0_CH_A,                             \
+        .clock         = FCG2_PERIPH_TMR0_2,                    \
+        .timeout_bits  = 20UL,                                  \
+    }
+#endif /* UART4_RXTO_CONFIG */
+#endif /* BSP_UART4_RX_USING_DMA */
+
+#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART4_TX_USING_DMA)
+#ifndef UART4_TX_CPLT_CONFIG
+#define UART4_TX_CPLT_CONFIG                                    \
+    {                                                           \
+        .irq_config     =                                       \
+        {                                                       \
+            .irq_num    = BSP_UART4_TX_CPLT_IRQ_NUM,            \
+            .irq_prio   = BSP_UART4_TX_CPLT_IRQ_PRIO,           \
+            .int_src    = INT_SRC_USART4_TCI,                   \
+        },                                                      \
+    }
+#endif
+#elif defined(RT_USING_SERIAL_V2)
+#ifndef UART4_TX_CPLT_CONFIG
+#define UART4_TX_CPLT_CONFIG                                    \
+    {                                                           \
+        .irq_config     =                                       \
+        {                                                       \
+            .irq_num    = BSP_UART4_TX_CPLT_IRQ_NUM,            \
+            .irq_prio   = BSP_UART4_TX_CPLT_IRQ_PRIO,           \
+            .int_src    = INT_SRC_USART4_TCI,                   \
+        },                                                      \
+    }
+#endif
+#endif /* UART4_TX_CPLT_CONFIG */
+
+#if defined(BSP_UART4_TX_USING_DMA)
+#ifndef UART4_DMA_TX_CONFIG
+#define UART4_DMA_TX_CONFIG                                     \
+    {                                                           \
+        .Instance       = UART4_TX_DMA_INSTANCE,                \
+        .channel        = UART4_TX_DMA_CHANNEL,                 \
+        .clock          = UART4_TX_DMA_CLOCK,                   \
+        .trigger_select = UART4_TX_DMA_TRIG_SELECT,             \
+        .trigger_event  = EVT_SRC_USART4_TI,                    \
+        .flag           = UART4_TX_DMA_TRANS_FLAG,              \
+        .irq_config     =                                       \
+        {                                                       \
+            .irq_num    = UART4_TX_DMA_IRQn,                    \
+            .irq_prio   = UART4_TX_DMA_INT_PRIO,                \
+            .int_src    = UART4_TX_DMA_INT_SRC,                 \
+        },                                                      \
+    }
+#endif /* UART4_DMA_TX_CONFIG */
+#endif /* BSP_UART4_TX_USING_DMA */
+#endif /* BSP_USING_UART4 */
+
+#if defined(BSP_USING_UART5)
+#ifndef UART5_CONFIG
+#define UART5_CONFIG                                            \
+    {                                                           \
+        .name     = "uart5",                                    \
+        .Instance = CM_USART5,                                  \
+        .clock    = FCG3_PERIPH_USART5,                         \
+        .irq_num  = BSP_UART5_IRQ_NUM,                          \
+        .rxerr_int_src = INT_SRC_USART5_EI,                     \
+        .rx_int_src    = INT_SRC_USART5_RI,                     \
+        .tx_int_src    = INT_SRC_USART5_TI,                     \
+    }
+#endif /* UART5_CONFIG */
+
+#if defined(BSP_UART5_RX_USING_DMA)
+#ifndef UART5_DMA_RX_CONFIG
+#define UART5_DMA_RX_CONFIG                                     \
+    {                                                           \
+        .Instance       = UART5_RX_DMA_INSTANCE,                \
+        .channel        = UART5_RX_DMA_CHANNEL,                 \
+        .clock          = UART5_RX_DMA_CLOCK,                   \
+        .trigger_select = UART5_RX_DMA_TRIG_SELECT,             \
+        .trigger_event  = EVT_SRC_USART5_RI,                    \
+        .flag           = UART5_RX_DMA_TRANS_FLAG,              \
+        .irq_config     =                                       \
+        {                                                       \
+            .irq_num    = UART5_RX_DMA_IRQn,                    \
+            .irq_prio   = UART5_RX_DMA_INT_PRIO,                \
+            .int_src    = UART5_RX_DMA_INT_SRC,                 \
+        },                                                      \
+    }
+#endif /* UART5_DMA_RX_CONFIG */
+
+#ifndef UART5_RXTO_CONFIG
+#define UART5_RXTO_CONFIG                                       \
+    {                                                           \
+        .TMR0_Instance = CM_TMR0_2,                             \
+        .channel       = TMR0_CH_B,                             \
+        .clock         = FCG2_PERIPH_TMR0_2,                    \
+        .timeout_bits  = 20UL,                                  \
+    }
+#endif /* UART5_RXTO_CONFIG */
+#endif /* BSP_UART5_RX_USING_DMA */
+
+#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART5_TX_USING_DMA)
+#ifndef UART5_TX_CPLT_CONFIG
+#define UART5_TX_CPLT_CONFIG                                    \
+    {                                                           \
+        .irq_config     =                                       \
+        {                                                       \
+            .irq_num    = BSP_UART5_TX_CPLT_IRQ_NUM,            \
+            .irq_prio   = BSP_UART5_TX_CPLT_IRQ_PRIO,           \
+            .int_src    = INT_SRC_USART5_TCI,                   \
+        },                                                      \
+    }
+#endif
+#elif defined(RT_USING_SERIAL_V2)
+#ifndef UART5_TX_CPLT_CONFIG
+#define UART5_TX_CPLT_CONFIG                                    \
+    {                                                           \
+        .irq_config     =                                       \
+        {                                                       \
+            .irq_num    = BSP_UART5_TX_CPLT_IRQ_NUM,            \
+            .irq_prio   = BSP_UART5_TX_CPLT_IRQ_PRIO,           \
+            .int_src    = INT_SRC_USART5_TCI,                   \
+        },                                                      \
+    }
+#endif
+#endif /* UART5_TX_CPLT_CONFIG */
+
+#if defined(BSP_UART5_TX_USING_DMA)
+#ifndef UART5_DMA_TX_CONFIG
+#define UART5_DMA_TX_CONFIG                                     \
+    {                                                           \
+        .Instance       = UART5_TX_DMA_INSTANCE,                \
+        .channel        = UART5_TX_DMA_CHANNEL,                 \
+        .clock          = UART5_TX_DMA_CLOCK,                   \
+        .trigger_select = UART5_TX_DMA_TRIG_SELECT,             \
+        .trigger_event  = EVT_SRC_USART5_TI,                    \
+        .flag           = UART5_TX_DMA_TRANS_FLAG,              \
+        .irq_config     =                                       \
+        {                                                       \
+            .irq_num    = UART5_TX_DMA_IRQn,                    \
+            .irq_prio   = UART5_TX_DMA_INT_PRIO,                \
+            .int_src    = UART5_TX_DMA_INT_SRC,                 \
+        },                                                      \
+    }
+#endif /* UART5_DMA_TX_CONFIG */
+#endif /* BSP_UART5_TX_USING_DMA */
+#endif /* BSP_USING_UART5 */
+
+#if defined(BSP_USING_UART6)
+#ifndef UART6_CONFIG
+#define UART6_CONFIG                                            \
+    {                                                           \
+        .name     = "uart6",                                    \
+        .Instance = CM_USART6,                                  \
+        .clock    = FCG3_PERIPH_USART6,                         \
+        .irq_num  = BSP_UART6_IRQ_NUM,                          \
+        .rxerr_int_src = INT_SRC_USART6_EI,                     \
+        .rx_int_src    = INT_SRC_USART6_RI,                     \
+        .tx_int_src    = INT_SRC_USART6_TI,                     \
+    }
+#endif /* UART6_CONFIG */
+
+#if defined(RT_USING_SERIAL_V2)
+#ifndef UART6_TX_CPLT_CONFIG
+#define UART6_TX_CPLT_CONFIG                                    \
+    {                                                           \
+        .irq_config     =                                       \
+        {                                                       \
+            .irq_num    = BSP_UART6_TX_CPLT_IRQ_NUM,            \
+            .irq_prio   = BSP_UART6_TX_CPLT_IRQ_PRIO,           \
+            .int_src    = INT_SRC_USART6_TCI,                   \
+        },                                                      \
+    }
+#endif
+#endif /* UART6_TX_CPLT_CONFIG */
+#endif /* BSP_USING_UART6 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

bsp/hc32/ev_hc32f472_lqfp100/board/drv_config.h

@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2024-02-20     CDT          first version
+ */
+
+#ifndef __DRV_CONFIG_H__
+#define __DRV_CONFIG_H__
+
+#include <board.h>
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "dma_config.h"
+#include "uart_config.h"
+#include "spi_config.h"
+#include "adc_config.h"
+#include "dac_config.h"
+#include "gpio_config.h"
+#include "can_config.h"
+#include "pm_config.h"
+#include "i2c_config.h"
+#include "qspi_config.h"
+#include "pulse_encoder_config.h"
+#include "timer_config.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

bsp/hc32/ev_hc32f472_lqfp100/board/hc32f4xx_conf.h

@@ -0,0 +1,136 @@
+/**
+ *******************************************************************************
+ * @file  template/source/hc32f4xx_conf.h
+ * @brief This file contains HC32 Series Device Driver Library usage management.
+ @verbatim
+   Change Logs:
+   Date             Author          Notes
+   2023-05-31       CDT             First version
+ @endverbatim
+ *******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                    opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+#ifndef __HC32F4XX_CONF_H__
+#define __HC32F4XX_CONF_H__
+
+/*******************************************************************************
+ * Include files
+ ******************************************************************************/
+#include <rtconfig.h>
+
+/* C binding of definitions if building with C++ compiler */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/*******************************************************************************
+ * Global type definitions ('typedef')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Global pre-processor symbols/macros ('#define')
+ ******************************************************************************/
+
+/**
+ * @brief This is the list of modules to be used in the Device Driver Library.
+ * Select the modules you need to use to DDL_ON.
+ * @note LL_ICG_ENABLE must be turned on(DDL_ON) to ensure that the chip works
+ * properly.
+ * @note LL_UTILITY_ENABLE must be turned on(DDL_ON) if using Device Driver
+ * Library.
+ * @note LL_PRINT_ENABLE must be turned on(DDL_ON) if using printf function.
+ */
+#define LL_ICG_ENABLE                               (DDL_ON)
+#define LL_UTILITY_ENABLE                           (DDL_ON)
+#define LL_PRINT_ENABLE                             (DDL_OFF)
+
+#define LL_ADC_ENABLE                               (DDL_ON)
+#define LL_AES_ENABLE                               (DDL_ON)
+#define LL_AOS_ENABLE                               (DDL_ON)
+#define LL_CLK_ENABLE                               (DDL_ON)
+#define LL_CMP_ENABLE                               (DDL_ON)
+#define LL_CRC_ENABLE                               (DDL_ON)
+#define LL_CTC_ENABLE                               (DDL_ON)
+#define LL_DAC_ENABLE                               (DDL_ON)
+#define LL_DBGC_ENABLE                              (DDL_OFF)
+#define LL_DCU_ENABLE                               (DDL_ON)
+#define LL_DMA_ENABLE                               (DDL_ON)
+#define LL_EFM_ENABLE                               (DDL_ON)
+#define LL_EMB_ENABLE                               (DDL_ON)
+#define LL_EVENT_PORT_ENABLE                        (DDL_OFF)
+#define LL_FCG_ENABLE                               (DDL_ON)
+#define LL_FCM_ENABLE                               (DDL_ON)
+#define LL_GPIO_ENABLE                              (DDL_ON)
+#define LL_HASH_ENABLE                              (DDL_ON)
+#define LL_I2C_ENABLE                               (DDL_ON)
+#define LL_INTERRUPTS_ENABLE                        (DDL_ON)
+#define LL_KEYSCAN_ENABLE                           (DDL_ON)
+#define LL_MCAN_ENABLE                              (DDL_ON)
+#define LL_MPU_ENABLE                               (DDL_ON)
+#define LL_PWC_ENABLE                               (DDL_ON)
+#define LL_QSPI_ENABLE                              (DDL_ON)
+#define LL_RMU_ENABLE                               (DDL_ON)
+#define LL_RTC_ENABLE                               (DDL_ON)
+#define LL_SMC_ENABLE                               (DDL_ON)
+#define LL_SPI_ENABLE                               (DDL_ON)
+#define LL_SRAM_ENABLE                              (DDL_ON)
+#define LL_SWDT_ENABLE                              (DDL_ON)
+#define LL_TMR0_ENABLE                              (DDL_ON)
+#define LL_TMR4_ENABLE                              (DDL_ON)
+#define LL_TMR6_ENABLE                              (DDL_ON)
+#define LL_TMRA_ENABLE                              (DDL_ON)
+#define LL_TRNG_ENABLE                              (DDL_ON)
+#define LL_USART_ENABLE                             (DDL_ON)
+#define LL_WDT_ENABLE                               (DDL_ON)
+
+/**
+ * @brief The following is a list of currently supported BSP boards.
+ */
+#define BSP_EV_HC32F472_LQFP80                      (9U)
+
+/**
+ * @brief The macro BSP_EV_HC32F4XX is used to specify the BSP board currently
+ * in use.
+ * The value should be set to one of the list of currently supported BSP boards.
+ * @note  If there is no supported BSP board or the BSP function is not used,
+ * the value needs to be set to 0U.
+ */
+#define BSP_EV_HC32F4XX                             (0U)
+
+/**
+ * @brief This is the list of BSP components to be used.
+ * Select the components you need to use to DDL_ON.
+ */
+#define BSP_24CXX_ENABLE                            (DDL_OFF)
+#define BSP_GT9XX_ENABLE                            (DDL_OFF)
+#define BSP_IS61LV6416_ENABLE                       (DDL_OFF)
+#define BSP_NT35510_ENABLE                          (DDL_OFF)
+#define BSP_TCA9539_ENABLE                          (DDL_OFF)
+#define BSP_W25QXX_ENABLE                           (DDL_OFF)
+#define BSP_INT_KEY_ENABLE                          (DDL_OFF)
+
+/*******************************************************************************
+ * Global variable definitions ('extern')
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Global function prototypes (definition in C source)
+ ******************************************************************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __HC32F4XX_CONF_H__ */
+
+/*******************************************************************************
+ * EOF (not truncated)
+ ******************************************************************************/

bsp/hc32/ev_hc32f472_lqfp100/board/linker_scripts/link.icf

@@ -0,0 +1,116 @@
+/***************************************************************************//**
+ * \file HC32F472.icf
+ * \version 1.0
+ *
+ * \brief Linker file for the IAR compiler.
+ *
+********************************************************************************
+* \copyright
+ * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                    opensource.org/licenses/BSD-3-Clause
+*******************************************************************************/
+/*###ICF### Section handled by ICF editor, don't touch! *****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
+
+// Check that necessary symbols have been passed to linker via command line interface
+if((!isdefinedsymbol(_LINK_RAM_)) && (!isdefinedsymbol(_LINK_FLASH_))) {
+  error "Link location not defined or not supported!";
+}
+if((!isdefinedsymbol(_HC32F472_512K_)) && (!isdefinedsymbol(_HC32F472_256K_SINGLE_)) && (!isdefinedsymbol(_HC32F472_256K_DUAL_))) {
+  error "Mcu type or size not defined or not supported!";
+}
+
+
+/*******************************************************************************
+ * Memory address and size definitions
+ ******************************************************************************/
+define symbol ram1_base_address = 0x1FFF8000;
+define symbol ram1_end_address  = 0x20007FFF;
+
+if(isdefinedsymbol(_LINK_RAM_)) {
+  define symbol ram_start_reserve = 0x8000;
+  define symbol rom1_base_address = ram1_base_address;
+  define symbol rom1_end_address  = rom1_base_address + ram_start_reserve - 0x01;
+  define symbol rom2_base_address = 0x0;
+  define symbol rom2_end_address  = 0x0;
+  define symbol rom3_base_address = 0x0;
+  define symbol rom3_end_address = 0x0;
+} else {
+  define symbol ram_start_reserve = 0x0;
+  define symbol rom1_base_address = 0x0;
+  define symbol rom3_base_address = 0x03000000;
+  define symbol rom3_end_address = 0x030017FF;
+  if(isdefinedsymbol(_HC32F472_512K_)) {
+    define symbol rom1_end_address  = 0x0007FFFF;
+    define symbol rom2_base_address = 0x0;
+    define symbol rom2_end_address  = 0x0;
+  } else if (isdefinedsymbol(_HC32F472_256K_SINGLE_)) {
+    define symbol rom1_end_address  = 0x0003FFFF;
+    define symbol rom2_base_address = 0x0;
+    define symbol rom2_end_address  = 0x0;
+  } else if (isdefinedsymbol(_HC32F472_256K_DUAL_)) {
+    define symbol rom1_end_address  = 0x0001FFFF;
+    define symbol rom2_base_address = 0x00040000;
+    define symbol rom2_end_address  = 0x0005FFFF;
+  }
+}
+
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = rom1_base_address;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_IROM1_start__ = rom1_base_address;
+define symbol __ICFEDIT_region_IROM1_end__   = rom1_end_address;
+define symbol __ICFEDIT_region_IROM2_start__ = rom2_base_address;
+define symbol __ICFEDIT_region_IROM2_end__   = rom2_end_address;
+define symbol __ICFEDIT_region_IROM3_start__ = rom3_base_address;
+define symbol __ICFEDIT_region_IROM3_end__   = rom3_end_address;
+define symbol __ICFEDIT_region_EROM1_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM1_end__   = 0x0;
+define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM2_end__   = 0x0;
+define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
+define symbol __ICFEDIT_region_EROM3_end__   = 0x0;
+define symbol __ICFEDIT_region_IRAM1_start__ = ram1_base_address + ram_start_reserve;
+define symbol __ICFEDIT_region_IRAM1_end__   = ram1_end_address;
+define symbol __ICFEDIT_region_IRAM2_start__ = 0x200F0000;
+define symbol __ICFEDIT_region_IRAM2_end__   = 0x200F0FFF;
+define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM1_end__   = 0x0;
+define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM2_end__   = 0x0;
+define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
+define symbol __ICFEDIT_region_ERAM3_end__   = 0x0;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0xC00;
+define symbol __ICFEDIT_size_proc_stack__ = 0x0;
+define symbol __ICFEDIT_size_heap__   = 0x400;
+/**** End of ICF editor section. ###ICF###*/
+
+/*******************************************************************************
+ * Memory definitions
+ ******************************************************************************/
+define memory mem with size = 4G;
+define region ROM_region       =   mem:[from __ICFEDIT_region_IROM1_start__   to __ICFEDIT_region_IROM1_end__]
+                                 | mem:[from __ICFEDIT_region_IROM2_start__   to __ICFEDIT_region_IROM2_end__];
+define region OTP_region       =   mem:[from __ICFEDIT_region_IROM3_start__   to __ICFEDIT_region_IROM3_end__];
+define region RAM_region       =   mem:[from __ICFEDIT_region_IRAM1_start__   to __ICFEDIT_region_IRAM1_end__]
+                                 | mem:[from __ICFEDIT_region_IRAM2_start__   to __ICFEDIT_region_IRAM2_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in OTP_region   { readonly section .otp_data };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };

bsp/hc32/ev_hc32f472_lqfp100/board/linker_scripts/link.ld

@@ -0,0 +1,276 @@
+/******************************************************************************
+ * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
+ *
+ * This software component is licensed by XHSC under BSD 3-Clause license
+ * (the "License"); You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                    opensource.org/licenses/BSD-3-Clause
+ *
+ */
+/*****************************************************************************/
+/*  File        HC32F472xE.ld                                                */
+/*  Abstract    Linker script for HC32F472 Device with                       */
+/*              512KByte FLASH, 68KByte RAM                                  */
+/*  Version     V1.0                                                         */
+/*  Date        2022-06-30                                                   */
+/*****************************************************************************/
+
+/* Custom defines, according to section 7.7 of the user manual.
+   Take OTP sector 16 for example. */
+__OTP_DATA_START = 0x03000000;
+__OTP_DATA_SIZE  = 2048;
+__OTP_LOCK_START = 0x03001800;
+__OTP_LOCK_SIZE  = 728;
+
+/* Use contiguous memory regions for simple. */
+MEMORY
+{
+    FLASH       (rx): ORIGIN = 0x00000000, LENGTH = 512K
+    OTP_DATA    (rx): ORIGIN = __OTP_DATA_START, LENGTH = __OTP_DATA_SIZE
+    OTP_LOCK    (rx): ORIGIN = __OTP_LOCK_START, LENGTH = __OTP_LOCK_SIZE
+    RAM        (rwx): ORIGIN = 0x1FFF8000, LENGTH = 64K
+    RAMB       (rwx): ORIGIN = 0x200F0000, LENGTH = 4K
+    QSPI_ROM    (rx): ORIGIN = 0x98000000, LENGTH = 8M
+}
+
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+    .vectors :
+    {
+        . = ALIGN(4);
+        KEEP(*(.vectors))
+        . = ALIGN(4);
+    } >FLASH
+
+    .icg_sec 0x00000400 :
+    {
+        KEEP(*(.icg_sec))
+    } >FLASH
+
+    .ex_rom :
+    {
+        . = ALIGN(4);
+        KEEP(*(.ex_rom))
+        . = ALIGN(4);
+    } >QSPI_ROM
+
+    .text :
+    {
+        . = ALIGN(4);
+        _stext = .;
+        KEEP(*(.isr_vector))            /* Startup code */
+        . = ALIGN(4);
+        *(.text)                        /* remaining code */
+        *(.text.*)                      /* remaining code */
+        *(.rodata)                      /* read-only data (constants) */
+        *(.rodata*)
+        *(.glue_7)
+        *(.glue_7t)
+        *(.gnu.linkonce.t*)
+
+        /* section information for finsh shell */
+        . = ALIGN(4);
+        __fsymtab_start = .;
+        KEEP(*(FSymTab))
+        __fsymtab_end = .;
+        . = ALIGN(4);
+        __vsymtab_start = .;
+        KEEP(*(VSymTab))
+        __vsymtab_end = .;
+        . = ALIGN(4);
+
+        /* section information for initial. */
+        . = ALIGN(4);
+        __rt_init_start = .;
+        KEEP(*(SORT(.rti_fn*)))
+        __rt_init_end = .;
+        . = ALIGN(4);
+
+        . = ALIGN(4);
+        _etext = .;
+    } >FLASH
+
+    .rodata :
+    {
+        . = ALIGN(4);
+        *(.rodata)
+        *(.rodata*)
+        . = ALIGN(4);
+    } >FLASH
+
+    .ARM.extab :
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } >FLASH
+
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } >FLASH
+    __exidx_end = .;
+
+    .preinit_array :
+    {
+        . = ALIGN(4);
+        /* preinit data */
+        PROVIDE_HIDDEN (__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE_HIDDEN (__preinit_array_end = .);
+        . = ALIGN(4);
+    } >FLASH
+
+    .init_array :
+    {
+        . = ALIGN(4);
+        /* init data */
+        PROVIDE_HIDDEN (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE_HIDDEN (__init_array_end = .);
+        . = ALIGN(4);
+    } >FLASH
+
+    .fini_array :
+    {
+        . = ALIGN(4);
+        /* finit data */
+        PROVIDE_HIDDEN (__fini_array_start = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE_HIDDEN (__fini_array_end = .);
+        . = ALIGN(4);
+    } >FLASH
+
+    __etext = ALIGN(4);
+
+    .otp_data_sec :
+    {
+        KEEP(*(.otp_data_sec))
+    } >OTP_DATA
+
+    .otp_lock_sec :
+    {
+        KEEP(*(.otp_lock_sec))
+    } >OTP_LOCK
+
+    .data : AT (__etext)
+    {
+        . = ALIGN(4);
+        __data_start__ = .;
+        *(vtable)
+        *(.data)
+        *(.data*)
+        *(.gnu.linkonce.d*)
+        . = ALIGN(4);
+        *(.ramfunc)
+        *(.ramfunc*)
+        . = ALIGN(4);
+        __data_end__ = .;
+    } >RAM
+
+    __etext_ramb = __etext + ALIGN (SIZEOF(.data), 4);
+    .ramb_data : AT (__etext_ramb)
+    {
+        . = ALIGN(4);
+        __data_start_ramb__ = .;
+        *(.ramb_data)
+        *(.ramb_data*)
+        . = ALIGN(4);
+        __data_end_ramb__ = .;
+    } >RAMB
+
+    .bss (NOLOAD):
+    {
+        . = ALIGN(4);
+        _sbss = .;
+        __bss_start__ = _sbss;
+        *(.bss)
+        *(.bss*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = .;
+        __bss_end__ = _ebss;
+        . = ALIGN(4);
+        *(.noinit*)
+        . = ALIGN(4);
+    } >RAM
+
+    .ramb_bss :
+    {
+        . = ALIGN(4);
+        __bss_start_ramb__ = .;
+        *(.ramb_bss)
+        *(.ramb_bss*)
+        . = ALIGN(4);
+        __bss_end_ramb__ = .;
+    } >RAMB
+
+    .heap_stack (COPY) :
+    {
+        . = ALIGN(8);
+        __end__ = .;
+        PROVIDE(end = .);
+        PROVIDE(_end = .);
+        *(.heap*)
+        . = ALIGN(8);
+        __HeapLimit = .;
+
+        __StackLimit = .;
+        *(.stack*)
+        . = ALIGN(8);
+        __StackTop = .;
+    } >RAM
+
+    /DISCARD/ :
+    {
+        libc.a (*)
+        libm.a (*)
+        libgcc.a (*)
+    }
+
+    .ARM.attributes 0 : { *(.ARM.attributes) }
+
+    PROVIDE(_stack = __StackTop);
+    PROVIDE(_Min_Heap_Size = __HeapLimit - __HeapBase);
+    PROVIDE(_Min_Stack_Size = __StackTop - __StackLimit);
+
+    __RamEnd = ORIGIN(RAM) + LENGTH(RAM);
+    ASSERT(__StackTop <= __RamEnd, "region RAM overflowed with stack")
+
+    /* Stabs debugging sections.  */
+    .stab          0 : { *(.stab) }
+    .stabstr       0 : { *(.stabstr) }
+    .stab.excl     0 : { *(.stab.excl) }
+    .stab.exclstr  0 : { *(.stab.exclstr) }
+    .stab.index    0 : { *(.stab.index) }
+    .stab.indexstr 0 : { *(.stab.indexstr) }
+    .comment       0 : { *(.comment) }
+    /* DWARF debug sections.
+     * Symbols in the DWARF debugging sections are relative to the beginning
+     * of the section so we begin them at 0.  */
+    /* DWARF 1 */
+    .debug          0 : { *(.debug) }
+    .line           0 : { *(.line) }
+    /* GNU DWARF 1 extensions */
+    .debug_srcinfo  0 : { *(.debug_srcinfo) }
+    .debug_sfnames  0 : { *(.debug_sfnames) }
+    /* DWARF 1.1 and DWARF 2 */
+    .debug_aranges  0 : { *(.debug_aranges) }
+    .debug_pubnames 0 : { *(.debug_pubnames) }
+    /* DWARF 2 */
+    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+    .debug_abbrev   0 : { *(.debug_abbrev) }
+    .debug_line     0 : { *(.debug_line) }
+    .debug_frame    0 : { *(.debug_frame) }
+    .debug_str      0 : { *(.debug_str) }
+    .debug_loc      0 : { *(.debug_loc) }
+    .debug_macinfo  0 : { *(.debug_macinfo) }
+    /* SGI/MIPS DWARF 2 extensions */
+    .debug_weaknames 0 : { *(.debug_weaknames) }
+    .debug_funcnames 0 : { *(.debug_funcnames) }
+    .debug_typenames 0 : { *(.debug_typenames) }
+    .debug_varnames  0 : { *(.debug_varnames) }
+}

bsp/hc32/ev_hc32f472_lqfp100/board/linker_scripts/link.sct

@@ -0,0 +1,22 @@
+; ****************************************************************
+; Scatter-Loading Description File
+; ****************************************************************
+LR_IROM1 0x00000000 0x00080000  {    ; load region size_region
+    ER_IROM1 0x00000000 0x00080000  {  ; load address = execution address
+        *.o (RESET, +First)
+        *(InRoot$$Sections)
+        .ANY (+RO)
+        .ANY (+XO)
+    }
+    RW_IRAM1 0x1FFF8000 UNINIT 0x00000008  {  ; RW data
+        *(.bss.noinit)
+    }
+    RW_IRAM2 0x1FFF8008 0x0000FFF8  {  ; RW data
+        .ANY (+RW +ZI)
+        .ANY (RAMCODE)
+    }
+    RW_IRAMB 0x200F0000 0x00001000  {  ; RW data
+        .ANY (+RW +ZI)
+    }
+}
+

bsp/hc32/ev_hc32f472_lqfp100/board/ports/fal_cfg.h

@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2024-02-20     CDT          first version
+ */
+
+#ifndef _FAL_CFG_H_
+#define _FAL_CFG_H_
+
+#include <rtthread.h>
+#include <board.h>
+
+/* enable hc32f4 onchip flash driver sample */
+#define FAL_FLASH_PORT_DRIVER_HC32F4
+/* enable SFUD flash driver sample */
+#define FAL_FLASH_PORT_DRIVER_SFUD
+
+extern const struct fal_flash_dev hc32_onchip_flash;
+extern struct fal_flash_dev ext_nor_flash0;
+
+/* flash device table */
+#define FAL_FLASH_DEV_TABLE                                          \
+{                                                                    \
+    &hc32_onchip_flash,                                              \
+    &ext_nor_flash0,                                                 \
+}
+
+/* ====================== Partition Configuration ========================== */
+#ifdef FAL_PART_HAS_TABLE_CFG
+/* partition table */
+#define FAL_PART_TABLE                                                                 \
+{                                                                                      \
+    {FAL_PART_MAGIC_WROD,          "app",   "onchip_flash",   0,  256 * 1024, 0},      \
+    {FAL_PART_MAGIC_WROD,   "filesystem",         "w25q64",   0,  8 * 1024 * 1024, 0}, \
+}
+#endif /* FAL_PART_HAS_TABLE_CFG */
+
+#endif /* _FAL_CFG_H_ */

bsp/hc32/ev_hc32f472_lqfp100/board/ports/tca9539_port.h

@@ -0,0 +1,67 @@
+/*
+ * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-04-28     CDT          first version
+ */
+
+#ifndef __TCA9539_PORT_H__
+#define __TCA9539_PORT_H__
+
+#include "tca9539.h"
+
+/**
+ * @defgroup HC32F472_EV_IO_Function_Sel Expand IO function definition
+ * @{
+ */
+#define EIO_USBFS_OC                    (TCA9539_IO_PIN0)   /* USBFS over-current, input */
+#define EIO_SCI_CD                      (TCA9539_IO_PIN1)   /* Smart card detect, input */
+#define EIO_TOUCH_INT                   (TCA9539_IO_PIN2)   /* Touch screen interrupt, input */
+#define EIO_RTCS_CTRST                  (TCA9539_IO_PIN5)   /* 'CS' for Resistor touch panel or 'Reset' for Cap touch panel, output */
+#define EIO_LCD_RST                     (TCA9539_IO_PIN6)   /* LCD panel reset, output */
+#define EIO_LCD_BKL                     (TCA9539_IO_PIN7)   /* LCD panel back light, output */
+
+#define EIO_LIN2_SLEEP                  (TCA9539_IO_PIN0)   /* LIN1 PHY sleep, output */
+#define EIO_LIN1_SLEEP                  (TCA9539_IO_PIN1)   /* LIN2 PHY sleep, output */
+#define EIO_CAN1_STB                    (TCA9539_IO_PIN2)   /* CAN1 PHY standby, output */
+#define EIO_CAN2_STB                    (TCA9539_IO_PIN3)   /* CAN2 PHY standby, output */
+#define EIO_CAN3_STB                    (TCA9539_IO_PIN4)   /* CAN3 PHY standby, output */
+#define EIO_LED_RED                     (TCA9539_IO_PIN5)   /* Red LED, output */
+#define EIO_LED_YELLOW                  (TCA9539_IO_PIN6)   /* Yellow LED, output */
+#define EIO_LED_BLUE                    (TCA9539_IO_PIN7)   /* Blue LED, output */
+/**
+ * @}
+ */
+
+/**
+ * @defgroup BSP_LED_PortPin_Sel BSP LED port/pin definition
+ * @{
+ */
+#define LED_RED_PORT                    (TCA9539_IO_PORT1)
+#define LED_RED_PIN                     (EIO_LED_RED)
+#define LED_YELLOW_PORT                 (TCA9539_IO_PORT1)
+#define LED_YELLOW_PIN                  (EIO_LED_YELLOW)
+#define LED_BLUE_PORT                   (TCA9539_IO_PORT1)
+#define LED_BLUE_PIN                    (EIO_LED_BLUE)
+/**
+ * @}
+ */
+
+/**
+ * @defgroup BSP_CAN_PortPin_Sel BSP CAN PHY STB port/pin definition
+ * @{
+ */
+#define CAN1_STB_PORT                   (TCA9539_IO_PORT1)
+#define CAN1_STB_PIN                    (EIO_CAN1_STB)
+#define CAN2_STB_PORT                   (TCA9539_IO_PORT1)
+#define CAN2_STB_PIN                    (EIO_CAN2_STB)
+#define CAN3_STB_PORT                   (TCA9539_IO_PORT1)
+#define CAN3_STB_PIN                    (EIO_CAN3_STB)
+/**
+ * @}
+ */
+
+#endif

bsp/hc32/ev_hc32f472_lqfp100/project.eww

@@ -0,0 +1,10 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<workspace>
+  <project>
+    <path>$WS_DIR$\project.ewp</path>
+  </project>
+  <batchBuild/>
+</workspace>
+
+

bsp/hc32/ev_hc32f472_lqfp100/project.uvoptx

@@ -0,0 +1,189 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
+
+  <SchemaVersion>1.0</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Extensions>
+    <cExt>*.c</cExt>
+    <aExt>*.s*; *.src; *.a*</aExt>
+    <oExt>*.obj; *.o</oExt>
+    <lExt>*.lib</lExt>
+    <tExt>*.txt; *.h; *.inc; *.md</tExt>
+    <pExt>*.plm</pExt>
+    <CppX>*.cpp</CppX>
+    <nMigrate>0</nMigrate>
+  </Extensions>
+
+  <DaveTm>
+    <dwLowDateTime>0</dwLowDateTime>
+    <dwHighDateTime>0</dwHighDateTime>
+  </DaveTm>
+
+  <Target>
+    <TargetName>rt-thread</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>8000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>0</RunSim>
+        <RunTarget>1</RunTarget>
+        <RunAbUc>0</RunAbUc>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\build\keil\List\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>1</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>255</CpuCode>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <tRtrace>1</tRtrace>
+        <sRSysVw>1</sRSysVw>
+        <tRSysVw>1</tRSysVw>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <bEvRecOn>1</bEvRecOn>
+        <bSchkAxf>0</bSchkAxf>
+        <bTchkAxf>0</bTchkAxf>
+        <nTsel>3</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>BIN\CMSIS_AGDI.dll</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>CMSIS_AGDI</Key>
+          <Name>-X"" -O206 -S0 -C0 -P00 -FO15 -FD1FFF8000 -FC4000 -FN2 -FF0HC32F472_256K -FS00 -FL080000 -FP0($$Device:HC32F472PETI$FlashARM\HC32F472_256K.FLM) -FF1HC32F472_otp -FS13000C00 -FL1400 -FP1($$Device:HC32F472PETI$FlashARM\HC32F472_otp.FLM)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>UL2CM3(-S0 -C0 -P0 -FD1FFF8000 -FC1000 -FN1 -FF0HC32F472_256K -FS00 -FL080000 -FP0($$Device:HC32F472PETI$FlashARM\HC32F472_256K.FLM))</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>CMSIS_AGDI</Key>
+          <Name>-X"" -O206 -S0 -C0 -P00 -FO15 -FD1FFF8000 -FC4000 -FN2 -FF0HC32F472_256K -FS00 -FL080000 -FP0($$Device:HC32F472PETI$FlashARM\HC32F472_256K.FLM) -FF1HC32F472_otp -FS13000C00 -FL1400 -FP1($$Device:HC32F472PETI$FlashARM\HC32F472_otp.FLM)</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <Tracepoint>
+        <THDelay>0</THDelay>
+      </Tracepoint>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>0</periodic>
+        <aLwin>0</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>0</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+      <bLintAuto>0</bLintAuto>
+      <bAutoGenD>0</bAutoGenD>
+      <LntExFlags>0</LntExFlags>
+      <pMisraName></pMisraName>
+      <pszMrule></pszMrule>
+      <pSingCmds></pSingCmds>
+      <pMultCmds></pMultCmds>
+      <pMisraNamep></pMisraNamep>
+      <pszMrulep></pszMrulep>
+      <pSingCmdsp></pSingCmdsp>
+      <pMultCmdsp></pMultCmdsp>
+      <DebugDescription>
+        <Enable>1</Enable>
+        <EnableFlashSeq>0</EnableFlashSeq>
+        <EnableLog>0</EnableLog>
+        <Protocol>2</Protocol>
+        <DbgClock>1000000</DbgClock>
+      </DebugDescription>
+    </TargetOption>
+  </Target>
+
+</ProjectOpt>

bsp/hc32/ev_hc32f472_lqfp100/rtconfig.h

@@ -0,0 +1,271 @@
+#ifndef RT_CONFIG_H__
+#define RT_CONFIG_H__
+
+/* Automatically generated file; DO NOT EDIT. */
+/* RT-Thread Configuration */
+
+/* RT-Thread Kernel */
+
+#define RT_NAME_MAX 8
+#define RT_CPUS_NR 1
+#define RT_ALIGN_SIZE 8
+#define RT_THREAD_PRIORITY_32
+#define RT_THREAD_PRIORITY_MAX 32
+#define RT_TICK_PER_SECOND 1000
+#define RT_USING_OVERFLOW_CHECK
+#define RT_USING_HOOK
+#define RT_HOOK_USING_FUNC_PTR
+#define RT_USING_IDLE_HOOK
+#define RT_IDLE_HOOK_LIST_SIZE 4
+#define IDLE_THREAD_STACK_SIZE 256
+
+/* kservice optimization */
+
+
+/* klibc optimization */
+
+#define RT_USING_DEBUG
+#define RT_DEBUGING_COLOR
+#define RT_DEBUGING_CONTEXT
+
+/* Inter-Thread communication */
+
+#define RT_USING_SEMAPHORE
+#define RT_USING_MUTEX
+#define RT_USING_EVENT
+#define RT_USING_MAILBOX
+#define RT_USING_MESSAGEQUEUE
+
+/* Memory Management */
+
+#define RT_USING_MEMPOOL
+#define RT_USING_SMALL_MEM
+#define RT_USING_SMALL_MEM_AS_HEAP
+#define RT_USING_HEAP
+#define RT_USING_DEVICE
+#define RT_USING_CONSOLE
+#define RT_CONSOLEBUF_SIZE 128
+#define RT_CONSOLE_DEVICE_NAME "uart2"
+#define RT_VER_NUM 0x50200
+#define RT_BACKTRACE_LEVEL_MAX_NR 32
+#define RT_USING_HW_ATOMIC
+#define RT_USING_CPU_FFS
+#define ARCH_ARM
+#define ARCH_ARM_CORTEX_M
+#define ARCH_ARM_CORTEX_M4
+
+/* RT-Thread Components */
+
+#define RT_USING_COMPONENTS_INIT
+#define RT_USING_USER_MAIN
+#define RT_MAIN_THREAD_STACK_SIZE 2048
+#define RT_MAIN_THREAD_PRIORITY 10
+#define RT_USING_MSH
+#define RT_USING_FINSH
+#define FINSH_USING_MSH
+#define FINSH_THREAD_NAME "tshell"
+#define FINSH_THREAD_PRIORITY 20
+#define FINSH_THREAD_STACK_SIZE 4096
+#define FINSH_USING_HISTORY
+#define FINSH_HISTORY_LINES 5
+#define FINSH_USING_SYMTAB
+#define FINSH_CMD_SIZE 80
+#define MSH_USING_BUILT_IN_COMMANDS
+#define FINSH_USING_DESCRIPTION
+#define FINSH_ARG_MAX 10
+#define FINSH_USING_OPTION_COMPLETION
+
+/* DFS: device virtual file system */
+
+
+/* Device Drivers */
+
+#define RT_USING_DEVICE_IPC
+#define RT_UNAMED_PIPE_NUMBER 64
+#define RT_USING_SYSTEM_WORKQUEUE
+#define RT_SYSTEM_WORKQUEUE_STACKSIZE 2048
+#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
+#define RT_USING_SERIAL
+#define RT_USING_SERIAL_V1
+#define RT_SERIAL_USING_DMA
+#define RT_SERIAL_RB_BUFSZ 64
+#define RT_USING_PIN
+
+/* Using USB */
+
+
+/* C/C++ and POSIX layer */
+
+/* ISO-ANSI C layer */
+
+/* Timezone and Daylight Saving Time */
+
+#define RT_LIBC_USING_LIGHT_TZ_DST
+#define RT_LIBC_TZ_DEFAULT_HOUR 8
+#define RT_LIBC_TZ_DEFAULT_MIN 0
+#define RT_LIBC_TZ_DEFAULT_SEC 0
+
+/* POSIX (Portable Operating System Interface) layer */
+
+
+/* Interprocess Communication (IPC) */
+
+
+/* Socket is in the 'Network' category */
+
+
+/* Network */
+
+
+/* Memory protection */
+
+
+/* Utilities */
+
+
+/* RT-Thread Utestcases */
+
+
+/* RT-Thread online packages */
+
+/* IoT - internet of things */
+
+
+/* Wi-Fi */
+
+/* Marvell WiFi */
+
+
+/* Wiced WiFi */
+
+
+/* IoT Cloud */
+
+
+/* security packages */
+
+
+/* language packages */
+
+/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
+
+
+/* XML: Extensible Markup Language */
+
+
+/* multimedia packages */
+
+/* LVGL: powerful and easy-to-use embedded GUI library */
+
+
+/* u8g2: a monochrome graphic library */
+
+
+/* tools packages */
+
+
+/* system packages */
+
+/* enhanced kernel services */
+
+
+/* acceleration: Assembly language or algorithmic acceleration packages */
+
+
+/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
+
+
+/* Micrium: Micrium software products porting for RT-Thread */
+
+
+/* peripheral libraries and drivers */
+
+/* sensors drivers */
+
+
+/* touch drivers */
+
+
+/* Kendryte SDK */
+
+
+/* AI packages */
+
+
+/* Signal Processing and Control Algorithm Packages */
+
+
+/* miscellaneous packages */
+
+/* project laboratory */
+
+/* samples: kernel and components samples */
+
+
+/* entertainment: terminal games and other interesting software packages */
+
+
+/* Arduino libraries */
+
+
+/* Projects and Demos */
+
+
+/* Sensors */
+
+
+/* Display */
+
+
+/* Timing */
+
+
+/* Data Processing */
+
+
+/* Data Storage */
+
+/* Communication */
+
+
+/* Device Control */
+
+
+/* Other */
+
+
+/* Signal IO */
+
+
+/* Uncategorized */
+
+#define SOC_FAMILY_HC32
+#define SOC_SERIES_HC32F4
+
+/* Hardware Drivers Config */
+
+#define SOC_HC32F472MC
+
+/* On-chip Drivers */
+
+#define BSP_USING_ON_CHIP_FLASH_CACHE
+#define BSP_USING_ON_CHIP_FLASH_ICODE_CACHE
+#define BSP_USING_ON_CHIP_FLASH_DCODE_CACHE
+#define BSP_USING_ON_CHIP_FLASH_ICODE_PREFETCH
+
+/* Onboard Peripheral Drivers */
+
+#define BSP_USING_EXT_IO
+
+/* On-chip Peripheral Drivers */
+
+#define BSP_USING_GPIO
+#define BSP_USING_UART
+#define BSP_USING_UART2
+#define BSP_UART2_RX_USING_DMA
+#define BSP_UART2_TX_USING_DMA
+
+/* Board extended module Drivers */
+
+
+#endif

bsp/hc32/ev_hc32f472_lqfp100/rtconfig.py

@@ -0,0 +1,150 @@
+import os
+
+# toolchains options
+ARCH='arm'
+CPU='cortex-m4'
+CROSS_TOOL='gcc'
+
+# bsp lib config
+BSP_LIBRARY_TYPE = None
+
+if os.getenv('RTT_CC'):
+    CROSS_TOOL = os.getenv('RTT_CC')
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+
+# cross_tool provides the cross compiler
+# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
+if  CROSS_TOOL == 'gcc':
+    PLATFORM    = 'gcc'
+    if os.getenv('RTT_EXEC_PATH'):
+        EXEC_PATH = os.getenv('RTT_EXEC_PATH')
+    else:
+        EXEC_PATH   = r'C:/Users/XXYYZZ'
+elif CROSS_TOOL == 'keil':
+    PLATFORM    = 'armcc'
+    EXEC_PATH   = r'C:/Keil_v5'
+elif CROSS_TOOL == 'iar':
+    PLATFORM    = 'iccarm'
+    EXEC_PATH   = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.4'
+
+BUILD = 'debug'
+
+if PLATFORM == 'gcc':
+    # toolchains
+    PREFIX = 'arm-none-eabi-'
+    CC = PREFIX + 'gcc'
+    AS = PREFIX + 'gcc'
+    AR = PREFIX + 'ar'
+    CXX = PREFIX + 'g++'
+    LINK = PREFIX + 'gcc'
+    TARGET_EXT = 'elf'
+    SIZE = PREFIX + 'size'
+    OBJDUMP = PREFIX + 'objdump'
+    OBJCPY = PREFIX + 'objcopy'
+
+    DEVICE = ' -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections'
+    CFLAGS = DEVICE + ' -Dgcc'
+    AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb '
+    LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.ld'
+
+    CPATH = ''
+    LPATH = ''
+
+    if BUILD == 'debug':
+        CFLAGS += ' -O0 -gdwarf-2 -g'
+        AFLAGS += ' -gdwarf-2'
+    else:
+        CFLAGS += ' -O2'
+
+    CXXFLAGS = CFLAGS 
+
+    POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
+
+elif PLATFORM == 'armcc':
+    # toolchains
+    CC = 'armcc'
+    CXX = 'armcc'
+    AS = 'armasm'
+    AR = 'armar'
+    LINK = 'armlink'
+    TARGET_EXT = 'axf'
+
+    DEVICE = ' --cpu Cortex-M4.fp '
+    CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99'
+    AFLAGS = DEVICE + ' --apcs=interwork '
+    LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict'
+    CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include'
+    LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib'
+
+    CFLAGS += ' -D__MICROLIB '
+    AFLAGS += ' --pd "__MICROLIB SETA 1" '
+    LFLAGS += ' --library_type=microlib '
+    EXEC_PATH += '/ARM/ARMCC/bin/'
+
+    if BUILD == 'debug':
+        CFLAGS += ' -g -O0'
+        AFLAGS += ' -g'
+    else:
+        CFLAGS += ' -O2'
+
+    CXXFLAGS = CFLAGS 
+    CFLAGS += ' -std=c99'
+
+    POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
+
+elif PLATFORM == 'iccarm':
+    # toolchains
+    CC = 'iccarm'
+    CXX = 'iccarm'
+    AS = 'iasmarm'
+    AR = 'iarchive'
+    LINK = 'ilinkarm'
+    TARGET_EXT = 'out'
+
+    DEVICE = '-Dewarm'
+
+    CFLAGS = DEVICE
+    CFLAGS += ' --diag_suppress Pa050'
+    CFLAGS += ' --no_cse'
+    CFLAGS += ' --no_unroll'
+    CFLAGS += ' --no_inline'
+    CFLAGS += ' --no_code_motion'
+    CFLAGS += ' --no_tbaa'
+    CFLAGS += ' --no_clustering'
+    CFLAGS += ' --no_scheduling'
+    CFLAGS += ' --endian=little'
+    CFLAGS += ' --cpu=Cortex-M4'
+    CFLAGS += ' -e'
+    CFLAGS += ' --fpu=VFPv4_sp'
+    CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
+    CFLAGS += ' --silent'
+
+    AFLAGS = DEVICE
+    AFLAGS += ' -s+'
+    AFLAGS += ' -w+'
+    AFLAGS += ' -r'
+    AFLAGS += ' --cpu Cortex-M4'
+    AFLAGS += ' --fpu VFPv4_sp'
+    AFLAGS += ' -S'
+
+    if BUILD == 'debug':
+        CFLAGS += ' --debug'
+        CFLAGS += ' -On'
+    else:
+        CFLAGS += ' -Oh'
+
+    LFLAGS = ' --config "board/linker_scripts/link.icf"'
+    LFLAGS += ' --entry __iar_program_start'
+
+    CXXFLAGS = CFLAGS
+    
+    EXEC_PATH = EXEC_PATH + '/arm/bin/'
+    POST_ACTION = 'ielftool --bin $TARGET rtthread.bin'
+
+def dist_handle(BSP_ROOT, dist_dir):
+    import sys
+    cwd_path = os.getcwd()
+    sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools'))
+    from sdk_dist import dist_do_building
+    dist_do_building(BSP_ROOT, dist_dir)

bsp/hc32/ev_hc32f472_lqfp100/template.eww

@@ -0,0 +1,10 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<workspace>
+  <project>
+    <path>$WS_DIR$\template.ewp</path>
+  </project>
+  <batchBuild/>
+</workspace>
+
+

bsp/hc32/ev_hc32f472_lqfp100/template.uvoptx

@@ -0,0 +1,189 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
+
+  <SchemaVersion>1.0</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Extensions>
+    <cExt>*.c</cExt>
+    <aExt>*.s*; *.src; *.a*</aExt>
+    <oExt>*.obj; *.o</oExt>
+    <lExt>*.lib</lExt>
+    <tExt>*.txt; *.h; *.inc; *.md</tExt>
+    <pExt>*.plm</pExt>
+    <CppX>*.cpp</CppX>
+    <nMigrate>0</nMigrate>
+  </Extensions>
+
+  <DaveTm>
+    <dwLowDateTime>0</dwLowDateTime>
+    <dwHighDateTime>0</dwHighDateTime>
+  </DaveTm>
+
+  <Target>
+    <TargetName>rt-thread</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>8000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>0</RunSim>
+        <RunTarget>1</RunTarget>
+        <RunAbUc>0</RunAbUc>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\build\keil\List\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>1</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>255</CpuCode>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <tRtrace>1</tRtrace>
+        <sRSysVw>1</sRSysVw>
+        <tRSysVw>1</tRSysVw>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <bEvRecOn>1</bEvRecOn>
+        <bSchkAxf>0</bSchkAxf>
+        <bTchkAxf>0</bTchkAxf>
+        <nTsel>3</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>BIN\CMSIS_AGDI.dll</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>CMSIS_AGDI</Key>
+          <Name>-X"" -O206 -S0 -C0 -P00 -FO15 -FD1FFF8000 -FC4000 -FN2 -FF0HC32F472_256K -FS00 -FL080000 -FP0($$Device:HC32F472PETI$FlashARM\HC32F472_256K.FLM) -FF1HC32F472_otp -FS13000C00 -FL1400 -FP1($$Device:HC32F472PETI$FlashARM\HC32F472_otp.FLM)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2CM3</Key>
+          <Name>UL2CM3(-S0 -C0 -P0 -FD1FFF8000 -FC1000 -FN1 -FF0HC32F472_256K -FS00 -FL080000 -FP0($$Device:HC32F472PETI$FlashARM\HC32F472_256K.FLM))</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>CMSIS_AGDI</Key>
+          <Name>-X"" -O206 -S0 -C0 -P00 -FO15 -FD1FFF8000 -FC4000 -FN2 -FF0HC32F472_256K -FS00 -FL080000 -FP0($$Device:HC32F472PETI$FlashARM\HC32F472_256K.FLM) -FF1HC32F472_otp -FS13000C00 -FL1400 -FP1($$Device:HC32F472PETI$FlashARM\HC32F472_otp.FLM)</Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint/>
+      <Tracepoint>
+        <THDelay>0</THDelay>
+      </Tracepoint>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>0</periodic>
+        <aLwin>0</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>0</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+      <bLintAuto>0</bLintAuto>
+      <bAutoGenD>0</bAutoGenD>
+      <LntExFlags>0</LntExFlags>
+      <pMisraName></pMisraName>
+      <pszMrule></pszMrule>
+      <pSingCmds></pSingCmds>
+      <pMultCmds></pMultCmds>
+      <pMisraNamep></pMisraNamep>
+      <pszMrulep></pszMrulep>
+      <pSingCmdsp></pSingCmdsp>
+      <pMultCmdsp></pMultCmdsp>
+      <DebugDescription>
+        <Enable>1</Enable>
+        <EnableFlashSeq>0</EnableFlashSeq>
+        <EnableLog>0</EnableLog>
+        <Protocol>2</Protocol>
+        <DbgClock>1000000</DbgClock>
+      </DebugDescription>
+    </TargetOption>
+  </Target>
+
+</ProjectOpt>

bsp/hc32/ev_hc32f472_lqfp100/template.uvprojx

@@ -0,0 +1,391 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
+
+  <SchemaVersion>2.1</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Targets>
+    <Target>
+      <TargetName>rt-thread</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <pCCUsed>5060750::V5.06 update 6 (build 750)::ARMCC</pCCUsed>
+      <uAC6>0</uAC6>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>HC32F472PETI</Device>
+          <Vendor>HDSC</Vendor>
+          <PackID>HDSC.HC32F472.1.0.0</PackID>
+          <PackURL>https://raw.githubusercontent.com/hdscmcu/pack/master/</PackURL>
+          <Cpu>IROM1(0x00000000,0x40000) IROM2(0x03000C00,0x400) IRAM1(0x1FFF8000,0x10000) IRAM2(0x200F0000,0x1000) CPUTYPE("Cortex-M4") FPU2 CLOCK(8000000) ESEL ELITTLE</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile></StartupFile>
+          <FlashDriverDll>CMSIS_AGDI(-S0 -C0 -P00 -FO15 -FD1FFF8000 -FC4000 -FN2 -FF0HC32F472_256K -FS00 -FL0080000 -FP0($$Device:HC32F472PETB$FlashARM\HC32F472_256K.FLM) -FF1HC32F472_otp -FS13000C00 -FL1400 -FP1($$Device:HC32F472PETI$FlashARM\HC32F472_otp.FLM))</FlashDriverDll>
+          <DeviceId>0</DeviceId>
+          <RegisterFile>$$Device:HC32F472PETI$Device\Include\HC32F472PETI.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile>../libraries/hc32f472_ddl/cmsis/Device/HDSC/hc32f4xx/Source/ARM/sfr/HC32F472.SFR</SFDFile>
+          <bCustSvd>1</bCustSvd>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath></RegisterFilePath>
+          <DBRegisterFilePath></DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\build\keil\Obj\</OutputDirectory>
+          <OutputName>rt-thread</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>1</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>0</BrowseInformation>
+          <ListingPath>.\build\keil\List\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopB1X>0</nStopB1X>
+            <nStopB2X>0</nStopB2X>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>1</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name>fromelf --bin !L --output rtthread.bin</UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopA1X>0</nStopA1X>
+            <nStopA2X>0</nStopA2X>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+          <ComprImg>1</ComprImg>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName>SARMCM3.DLL</SimDllName>
+          <SimDllArguments> -REMAP -MPU</SimDllArguments>
+          <SimDlgDll>DCM.DLL</SimDlgDll>
+          <SimDlgDllArguments>-pCM4</SimDlgDllArguments>
+          <TargetDllName>SARMCM3.DLL</TargetDllName>
+          <TargetDllArguments> -MPU</TargetDllArguments>
+          <TargetDlgDll>TCM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4096</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>BIN\UL2CM3.DLL</Flash2>
+          <Flash3></Flash3>
+          <Flash4></Flash4>
+          <pFcarmOut></pFcarmOut>
+          <pFcarmGrp></pFcarmGrp>
+          <pFcArmRoot></pFcArmRoot>
+          <FcArmLst>0</FcArmLst>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>0</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M4"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>1</RvdsVP>
+            <RvdsMve>0</RvdsMve>
+            <RvdsCdeCp>0</RvdsCdeCp>
+            <hadIRAM2>1</hadIRAM2>
+            <hadIROM2>1</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>0</useUlib>
+            <EndSel>1</EndSel>
+            <uLtcg>0</uLtcg>
+            <nSecure>0</nSecure>
+            <RoSelD>3</RoSelD>
+            <RwSelD>3</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>0</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x1FFF8000</StartAddress>
+                <Size>0x10000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x40000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x40000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x03000C00</StartAddress>
+                <Size>0x400</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x1FFF8000</StartAddress>
+                <Size>0x10000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x200F0000</StartAddress>
+                <Size>0x1000</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>1</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>1</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>2</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <uC99>1</uC99>
+            <uGnu>0</uGnu>
+            <useXO>0</useXO>
+            <v6Lang>0</v6Lang>
+            <v6LangP>0</v6LangP>
+            <vShortEn>0</vShortEn>
+            <vShortWch>0</vShortWch>
+            <v6Lto>0</v6Lto>
+            <v6WtE>0</v6WtE>
+            <v6Rtti>0</v6Rtti>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <useXO>0</useXO>
+            <uClangAs>0</uClangAs>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>0</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x00000000</TextAddressRange>
+            <DataAddressRange>0x1FFF8000</DataAddressRange>
+            <pXoBase></pXoBase>
+            <ScatterFile>.\board\linker_scripts\link.sct</ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc></Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+    </Target>
+  </Targets>
+
+  <RTE>
+    <apis/>
+    <components/>
+    <files/>
+  </RTE>
+
+</Project>

bsp/hc32/libraries/.ignore_format.yml

@@ -6,3 +6,4 @@ dir_path:
 - hc32f4a0_ddl
 - hc32f460_ddl
 - hc32f448_ddl
+- hc32f472_ddl

bsp/hc32/libraries/hc32_drivers/drv_flash/drv_flash_f4.c

@@ -111,8 +111,10 @@ int hc32_flash_write(rt_uint32_t addr, const rt_uint8_t *buf, size_t size)
     /* calculate sector information */
     FirstSector = addr / SECTOR_SIZE,
     NbOfSectors = GetSectorNum(addr, size);
+#if defined (HC32F4A0) || defined (HC32F472) || defined (HC32F448)
     /* Sectors disable write protection */
     EFM_SequenceSectorOperateCmd(FirstSector, NbOfSectors, ENABLE);
+#endif
     /* Word align */
     if (0U != (addr % 4))
     {
@@ -149,8 +151,10 @@ int hc32_flash_write(rt_uint32_t addr, const rt_uint8_t *buf, size_t size)
     }
 
 __exit:
+#if defined (HC32F4A0) || defined (HC32F472) || defined (HC32F448)
     /* Sectors enable write protection */
     EFM_SequenceSectorOperateCmd(FirstSector, NbOfSectors, DISABLE);
+#endif
     EFM_FWMC_Cmd(DISABLE);
 
     if (result != RT_EOK)
@@ -189,8 +193,10 @@ int hc32_flash_erase(rt_uint32_t addr, size_t size)
     /* calculate sector information */
     FirstSector = addr / SECTOR_SIZE,
     NbOfSectors = GetSectorNum(addr, size);
+#if defined (HC32F4A0) || defined (HC32F472) || defined (HC32F448)
     /* Sectors disable write protection */
     EFM_SequenceSectorOperateCmd(FirstSector, NbOfSectors, ENABLE);
+#endif
     /* Erase sector */
     for (SectorVal = FirstSector; SectorVal < NbOfSectors; SectorVal++)
     {
@@ -201,8 +207,10 @@ int hc32_flash_erase(rt_uint32_t addr, size_t size)
             break;
         }
     }
+#if defined (HC32F4A0) || defined (HC32F472) || defined (HC32F448)
     /* Sectors enable write protection */
     EFM_SequenceSectorOperateCmd(FirstSector, NbOfSectors, DISABLE);
+#endif
     EFM_FWMC_Cmd(DISABLE);
 
     if (result != RT_EOK)

bsp/hc32/libraries/hc32_drivers/drv_gpio.c

@@ -29,6 +29,8 @@
     #define PIN_MAX_NUM                     ((GPIO_PORT_H * 16) + (__CLZ(__RBIT(GPIO_PIN_02))) + 1)
 #elif defined (HC32F448)
     #define PIN_MAX_NUM                     ((GPIO_PORT_H * 16) + (__CLZ(__RBIT(GPIO_PIN_02))) + 1)
+#elif defined (HC32F472)
+    #define PIN_MAX_NUM                     ((GPIO_PORT_F * 16) + (__CLZ(__RBIT(GPIO_PIN_08))) + 1)
 #endif
 
 #define ITEM_NUM(items)                 sizeof(items) / sizeof(items[0])
@@ -252,6 +254,9 @@ static void hc32_pin_mode(struct rt_device *device, rt_base_t pin, rt_uint8_t mo
     case PIN_MODE_INPUT_PULLDOWN:
         stcGpioInit.u16PinDir   = PIN_DIR_IN;
         stcGpioInit.u16PullUp   = PIN_PU_OFF;
+#if defined (HC32F448) || defined (HC32F472)
+        stcGpioInit.u16PullDown = PIN_PD_ON;
+#endif
         break;
     case PIN_MODE_OUTPUT_OD:
         stcGpioInit.u16PinDir        = PIN_DIR_OUT;

bsp/hc32/libraries/hc32_drivers/drv_irq.c

@@ -68,7 +68,7 @@ rt_err_t hc32_install_irq_handler(struct hc32_irq_config *irq_config,
     return result;
 }
 
-#if defined (HC32F448)
+#if defined (HC32F448) || defined (HC32F472)
 rt_err_t hc32_install_independ_irq_handler(struct hc32_irq_config *irq_config,
         rt_bool_t irq_enable)
 {

bsp/hc32/libraries/hc32_drivers/drv_irq.h

@@ -47,7 +47,7 @@ struct hc32_irq_config
 rt_err_t hc32_install_irq_handler(struct hc32_irq_config *irq_config,
                                   void (*irq_hdr)(void),
                                   rt_bool_t irq_enable);
-#if defined (HC32F448)
+#if defined (HC32F448) || defined (HC32F472)
 rt_err_t hc32_install_independ_irq_handler(struct hc32_irq_config *irq_config,
         rt_bool_t irq_enable);
 #endif

bsp/hc32/libraries/hc32_drivers/drv_pm.c

@@ -66,7 +66,7 @@ static void _uart_console_reconfig(void)
 
  * @retval None
  */
-__WEAKDEF void pwc_seep_enter(uint8_t u8SleepType)
+__WEAKDEF void pwc_sleep_enter(uint8_t u8SleepType)
 {
     DDL_ASSERT(IS_PWC_UNLOCKED());
 
@@ -96,7 +96,7 @@ __WEAKDEF void pwc_seep_enter(uint8_t u8SleepType)
 static void _sleep_enter_idle(void)
 {
     struct pm_sleep_mode_idle_config sleep_idle_cfg = PM_SLEEP_IDLE_CFG;
-    pwc_seep_enter(sleep_idle_cfg.pwc_sleep_type);
+    pwc_sleep_enter(sleep_idle_cfg.pwc_sleep_type);
 }
 
 static void _sleep_enter_deep(void)

bsp/hc32/libraries/hc32_drivers/drv_qspi.c

@@ -7,6 +7,9 @@
  * Date           Author       Notes
  * 2023-06-15     CDT          first version
  * 2023-09-30     CDT          Delete dma transmit interrupt
+ * 2024-02-28     CDT          support HC32F448
+ * 2024-02-29     CDT          Support multi line write/read
+ * 2024-04-18     CDT          support HC32F472
  */
 
 /*******************************************************************************
@@ -37,6 +40,10 @@
 #define QSPI_READ_FUNC                  (0U)
 #define QSPI_WRITE_FUNC                 (1U)
 
+/* QSPI direct communication line */
+#define QSPI_DIRECT_COMM_LINE_ONE       (0U)
+#define QSPI_DIRECT_COMM_LINE_MULTI     (1U)
+
 #define QSPI_BASE_BLK_SIZE              (0x4000000UL)
 #define QSPI_MAX_FLASH_ADDR             (0xFC000000UL)
 
@@ -171,6 +178,68 @@ static int32_t hc32_qspi_search_rom_cmd(uint8_t u8Cmd)
 }
 #endif
 
+
+static int32_t hc32_qspi_check_direct_comm_param(struct rt_qspi_message *message, uint8_t line)
+{
+    if (QSPI_DIRECT_COMM_LINE_ONE == line)
+    {
+        if (message->instruction.qspi_lines > 1)
+        {
+            return LL_ERR_INVD_PARAM;
+        }
+        if (message->address.size != 0)
+        {
+            if ((message->address.qspi_lines > 1) || ((message->address.size % 8) != 0))
+            {
+                return LL_ERR_INVD_PARAM;
+            }
+        }
+        if (message->qspi_data_lines > 1)
+        {
+            return LL_ERR_INVD_PARAM;
+        }
+        if (0U != message->dummy_cycles)
+        {
+            if ((message->dummy_cycles < 3) || (message->dummy_cycles > 18) || (message->dummy_cycles % 8) != 0)
+            {
+                return LL_ERR_INVD_PARAM;
+            }
+        }
+    }
+    else
+    {
+        if ((message->instruction.qspi_lines > 2) && (message->instruction.qspi_lines != 4))
+        {
+            return LL_ERR_INVD_PARAM;
+        }
+        if (message->address.size != 0)
+        {
+            if (((message->address.qspi_lines > 2) && (message->address.qspi_lines != 4)) ||
+                    ((message->address.size % 8) != 0))
+            {
+                return LL_ERR_INVD_PARAM;
+            }
+        }
+        if ((message->qspi_data_lines > 2) && (message->qspi_data_lines != 4))
+        {
+            return LL_ERR_INVD_PARAM;
+        }
+        if ((0U != message->dummy_cycles) && ((message->dummy_cycles < 3) || (message->dummy_cycles > 18)))
+        {
+            return LL_ERR_INVD_PARAM;
+        }
+        if (0U != message->dummy_cycles)
+        {
+            if ((message->dummy_cycles < 3) || (message->dummy_cycles > 18))
+            {
+                return LL_ERR_INVD_PARAM;
+            }
+        }
+    }
+
+    return LL_OK;
+}
+
 static int32_t hc32_qspi_send_cmd(struct hc32_qspi_bus *qspi_bus, struct rt_qspi_message *message, uint8_t u8Func)
 {
 #ifndef BSP_QSPI_USING_SOFT_CS
@@ -242,26 +311,28 @@ static int32_t hc32_qspi_send_cmd(struct hc32_qspi_bus *qspi_bus, struct rt_qspi
     else
 #endif
     {
-        if ((message->instruction.qspi_lines != 0) && (message->instruction.qspi_lines != 1))
+#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F472)
+#ifndef BSP_QSPI_USING_SOFT_CS
+        if (LL_OK != hc32_qspi_check_direct_comm_param(message, QSPI_DIRECT_COMM_LINE_ONE))
         {
             return LL_ERR_INVD_PARAM;
         }
-        if ((message->address.qspi_lines != 0) && ((message->address.qspi_lines != 1) && (message->address.size != 0)))
+        /* Set standard read mode */
+        QSPI_SetReadMode(QSPI_RD_MD_STD_RD);
+#else
+        if (LL_OK != hc32_qspi_check_direct_comm_param(message, QSPI_DIRECT_COMM_LINE_MULTI))
         {
             return LL_ERR_INVD_PARAM;
         }
-        if ((message->address.size % 8) != 0)
-        {
-            return LL_ERR_INVD_PARAM;
-        }
-        if ((message->qspi_data_lines != 0) && (message->qspi_data_lines != 1))
-        {
-            return LL_ERR_INVD_PARAM;
-        }
-        if ((message->dummy_cycles % 8) != 0)
+        /* Set custom read mode */
+        QSPI_SetReadMode(QSPI_RD_MD_CUSTOM_FAST_RD);
+#endif
+#elif defined (HC32F448)
+        if (LL_OK != hc32_qspi_check_direct_comm_param(message, QSPI_DIRECT_COMM_LINE_MULTI))
         {
             return LL_ERR_INVD_PARAM;
         }
+#endif
     }
 
     return LL_OK;
@@ -279,8 +350,73 @@ static void hc32_qspi_word_to_byte(uint32_t u32Word, uint8_t *pu8Byte, uint8_t u
     while ((u32ByteNum--) != 0UL);
 }
 
-static int32_t hc32_qspi_write_instr(struct hc32_qspi_bus *qspi_bus, uint8_t u8Instr, uint32_t u32InstrLen,
-                                     uint8_t *pu8Addr, uint32_t u32AddrLen, const uint8_t *pu8WriteBuf, uint32_t u32BufLen)
+#if defined (HC32F448)
+static rt_uint32_t hc32_qspi_get_dcom_protocol_line(rt_uint8_t protocol_line)
+{
+    rt_uint32_t dcom_protocol_line;
+
+    switch (protocol_line)
+    {
+    case 2:
+        dcom_protocol_line = QSPI_DIRECT_COMM_PROTOCOL_2LINE;
+        break;
+    case 4:
+        dcom_protocol_line = QSPI_DIRECT_COMM_PROTOCOL_4LINE;
+        break;
+    case 1:
+    default:
+        dcom_protocol_line = QSPI_DIRECT_COMM_PROTOCOL_1LINE;
+        break;
+    }
+
+    return dcom_protocol_line;
+}
+#endif
+
+static void hc32_qspi_write_direct_comm_value(rt_uint8_t protocol_line, rt_uint8_t value)
+{
+#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F472)
+    (void)protocol_line;
+    QSPI_WriteDirectCommValue(value);
+#elif defined (HC32F448)
+    QSPI_WriteDirectCommValue(hc32_qspi_get_dcom_protocol_line(protocol_line), value);
+#endif
+}
+
+#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F472)
+#ifdef BSP_QSPI_USING_SOFT_CS
+static void hc32_qspi_set_trans_protocol(uint32_t u32Line)
+{
+    stc_qspi_custom_mode_t stcCustomMode;
+
+    stcCustomMode.u8InstrCode        = 0U;
+    switch (u32Line)
+    {
+    case 2:
+        stcCustomMode.u32InstrProtocol   = QSPI_INSTR_PROTOCOL_2LINE;
+        stcCustomMode.u32AddrProtocol    = QSPI_ADDR_PROTOCOL_2LINE;
+        stcCustomMode.u32DataProtocol    = QSPI_DATA_PROTOCOL_2LINE;
+        break;
+    case 4:
+        stcCustomMode.u32InstrProtocol   = QSPI_INSTR_PROTOCOL_4LINE;
+        stcCustomMode.u32AddrProtocol    = QSPI_ADDR_PROTOCOL_4LINE;
+        stcCustomMode.u32DataProtocol    = QSPI_DATA_PROTOCOL_4LINE;
+        break;
+    case 1:
+    default:
+        stcCustomMode.u32InstrProtocol   = QSPI_INSTR_PROTOCOL_1LINE;
+        stcCustomMode.u32AddrProtocol    = QSPI_ADDR_PROTOCOL_1LINE;
+        stcCustomMode.u32DataProtocol    = QSPI_DATA_PROTOCOL_1LINE;
+        break;
+    }
+    QSPI_CustomReadConfig(&stcCustomMode);
+}
+#endif
+#endif
+
+static int32_t hc32_qspi_write_instr(struct hc32_qspi_bus *qspi_bus, struct rt_qspi_message *message,
+                                     uint8_t u8Instr, uint32_t u32InstrLen, uint8_t *pu8Addr, uint32_t u32AddrLen,
+                                     const uint8_t *pu8WriteBuf, uint32_t u32BufLen)
 {
     uint32_t u32Count;
     int32_t i32Ret = LL_OK;
@@ -290,28 +426,71 @@ static int32_t hc32_qspi_write_instr(struct hc32_qspi_bus *qspi_bus, uint8_t u8I
     uint32_t u32DmaTransSize;
     uint32_t u32TxIndex = 0U;
     rt_uint32_t u32TimeoutCnt;
+    rt_uint32_t src_addr;
 #endif
 
-    QSPI_EnterDirectCommMode();
+#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F472)
+#ifndef BSP_QSPI_USING_SOFT_CS
+    /* Enter direct communication mode */
+    SET_REG32_BIT(CM_QSPI->CR, QSPI_CR_DCOME);
+#endif
+#elif defined (HC32F448)
+    /* Enter direct communication mode */
+    SET_REG32_BIT(CM_QSPI->CR, QSPI_CR_DCOME);
+#endif
     if (0UL != u32InstrLen)
     {
-        QSPI_WriteDirectCommValue(u8Instr);
+#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F472)
+#ifdef BSP_QSPI_USING_SOFT_CS
+        hc32_qspi_set_trans_protocol(message->instruction.qspi_lines);
+        SET_REG32_BIT(CM_QSPI->CR, QSPI_CR_DCOME);
+#endif
+#endif
+        hc32_qspi_write_direct_comm_value(message->instruction.qspi_lines, u8Instr);
+#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F472)
+#ifdef BSP_QSPI_USING_SOFT_CS
+        CLR_REG32_BIT(CM_QSPI->CR, QSPI_CR_DCOME);
+#endif
+#endif
     }
     if ((NULL != pu8Addr) && (0UL != u32AddrLen))
     {
+#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F472)
+#ifdef BSP_QSPI_USING_SOFT_CS
+        hc32_qspi_set_trans_protocol(message->address.qspi_lines);
+        SET_REG32_BIT(CM_QSPI->CR, QSPI_CR_DCOME);
+#endif
+#endif
         for (u32Count = 0UL; u32Count < u32AddrLen; u32Count++)
         {
-            QSPI_WriteDirectCommValue(pu8Addr[u32Count]);
+            hc32_qspi_write_direct_comm_value(message->address.qspi_lines, pu8Addr[u32Count]);
         }
+#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F472)
+#ifdef BSP_QSPI_USING_SOFT_CS
+        CLR_REG32_BIT(CM_QSPI->CR, QSPI_CR_DCOME);
+#endif
+#endif
     }
     if ((NULL != pu8WriteBuf) && (0UL != u32BufLen))
     {
+#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F472)
+#ifdef BSP_QSPI_USING_SOFT_CS
+        hc32_qspi_set_trans_protocol(message->qspi_data_lines);
+        SET_REG32_BIT(CM_QSPI->CR, QSPI_CR_DCOME);
+#endif
+#endif
+
 #ifdef BSP_QSPI_USING_DMA
         qspi_dma = qspi_bus->config->dma_qspi;
         AOS_SetTriggerEventSrc(qspi_dma->trigger_select, qspi_dma->trigger_event);
         /* Config Dma */
         DMA_StructInit(&stcDmaInit);
+#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F472)
         stcDmaInit.u32DataWidth     = DMA_DATAWIDTH_8BIT;
+#elif defined (HC32F448)
+        rt_uint16_t dcom_line = (rt_uint16_t)hc32_qspi_get_dcom_protocol_line(message->qspi_data_lines);
+        stcDmaInit.u32DataWidth     = DMA_DATAWIDTH_16BIT;
+#endif
         stcDmaInit.u32SrcAddrInc    = DMA_SRC_ADDR_INC;
         stcDmaInit.u32DestAddrInc   = DMA_DEST_ADDR_FIX;
         DMA_Init(qspi_dma->Instance, qspi_dma->channel, &stcDmaInit);
@@ -327,8 +506,24 @@ static int32_t hc32_qspi_write_instr(struct hc32_qspi_bus *qspi_bus, uint8_t u8I
                 u32DmaTransSize = u32BufLen;
                 u32BufLen = 0U;
             }
+
+#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F472)
+            src_addr = (rt_uint32_t)&pu8WriteBuf[u32TxIndex];
+#elif defined (HC32F448)
+            if (u32DmaTransSize > qspi_bus->config->dma_tx_buf_size)
+            {
+                LOG_E("qspi dma transmit size over buffer size!");
+                i32Ret = LL_ERR;
+                break;
+            }
+            for (rt_uint32_t i = 0; i < u32DmaTransSize; i++)
+            {
+                qspi_bus->config->dma_tx_buf[i] = (rt_uint16_t)pu8WriteBuf[u32TxIndex + i] | dcom_line;
+            }
+            src_addr = (rt_uint32_t)qspi_bus->config->dma_tx_buf;
+#endif
             DMA_ClearTransCompleteStatus(qspi_dma->Instance, qspi_dma->flag);
-            DMA_SetSrcAddr(qspi_dma->Instance, qspi_dma->channel, (uint32_t)&pu8WriteBuf[u32TxIndex]);
+            DMA_SetSrcAddr(qspi_dma->Instance, qspi_dma->channel, src_addr);
             DMA_SetDestAddr(qspi_dma->Instance, qspi_dma->channel, (uint32_t)&qspi_bus->config->Instance->DCOM);
             DMA_SetTransCount(qspi_dma->Instance, qspi_dma->channel, 1UL);
             DMA_SetBlockSize(qspi_dma->Instance, qspi_dma->channel, (uint16_t)u32DmaTransSize);
@@ -352,17 +547,33 @@ static int32_t hc32_qspi_write_instr(struct hc32_qspi_bus *qspi_bus, uint8_t u8I
 #else
         for (u32Count = 0UL; u32Count < u32BufLen; u32Count++)
         {
-            QSPI_WriteDirectCommValue(pu8WriteBuf[u32Count]);
+            hc32_qspi_write_direct_comm_value(message->qspi_data_lines, pu8WriteBuf[u32Count]);
         }
+#endif
+
+#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F472)
+#ifdef BSP_QSPI_USING_SOFT_CS
+        /* Exit direct communication mode */
+        CLR_REG32_BIT(CM_QSPI->CR, QSPI_CR_DCOME);
+#endif
 #endif
     }
-    QSPI_ExitDirectCommMode();
+#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F472)
+#ifndef BSP_QSPI_USING_SOFT_CS
+    /* Exit direct communication mode */
+    CLR_REG32_BIT(CM_QSPI->CR, QSPI_CR_DCOME);
+#endif
+#elif defined (HC32F448)
+    /* Exit direct communication mode */
+    CLR_REG32_BIT(CM_QSPI->CR, QSPI_CR_DCOME);
+#endif
 
     return i32Ret;
 }
 
-static int32_t hc32_qspi_read_instr(struct hc32_qspi_bus *qspi_bus, uint8_t u8Instr, uint32_t u32InstrLen,
-                                    uint8_t *pu8Addr, uint32_t u32AddrLen, uint8_t *pu8ReadBuf, uint32_t u32BufLen)
+static int32_t hc32_qspi_read_instr(struct hc32_qspi_bus *qspi_bus, struct rt_qspi_message *message,
+                                    uint8_t u8Instr, uint32_t u32InstrLen, uint8_t *pu8Addr, uint32_t u32AddrLen,
+                                    uint8_t *pu8ReadBuf, uint32_t u32BufLen)
 {
     uint32_t u32Count;
     int32_t i32Ret = LL_OK;
@@ -374,20 +585,57 @@ static int32_t hc32_qspi_read_instr(struct hc32_qspi_bus *qspi_bus, uint8_t u8In
     rt_uint32_t u32TimeoutCnt;
 #endif
 
-    QSPI_EnterDirectCommMode();
+#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F472)
+#ifndef BSP_QSPI_USING_SOFT_CS
+    /* Enter direct communication mode */
+    SET_REG32_BIT(CM_QSPI->CR, QSPI_CR_DCOME);
+#endif
+#elif defined (HC32F448)
+    /* Enter direct communication mode */
+    SET_REG32_BIT(CM_QSPI->CR, QSPI_CR_DCOME);
+#endif
     if (0UL != u32InstrLen)
     {
-        QSPI_WriteDirectCommValue(u8Instr);
+#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F472)
+#ifdef BSP_QSPI_USING_SOFT_CS
+        hc32_qspi_set_trans_protocol(message->instruction.qspi_lines);
+        SET_REG32_BIT(CM_QSPI->CR, QSPI_CR_DCOME);
+#endif
+#endif
+        hc32_qspi_write_direct_comm_value(message->instruction.qspi_lines, u8Instr);
+#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F472)
+#ifdef BSP_QSPI_USING_SOFT_CS
+        CLR_REG32_BIT(CM_QSPI->CR, QSPI_CR_DCOME);
+#endif
+#endif
     }
     if ((NULL != pu8Addr) && (0UL != u32AddrLen))
     {
+#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F472)
+#ifdef BSP_QSPI_USING_SOFT_CS
+        hc32_qspi_set_trans_protocol(message->address.qspi_lines);
+        SET_REG32_BIT(CM_QSPI->CR, QSPI_CR_DCOME);
+#endif
+#endif
         for (u32Count = 0UL; u32Count < u32AddrLen; u32Count++)
         {
-            QSPI_WriteDirectCommValue(pu8Addr[u32Count]);
+            hc32_qspi_write_direct_comm_value(message->address.qspi_lines, pu8Addr[u32Count]);
         }
+#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F472)
+#ifdef BSP_QSPI_USING_SOFT_CS
+        CLR_REG32_BIT(CM_QSPI->CR, QSPI_CR_DCOME);
+#endif
+#endif
     }
     if ((NULL != pu8ReadBuf) && (0UL != u32BufLen))
     {
+#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F472)
+#ifdef BSP_QSPI_USING_SOFT_CS
+        hc32_qspi_set_trans_protocol(message->qspi_data_lines);
+        SET_REG32_BIT(CM_QSPI->CR, QSPI_CR_DCOME);
+#endif
+#endif
+
 #ifdef BSP_QSPI_USING_DMA
         qspi_dma = qspi_bus->config->dma_qspi;
         AOS_SetTriggerEventSrc(qspi_dma->trigger_select, qspi_dma->trigger_event);
@@ -436,9 +684,24 @@ static int32_t hc32_qspi_read_instr(struct hc32_qspi_bus *qspi_bus, uint8_t u8In
         {
             pu8ReadBuf[u32Count] = QSPI_ReadDirectCommValue();
         }
+#endif
+
+#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F472)
+#ifdef BSP_QSPI_USING_SOFT_CS
+        /* Exit direct communication mode */
+        CLR_REG32_BIT(CM_QSPI->CR, QSPI_CR_DCOME);
+#endif
 #endif
     }
-    QSPI_ExitDirectCommMode();
+#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F472)
+#ifndef BSP_QSPI_USING_SOFT_CS
+    /* Exit direct communication mode */
+    CLR_REG32_BIT(CM_QSPI->CR, QSPI_CR_DCOME);
+#endif
+#elif defined (HC32F448)
+    /* Exit direct communication mode */
+    CLR_REG32_BIT(CM_QSPI->CR, QSPI_CR_DCOME);
+#endif
 
     return i32Ret;
 }
@@ -450,8 +713,8 @@ static int32_t hc32_qspi_write(struct hc32_qspi_bus *qspi_bus, struct rt_qspi_me
     rt_int32_t length = message->parent.length;
     uint32_t u32Addr = message->address.content;
     uint8_t u8Instr = message->instruction.content;
-    uint8_t u8AddrBuf[10];
-    uint32_t u32AddrLen = 0U;
+    uint8_t u8AddrBuf[32];
+    uint32_t u32AddrLen = 0U, u32DummyLen = 0U;
     uint32_t u32InstrLen = 0U;
     int32_t i32Ret;
 
@@ -467,12 +730,16 @@ static int32_t hc32_qspi_write(struct hc32_qspi_bus *qspi_bus, struct rt_qspi_me
         u32AddrLen = message->address.size / 8;
         hc32_qspi_word_to_byte(u32Addr, u8AddrBuf, u32AddrLen);
     }
-    for (u32Count = 0; u32Count < (message->dummy_cycles / 8); u32Count++)
+    if (message->dummy_cycles != 0)
     {
-        u8AddrBuf[u32AddrLen] = 0xFF;
-        u32AddrLen += 1;
+        u32DummyLen = message->dummy_cycles * message->address.qspi_lines / 8;
+        for (u32Count = 0; u32Count < u32DummyLen; u32Count++)
+        {
+            u8AddrBuf[u32AddrLen] = 0xFF;
+            u32AddrLen += 1;
+        }
     }
-    i32Ret = hc32_qspi_write_instr(qspi_bus, u8Instr, u32InstrLen, u8AddrBuf, u32AddrLen, tx_buf, length);
+    i32Ret = hc32_qspi_write_instr(qspi_bus, message, u8Instr, u32InstrLen, u8AddrBuf, u32AddrLen, tx_buf, length);
 
     return i32Ret;
 }
@@ -485,8 +752,8 @@ static int32_t hc32_qspi_read(struct hc32_qspi_bus *qspi_bus, struct rt_qspi_mes
     rt_int32_t length = message->parent.length;
     uint32_t u32Addr = message->address.content;
     uint8_t u8Instr = message->instruction.content;
-    uint8_t u8AddrBuf[10];
-    uint32_t u32AddrLen = 0U;
+    uint8_t u8AddrBuf[32];
+    uint32_t u32AddrLen = 0U, u32DummyLen = 0U;
     uint32_t u32InstrLen = 0U;
     int32_t i32Ret = LL_OK;
 
@@ -618,12 +885,16 @@ static int32_t hc32_qspi_read(struct hc32_qspi_bus *qspi_bus, struct rt_qspi_mes
             u32AddrLen = message->address.size / 8;
             hc32_qspi_word_to_byte(u32Addr, u8AddrBuf, u32AddrLen);
         }
-        for (u32Count = 0; u32Count < (message->dummy_cycles / 8); u32Count++)
+        if (message->dummy_cycles != 0)
         {
-            u8AddrBuf[u32AddrLen] = 0xFF;
-            u32AddrLen += 1;
+            u32DummyLen = message->dummy_cycles * message->address.qspi_lines / 8;
+            for (u32Count = 0; u32Count < u32DummyLen; u32Count++)
+            {
+                u8AddrBuf[u32AddrLen] = 0xFF;
+                u32AddrLen += 1;
+            }
         }
-        i32Ret = hc32_qspi_read_instr(qspi_bus, u8Instr, u32InstrLen, u8AddrBuf, u32AddrLen, rx_buf, length);
+        i32Ret = hc32_qspi_read_instr(qspi_bus, message, u8Instr, u32InstrLen, u8AddrBuf, u32AddrLen, rx_buf, length);
     }
 
     return i32Ret;
@@ -733,6 +1004,13 @@ static void qspi_err_irq_handler(void)
     rt_interrupt_leave();
 }
 
+#if defined (HC32F448) || defined (HC32F472)
+void QSPI_Handler(void)
+{
+    qspi_err_irq_handler();
+}
+#endif
+
 /**
   * @brief  This function attach device to QSPI bus.
   * @param  bus_name                    QSPI bus name
@@ -802,6 +1080,10 @@ static void hc32_get_qspi_info(void)
 #ifdef BSP_QSPI_USING_DMA
     static struct dma_config qspi_dma = QSPI_DMA_CONFIG;
     qspi_config.dma_qspi    = &qspi_dma;
+#if defined (HC32F448)
+    qspi_config.dma_tx_buf_size = QSPI_DMA_TX_BUFSIZE;
+    qspi_config.dma_tx_buf = rt_malloc(qspi_config.dma_tx_buf_size << 1);
+#endif
 #endif
     qspi_bus_obj.config = &qspi_config;
 }
@@ -810,7 +1092,12 @@ static int rt_hw_qspi_bus_init(void)
 {
     hc32_get_qspi_info();
     /* register the handle */
+#if defined (HC32F460) || defined (HC32F4A0)
     hc32_install_irq_handler(&qspi_bus_obj.config->err_irq.irq_config, qspi_bus_obj.config->err_irq.irq_callback, RT_FALSE);
+#elif defined (HC32F448) || defined (HC32F472)
+    hc32_install_independ_irq_handler(&qspi_bus_obj.config->err_irq.irq_config, RT_FALSE);
+#endif
+
     return hc32_qspi_register_bus(&qspi_bus_obj, "qspi1");
 }
 INIT_BOARD_EXPORT(rt_hw_qspi_bus_init);

bsp/hc32/libraries/hc32_drivers/drv_qspi.h

@@ -39,6 +39,10 @@ struct hc32_qspi_config
     struct hc32_qspi_irq_config err_irq;
 #ifdef BSP_QSPI_USING_DMA
     struct dma_config           *dma_qspi;
+#if defined (HC32F448)
+    rt_uint16_t                 *dma_tx_buf;
+    rt_uint16_t                 dma_tx_buf_size;    /* unit: half-word, DMA data width of QSPI transmitting is 16bit */
+#endif
 #endif
 };
 

bsp/hc32/libraries/hc32_drivers/drv_spi.c

@@ -8,6 +8,7 @@
  * 2022-04-28     CDT          first version
  * 2023-09-30     CDT          Delete dma transmit interrupt
  * 2024-02-20     CDT          support HC32F448
+ * 2024-04-16     CDT          support HC32F472
  */
 
 /*******************************************************************************
@@ -293,7 +294,7 @@ static rt_err_t hc32_spi_init(struct hc32_spi *spi_drv, struct rt_spi_configurat
 #endif
 
     /* Enable error interrupt */
-#if defined (HC32F448)
+#if defined (HC32F448) || defined (HC32F472)
     INTC_IntSrcCmd(spi_drv->config->err_irq.irq_config.int_src, ENABLE);
 #endif
     NVIC_EnableIRQ(spi_drv->config->err_irq.irq_config.irq_num);
@@ -311,7 +312,7 @@ static void hc32_spi_enable(CM_SPI_TypeDef *SPIx)
     {
         SPI_Cmd(SPIx, ENABLE);
     }
-#elif defined (HC32F448)
+#elif defined (HC32F448) || defined (HC32F472)
     if ((SPIx->CR & SPI_CR_SPE) != SPI_CR_SPE)
     {
         SPI_Cmd(SPIx, ENABLE);
@@ -332,7 +333,7 @@ static void hc32_spi_set_trans_mode(CM_SPI_TypeDef *SPIx, uint32_t u32Mode)
     {
         CLR_REG32_BIT(SPIx->CR1, SPI_CR1_TXMDS);
     }
-#elif defined (HC32F448)
+#elif defined (HC32F448) || defined (HC32F472)
     if (SPI_SEND_ONLY == u32Mode)
     {
         SET_REG32_BIT(SPIx->CR, SPI_CR_TXMDS);
@@ -351,7 +352,7 @@ static uint32_t hc32_spi_get_trans_mode(CM_SPI_TypeDef *SPIx)
 {
 #if defined (HC32F460) || defined (HC32F4A0)
     return READ_REG32_BIT(SPIx->CR1, SPI_CR1_TXMDS);
-#elif defined (HC32F448)
+#elif defined (HC32F448) || defined (HC32F472)
     return READ_REG32_BIT(SPIx->CR, SPI_CR_TXMDS);
 #else
 #error "Please select first the target HC32xxxx device used in your application."
@@ -679,7 +680,7 @@ rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name,
 
 static void hc32_spi_err_irq_handle(struct hc32_spi *spi)
 {
-#if defined (HC32F448)
+#if defined (HC32F448) ||defined (HC32F472)
 #define SPI_FLAG_OVERLOAD       SPI_FLAG_OVERRUN
 #define SPI_FLAG_UNDERLOAD      SPI_FLAG_UNDERRUN
 #endif
@@ -715,12 +716,12 @@ static void hc32_spi1_err_irq_handler(void)
     rt_interrupt_leave();
 }
 
-#if defined (HC32F448)
+#if defined (HC32F448) ||defined (HC32F472)
 void SPI1_Handler(void)
 {
     hc32_spi1_err_irq_handler();
 }
-#endif /* HC32F448 */
+#endif /* HC32F448, HC32F472 */
 
 #endif /* BSP_USING_SPI1 */
 
@@ -733,12 +734,12 @@ static void hc32_spi2_err_irq_handler(void)
     /* leave interrupt */
     rt_interrupt_leave();
 }
-#if defined (HC32F448)
+#if defined (HC32F448) ||defined (HC32F472)
 void SPI2_Handler(void)
 {
     hc32_spi2_err_irq_handler();
 }
-#endif /* HC32F448 */
+#endif /* HC32F448, HC32F472 */
 
 #endif /* BSP_USING_SPI2 */
 
@@ -751,12 +752,12 @@ static void hc32_spi3_err_irq_handler(void)
     /* leave interrupt */
     rt_interrupt_leave();
 }
-#if defined (HC32F448)
+#if defined (HC32F448) ||defined (HC32F472)
 void SPI3_Handler(void)
 {
     hc32_spi3_err_irq_handler();
 }
-#endif /* HC32F448 */
+#endif /* HC32F448, HC32F472 */
 
 #endif /* BSP_USING_SPI3 */
 

bsp/hc32/libraries/hc32_drivers/drv_usart.c

@@ -7,6 +7,7 @@
  * Date           Author       Notes
  * 2022-04-28     CDT          first version
  * 2023-10-09     CDT          support HC32F448
+ * 2024-04-15     CDT          support HC32F472
  */
 
 /*******************************************************************************
@@ -46,10 +47,8 @@
 
 #if defined (HC32F460)
     #define FCG_USART_CLK               FCG_Fcg1PeriphClockCmd
-
-#elif defined (HC32F4A0) || defined (HC32F448)
+#elif defined (HC32F4A0) || defined (HC32F448) || defined (HC32F472)
     #define FCG_USART_CLK               FCG_Fcg3PeriphClockCmd
-
 #endif
 
 #define FCG_TMR0_CLK                    FCG_Fcg2PeriphClockCmd
@@ -162,7 +161,7 @@ static rt_err_t hc32_configure(struct rt_serial_device *serial, struct serial_co
 #elif defined (HC32F460)
     if ((CM_USART1 == uart->config->Instance) || (CM_USART2 == uart->config->Instance) || \
             (CM_USART3 == uart->config->Instance) || (CM_USART4 == uart->config->Instance))
-#elif defined (HC32F448)
+#elif defined (HC32F448) || defined (HC32F472)
     if ((CM_USART1 == uart->config->Instance) || (CM_USART2 == uart->config->Instance) || \
             (CM_USART4 == uart->config->Instance) || (CM_USART5 == uart->config->Instance))
 #endif
@@ -220,7 +219,7 @@ static rt_err_t hc32_configure(struct rt_serial_device *serial, struct serial_co
     {
         uart_init.u32FirstBit = USART_FIRST_BIT_MSB;
     }
-#if defined (HC32F4A0) || defined (HC32F448)
+#if defined (HC32F4A0) || defined (HC32F448) || defined (HC32F472)
     switch (cfg->flowcontrol)
     {
     case RT_SERIAL_FLOWCONTROL_NONE:
@@ -271,7 +270,7 @@ static rt_err_t hc32_configure(struct rt_serial_device *serial, struct serial_co
     /* Enable error interrupt */
 #if defined (HC32F460) || defined (HC32F4A0)
     NVIC_EnableIRQ(uart->config->rxerr_irq.irq_config.irq_num);
-#elif defined (HC32F448)
+#elif defined (HC32F448) || defined (HC32F472)
     INTC_IntSrcCmd(uart->config->tx_int_src, ENABLE);
     INTC_IntSrcCmd(uart->config->rx_int_src, DISABLE);
     INTC_IntSrcCmd(uart->config->rxerr_int_src, ENABLE);
@@ -300,7 +299,7 @@ static rt_err_t hc32_control(struct rt_serial_device *serial, int cmd, void *arg
 #if defined (HC32F460) || defined (HC32F4A0)
             NVIC_DisableIRQ(uart->config->rx_irq.irq_config.irq_num);
             INTC_IrqSignOut(uart->config->rx_irq.irq_config.irq_num);
-#elif defined (HC32F448)
+#elif defined (HC32F448) || defined (HC32F472)
             INTC_IntSrcCmd(uart->config->rx_int_src, DISABLE);
 #endif
         }
@@ -310,7 +309,7 @@ static rt_err_t hc32_control(struct rt_serial_device *serial, int cmd, void *arg
             NVIC_DisableIRQ(uart->config->tx_irq.irq_config.irq_num);
             USART_FuncCmd(uart->config->Instance, USART_INT_TX_EMPTY, DISABLE);
             INTC_IrqSignOut(uart->config->tx_irq.irq_config.irq_num);
-#elif defined (HC32F448)
+#elif defined (HC32F448) || defined (HC32F472)
             USART_FuncCmd(uart->config->Instance, USART_INT_TX_EMPTY, DISABLE);
 #endif
         }
@@ -334,14 +333,14 @@ static rt_err_t hc32_control(struct rt_serial_device *serial, int cmd, void *arg
             hc32_install_irq_handler(&uart->config->rx_irq.irq_config, uart->config->rx_irq.irq_callback, RT_TRUE);
             USART_FuncCmd(uart->config->Instance, USART_INT_RX, ENABLE);
         }
-        else
+        else if (RT_DEVICE_FLAG_INT_TX == ctrl_arg)
         {
             INTC_IrqSignOut(uart->config->tx_irq.irq_config.irq_num);
             hc32_install_irq_handler(&uart->config->tx_irq.irq_config, uart->config->tx_irq.irq_callback, RT_TRUE);
             USART_FuncCmd(uart->config->Instance, USART_TX, DISABLE);
             USART_FuncCmd(uart->config->Instance, USART_TX | USART_INT_TX_EMPTY, ENABLE);
         }
-#elif defined (HC32F448)
+#elif defined (HC32F448) || defined (HC32F472)
         /* NVIC config */
         if (RT_DEVICE_FLAG_INT_RX == ctrl_arg)
         {
@@ -349,7 +348,7 @@ static rt_err_t hc32_control(struct rt_serial_device *serial, int cmd, void *arg
             INTC_IntSrcCmd(uart->config->rx_int_src, ENABLE);
             USART_FuncCmd(uart->config->Instance, USART_INT_RX, ENABLE);
         }
-        else
+        else if (RT_DEVICE_FLAG_INT_TX == ctrl_arg)
         {
             USART_FuncCmd(uart->config->Instance, USART_TX | USART_INT_TX_EMPTY, ENABLE);
         }
@@ -504,7 +503,7 @@ static void hc32_uart_rx_timeout(struct rt_serial_device *serial)
     {
         RT_ASSERT(TMR0_CH_B == ch);
     }
-#elif defined(HC32F4A0)
+#elif defined (HC32F4A0)
     if ((CM_USART1 == uart->config->Instance) || (CM_USART6 == uart->config->Instance))
     {
         RT_ASSERT(TMR0_CH_A == ch);
@@ -513,7 +512,7 @@ static void hc32_uart_rx_timeout(struct rt_serial_device *serial)
     {
         RT_ASSERT(TMR0_CH_B == ch);
     }
-#elif defined (HC32F448)
+#elif defined (HC32F448) || defined (HC32F472)
     if ((CM_USART1 == uart->config->Instance) || (CM_USART4 == uart->config->Instance))
     {
         RT_ASSERT(TMR0_CH_A == ch);
@@ -588,7 +587,7 @@ static void hc32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag)
         RT_ASSERT(RT_NULL != uart->config->dma_rx->Instance);
         RT_ASSERT(RT_NULL != rx_fifo);
 
-#if defined (HC32F448)
+#if defined (HC32F448) || defined (HC32F472)
         INTC_IntSrcCmd(uart->config->rx_int_src, DISABLE);
 #endif
 
@@ -748,7 +747,7 @@ static void hc32_uart_tc_irq_handler(struct hc32_uart *uart)
 #endif
 #endif
 
-#if defined (HC32F448)
+#if defined (HC32F448) || defined (HC32F472)
 static void hc32_usart_handler(struct hc32_uart *uart)
 {
     RT_ASSERT(RT_NULL != uart);
@@ -758,7 +757,10 @@ static void hc32_usart_handler(struct hc32_uart *uart)
             (ENABLE == USART_GetFuncState(uart->config->Instance, USART_RX_TIMEOUT)) && \
             (ENABLE == INTC_GetIntSrcState(uart->config->rxto_int_src)))
     {
+#if defined (BSP_UART1_RX_USING_DMA) || defined (BSP_UART2_RX_USING_DMA) || \
+    defined (BSP_UART4_RX_USING_DMA) || defined (BSP_UART5_RX_USING_DMA)
         hc32_uart_rxto_irq_handler(uart);
+#endif
     }
 #endif
 
@@ -835,7 +837,7 @@ static void hc32_uart1_tc_irq_handler(void)
     rt_interrupt_leave();
 }
 
-#if defined (HC32F448)
+#if defined (HC32F448) || defined (HC32F472)
 void USART1_TxComplete_Handler(void)
 {
     hc32_uart1_tc_irq_handler();
@@ -870,7 +872,7 @@ static void hc32_uart1_dma_rx_irq_handler(void)
 #endif /* BSP_UART1_RX_USING_DMA */
 #endif /* RT_SERIAL_USING_DMA */
 
-#if defined (HC32F448)
+#if defined (HC32F448) || defined (HC32F472)
 void USART1_Handler(void)
 {
     /* enter interrupt */
@@ -881,7 +883,7 @@ void USART1_Handler(void)
     /* leave interrupt */
     rt_interrupt_leave();
 }
-#endif /* HC32F448 */
+#endif /* HC32F448, HC32F472 */
 #endif /* BSP_USING_UART1 */
 
 #if defined (BSP_USING_UART2)
@@ -933,7 +935,7 @@ static void hc32_uart2_tc_irq_handler(void)
     rt_interrupt_leave();
 }
 
-#if defined (HC32F448)
+#if defined (HC32F448) || defined (HC32F472)
 void USART2_TxComplete_Handler(void)
 {
     hc32_uart2_tc_irq_handler();
@@ -968,7 +970,7 @@ static void hc32_uart2_dma_rx_irq_handler(void)
 #endif /* BSP_UART2_RX_USING_DMA */
 #endif /* RT_SERIAL_USING_DMA */
 
-#if defined (HC32F448)
+#if defined (HC32F448) || defined (HC32F472)
 void USART2_Handler(void)
 {
     /* enter interrupt */
@@ -979,7 +981,7 @@ void USART2_Handler(void)
     /* leave interrupt */
     rt_interrupt_leave();
 }
-#endif /* HC32F448 */
+#endif /* HC32F448, HC32F472 */
 #endif /* BSP_USING_UART2 */
 
 #if defined (BSP_USING_UART3)
@@ -1058,7 +1060,7 @@ static void hc32_uart3_dma_rx_irq_handler(void)
 #endif /* RT_SERIAL_USING_DMA */
 #endif /* HC32F460, HC32F4A0 */
 
-#if defined (HC32F448)
+#if defined (HC32F448) || defined (HC32F472)
 void USART3_Handler(void)
 {
     /* enter interrupt */
@@ -1069,7 +1071,7 @@ void USART3_Handler(void)
     /* leave interrupt */
     rt_interrupt_leave();
 }
-#endif /* HC32F448 */
+#endif /* HC32F448, HC32F472 */
 #endif /* BSP_USING_UART3 */
 
 #if defined (BSP_USING_UART4)
@@ -1121,12 +1123,12 @@ static void hc32_uart4_tc_irq_handler(void)
     rt_interrupt_leave();
 }
 
-#if defined (HC32F448)
+#if defined (HC32F448) || defined (HC32F472)
 void USART4_TxComplete_Handler(void)
 {
     hc32_uart4_tc_irq_handler();
 }
-#endif /* HC32F448 */
+#endif /* HC32F448, HC32F472 */
 #endif /* BSP_UART4_TX_USING_DMA */
 
 #if defined (BSP_UART4_RX_USING_DMA)
@@ -1156,7 +1158,7 @@ static void hc32_uart4_dma_rx_irq_handler(void)
 #endif /* BSP_UART4_RX_USING_DMA */
 #endif /* RT_SERIAL_USING_DMA */
 
-#if defined (HC32F448)
+#if defined (HC32F448) || defined (HC32F472)
 void USART4_Handler(void)
 {
     /* enter interrupt */
@@ -1167,7 +1169,7 @@ void USART4_Handler(void)
     /* leave interrupt */
     rt_interrupt_leave();
 }
-#endif /* HC32F448 */
+#endif /* HC32F448, HC32F472 */
 #endif /* BSP_USING_UART4 */
 
 #if defined (BSP_USING_UART5)
@@ -1206,7 +1208,7 @@ static void hc32_uart5_rxerr_irq_handler(void)
 }
 #endif /* HC32F460, HC32F4A0 */
 
-#if defined (HC32F448)
+#if defined (HC32F448) || defined (HC32F472)
 #if defined (RT_SERIAL_USING_DMA)
 #if defined (BSP_UART5_TX_USING_DMA)
 static void hc32_uart5_tc_irq_handler(void)
@@ -1250,7 +1252,7 @@ void USART5_Handler(void)
     /* leave interrupt */
     rt_interrupt_leave();
 }
-#endif /* HC32F448 */
+#endif /* HC32F448, HC32F472 */
 #endif /* BSP_USING_UART5 */
 
 #if defined (BSP_USING_UART6)
@@ -1302,7 +1304,7 @@ static void hc32_uart6_tc_irq_handler(void)
 }
 #endif /* BSP_UART6_TX_USING_DMA */
 
-#if defined(BSP_UART6_RX_USING_DMA)
+#if defined (BSP_UART6_RX_USING_DMA)
 static void hc32_uart6_rxto_irq_handler(void)
 {
     /* enter interrupt */
@@ -1328,7 +1330,7 @@ static void hc32_uart6_dma_rx_irq_handler(void)
 #endif /* RT_SERIAL_USING_DMA */
 #endif /* HC32F460, HC32F4A0 */
 
-#if defined (HC32F448)
+#if defined (HC32F448) || defined (HC32F472)
 void USART6_Handler(void)
 {
     /* enter interrupt */
@@ -1339,7 +1341,7 @@ void USART6_Handler(void)
     /* leave interrupt */
     rt_interrupt_leave();
 }
-#endif /* HC32F448 */
+#endif /* HC32F448, HC32F472 */
 #endif /* BSP_USING_UART6 */
 
 #if defined (BSP_USING_UART7)
@@ -1577,7 +1579,7 @@ static void hc32_uart_get_dma_info(void)
 
 #ifdef BSP_USING_UART3
     uart_obj[UART3_INDEX].uart_dma_flag = 0;
-#if defined (HC32F460) || defined (HC32F4A0)
+#if defined (HC32F460)
 #ifdef BSP_UART3_RX_USING_DMA
     uart_obj[UART3_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
     static struct dma_config uart3_dma_rx = UART3_DMA_RX_CONFIG;
@@ -1605,7 +1607,7 @@ static void hc32_uart_get_dma_info(void)
     static struct dma_config uart4_dma_rx = UART4_DMA_RX_CONFIG;
     static struct hc32_uart_rxto uart4_rx_timeout = UART4_RXTO_CONFIG;
     uart4_dma_rx.irq_callback = hc32_uart4_dma_rx_irq_handler;
-#if defined (HC32F460) || defined (HC32F4A0)
+#if defined (HC32F460)
     uart4_rx_timeout.irq_callback = hc32_uart4_rxto_irq_handler;
 #endif
     uart_config[UART4_INDEX].rx_timeout = &uart4_rx_timeout;
@@ -1623,7 +1625,7 @@ static void hc32_uart_get_dma_info(void)
 
 #ifdef BSP_USING_UART5
     uart_obj[UART5_INDEX].uart_dma_flag = 0;
-#if defined (HC32F448)
+#if defined (HC32F448) || defined (HC32F472)
 #ifdef BSP_UART5_RX_USING_DMA
     uart_obj[UART5_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
     static struct dma_config uart5_dma_rx = UART5_DMA_RX_CONFIG;
@@ -1645,7 +1647,7 @@ static void hc32_uart_get_dma_info(void)
 
 #ifdef BSP_USING_UART6
     uart_obj[UART6_INDEX].uart_dma_flag = 0;
-#if defined (HC32F460) || defined (HC32F4A0)
+#if defined (HC32F4A0)
 #ifdef BSP_UART6_RX_USING_DMA
     uart_obj[UART6_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
     static struct dma_config uart6_dma_rx = UART6_DMA_RX_CONFIG;
@@ -1668,6 +1670,7 @@ static void hc32_uart_get_dma_info(void)
 
 #ifdef BSP_USING_UART7
     uart_obj[UART7_INDEX].uart_dma_flag = 0;
+#if defined (HC32F4A0)
 #ifdef BSP_UART7_RX_USING_DMA
     uart_obj[UART7_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
     static struct dma_config uart7_dma_rx = UART7_DMA_RX_CONFIG;
@@ -1686,6 +1689,7 @@ static void hc32_uart_get_dma_info(void)
     uart_config[UART7_INDEX].tc_irq = &uart7_tc_irq;
 #endif
 #endif
+#endif
 
 #ifdef BSP_USING_UART8
     uart_obj[UART8_INDEX].uart_dma_flag = 0;

bsp/hc32/libraries/hc32_drivers/drv_usart.h

@@ -57,7 +57,7 @@ struct hc32_uart_config
     struct hc32_uart_irq_config rxerr_irq;
     struct hc32_uart_irq_config rx_irq;
     struct hc32_uart_irq_config tx_irq;
-#elif defined (HC32F448)
+#elif defined (HC32F448) || defined (HC32F472)
     IRQn_Type                   irq_num;
     en_int_src_t                rxerr_int_src;
     en_int_src_t                tx_int_src;

bsp/hc32/libraries/hc32_drivers/drv_usart_v2.c

@@ -7,6 +7,7 @@
  * Date           Author       Notes
  * 2022-04-28     CDT          first version
  * 2024-02-06     CDT          support HC32F448
+ * 2024-04-15     CDT          support HC32F472
  */
 
 /*******************************************************************************
@@ -47,7 +48,7 @@
 #if defined (HC32F460)
     #define FCG_USART_CLK               FCG_Fcg1PeriphClockCmd
 
-#elif defined(HC32F4A0) || defined (HC32F448)
+#elif defined (HC32F4A0) || defined (HC32F448) || defined (HC32F472)
     #define FCG_USART_CLK               FCG_Fcg3PeriphClockCmd
 
 #endif
@@ -156,13 +157,13 @@ static rt_err_t hc32_configure(struct rt_serial_device *serial, struct serial_co
     uart_init.u32OverSampleBit = USART_OVER_SAMPLE_8BIT;
     uart_init.u32Baudrate = cfg->baud_rate;
     uart_init.u32ClockSrc = USART_CLK_SRC_INTERNCLK;
-#if defined(HC32F4A0)
+#if defined (HC32F4A0)
     if ((CM_USART1 == uart->config->Instance) || (CM_USART2 == uart->config->Instance) || \
             (CM_USART6 == uart->config->Instance) || (CM_USART7 == uart->config->Instance))
 #elif defined (HC32F460)
     if ((CM_USART1 == uart->config->Instance) || (CM_USART2 == uart->config->Instance) || \
             (CM_USART3 == uart->config->Instance) || (CM_USART4 == uart->config->Instance))
-#elif defined (HC32F448)
+#elif defined (HC32F448) || defined (HC32F472)
     if ((CM_USART1 == uart->config->Instance) || (CM_USART2 == uart->config->Instance) || \
             (CM_USART4 == uart->config->Instance) || (CM_USART5 == uart->config->Instance))
 #endif
@@ -220,7 +221,7 @@ static rt_err_t hc32_configure(struct rt_serial_device *serial, struct serial_co
     {
         uart_init.u32FirstBit = USART_FIRST_BIT_MSB;
     }
-#if defined (HC32F4A0) || defined (HC32F448)
+#if defined (HC32F4A0) || defined (HC32F448) || defined (HC32F472)
     switch (cfg->flowcontrol)
     {
     case RT_SERIAL_FLOWCONTROL_NONE:
@@ -268,7 +269,7 @@ static rt_err_t hc32_configure(struct rt_serial_device *serial, struct serial_co
     /* Enable error interrupt */
 #if defined (HC32F460) || defined (HC32F4A0)
     NVIC_EnableIRQ(uart->config->rxerr_irq.irq_config.irq_num);
-#elif defined (HC32F448)
+#elif defined (HC32F448) || defined (HC32F472)
     INTC_IntSrcCmd(uart->config->tx_int_src, ENABLE);
     INTC_IntSrcCmd(uart->config->rx_int_src, DISABLE);
     INTC_IntSrcCmd(uart->config->rxerr_int_src, ENABLE);
@@ -321,7 +322,7 @@ static rt_err_t hc32_control(struct rt_serial_device *serial, int cmd, void *arg
 #if defined (HC32F460) || defined (HC32F4A0)
             NVIC_DisableIRQ(uart->config->rx_irq.irq_config.irq_num);
             INTC_IrqSignOut(uart->config->rx_irq.irq_config.irq_num);
-#elif defined (HC32F448)
+#elif defined (HC32F448) || defined (HC32F472)
             INTC_IntSrcCmd(uart->config->rx_int_src, DISABLE);
 #endif
         }
@@ -333,7 +334,7 @@ static rt_err_t hc32_control(struct rt_serial_device *serial, int cmd, void *arg
             USART_FuncCmd(uart->config->Instance, (USART_INT_TX_EMPTY | USART_INT_TX_CPLT), DISABLE);
             INTC_IrqSignOut(uart->config->tx_irq.irq_config.irq_num);
             INTC_IrqSignOut(uart->config->tc_irq.irq_config.irq_num);
-#elif defined (HC32F448)
+#elif defined (HC32F448) || defined (HC32F472)
             NVIC_DisableIRQ(uart->config->tc_irq.irq_config.irq_num);
             INTC_IrqSignOut(uart->config->tc_irq.irq_config.irq_num);
             USART_FuncCmd(uart->config->Instance, (USART_INT_TX_EMPTY | USART_INT_TX_CPLT), DISABLE);
@@ -359,7 +360,7 @@ static rt_err_t hc32_control(struct rt_serial_device *serial, int cmd, void *arg
             hc32_install_irq_handler(&uart->config->rx_irq.irq_config, uart->config->rx_irq.irq_callback, RT_TRUE);
             USART_FuncCmd(uart->config->Instance, USART_INT_RX, ENABLE);
         }
-        else
+        else if (RT_DEVICE_FLAG_INT_TX == ctrl_arg)
         {
             INTC_IrqSignOut(uart->config->tx_irq.irq_config.irq_num);
             INTC_IrqSignOut(uart->config->tc_irq.irq_config.irq_num);
@@ -368,7 +369,7 @@ static rt_err_t hc32_control(struct rt_serial_device *serial, int cmd, void *arg
             USART_FuncCmd(uart->config->Instance, USART_TX, DISABLE);
             USART_FuncCmd(uart->config->Instance, USART_TX | USART_INT_TX_EMPTY, ENABLE);
         }
-#elif defined (HC32F448)
+#elif defined (HC32F448) || defined (HC32F472)
         /* NVIC config */
         if (RT_DEVICE_FLAG_INT_RX == ctrl_arg)
         {
@@ -376,7 +377,7 @@ static rt_err_t hc32_control(struct rt_serial_device *serial, int cmd, void *arg
             INTC_IntSrcCmd(uart->config->rx_int_src, ENABLE);
             USART_FuncCmd(uart->config->Instance, USART_INT_RX, ENABLE);
         }
-        else
+        else if (RT_DEVICE_FLAG_INT_TX == ctrl_arg)
         {
             NVIC_ClearPendingIRQ(uart->config->tc_irq.irq_config.irq_num);
             NVIC_EnableIRQ(uart->config->tc_irq.irq_config.irq_num);
@@ -573,7 +574,7 @@ static void hc32_uart_rx_timeout(struct rt_serial_device *serial)
     {
         RT_ASSERT(TMR0_CH_B == ch);
     }
-#elif defined(HC32F4A0)
+#elif defined (HC32F4A0)
     if ((CM_USART1 == uart->config->Instance) || (CM_USART6 == uart->config->Instance))
     {
         RT_ASSERT(TMR0_CH_A == ch);
@@ -582,7 +583,7 @@ static void hc32_uart_rx_timeout(struct rt_serial_device *serial)
     {
         RT_ASSERT(TMR0_CH_B == ch);
     }
-#elif defined (HC32F448)
+#elif defined (HC32F448) || defined (HC32F472)
     if ((CM_USART1 == uart->config->Instance) || (CM_USART4 == uart->config->Instance))
     {
         RT_ASSERT(TMR0_CH_A == ch);
@@ -657,7 +658,7 @@ static void hc32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag)
         RT_ASSERT(RT_NULL != uart->config->dma_rx->Instance);
         RT_ASSERT(RT_NULL != rx_fifo);
 
-#if defined (HC32F448)
+#if defined (HC32F448) || defined (HC32F472)
         INTC_IntSrcCmd(uart->config->rx_int_src, DISABLE);
 #endif
 
@@ -801,7 +802,7 @@ static void hc32_uart_rxto_irq_handler(struct hc32_uart *uart)
 #endif
 #endif
 
-#if defined (HC32F448)
+#if defined (HC32F448) || defined (HC32F472)
 static void hc32_usart_handler(struct hc32_uart *uart)
 {
     RT_ASSERT(RT_NULL != uart);
@@ -811,7 +812,10 @@ static void hc32_usart_handler(struct hc32_uart *uart)
             (ENABLE == USART_GetFuncState(uart->config->Instance, USART_RX_TIMEOUT)) && \
             (ENABLE == INTC_GetIntSrcState(uart->config->rxto_int_src)))
     {
+#if defined (BSP_UART1_RX_USING_DMA) || defined (BSP_UART2_RX_USING_DMA) || \
+    defined (BSP_UART4_RX_USING_DMA) || defined (BSP_UART5_RX_USING_DMA)
         hc32_uart_rxto_irq_handler(uart);
+#endif
     }
 #endif
 
@@ -914,7 +918,7 @@ static void hc32_uart1_dma_rx_irq_handler(void)
 #endif /* BSP_UART1_RX_USING_DMA */
 #endif /* RT_SERIAL_USING_DMA */
 
-#if defined (HC32F448)
+#if defined (HC32F448) || defined (HC32F472)
 void USART1_Handler(void)
 {
     /* enter interrupt */
@@ -936,7 +940,7 @@ void USART1_TxComplete_Handler(void)
     /* leave interrupt */
     rt_interrupt_leave();
 }
-#endif /* HC32F448 */
+#endif /* HC32F448, HC32F472 */
 #endif /* BSP_USING_UART1 */
 
 #if defined (BSP_USING_UART2)
@@ -1014,7 +1018,7 @@ static void hc32_uart2_dma_rx_irq_handler(void)
 #endif /* BSP_UART2_RX_USING_DMA */
 #endif /* RT_SERIAL_USING_DMA */
 
-#if defined (HC32F448)
+#if defined (HC32F448) || defined (HC32F472)
 void USART2_Handler(void)
 {
     /* enter interrupt */
@@ -1036,7 +1040,7 @@ void USART2_TxComplete_Handler(void)
     /* leave interrupt */
     rt_interrupt_leave();
 }
-#endif /* HC32F448 */
+#endif /* HC32F448, HC32F472 */
 #endif /* BSP_USING_UART2 */
 
 #if defined (BSP_USING_UART3)
@@ -1115,7 +1119,7 @@ static void hc32_uart3_dma_rx_irq_handler(void)
 #endif /* BSP_UART3_RX_USING_DMA */
 #endif /* RT_SERIAL_USING_DMA */
 
-#if defined (HC32F448)
+#if defined (HC32F448) || defined (HC32F472)
 void USART3_Handler(void)
 {
     /* enter interrupt */
@@ -1137,7 +1141,7 @@ void USART3_TxComplete_Handler(void)
     /* leave interrupt */
     rt_interrupt_leave();
 }
-#endif /* HC32F448 */
+#endif /* HC32F448, HC32F472 */
 #endif /* BSP_USING_UART3 */
 
 #if defined (BSP_USING_UART4)
@@ -1215,7 +1219,7 @@ static void hc32_uart4_dma_rx_irq_handler(void)
 #endif /* BSP_UART4_RX_USING_DMA */
 #endif /* RT_SERIAL_USING_DMA */
 
-#if defined (HC32F448)
+#if defined (HC32F448) || defined (HC32F472)
 void USART4_Handler(void)
 {
     /* enter interrupt */
@@ -1237,7 +1241,7 @@ void USART4_TxComplete_Handler(void)
     /* leave interrupt */
     rt_interrupt_leave();
 }
-#endif /* HC32F448 */
+#endif /* HC32F448, HC32F472 */
 #endif /* BSP_USING_UART4 */
 
 #if defined (BSP_USING_UART5)
@@ -1287,7 +1291,7 @@ static void hc32_uart5_tc_irq_handler(void)
     rt_interrupt_leave();
 }
 
-#if defined (HC32F448)
+#if defined (HC32F448) || defined (HC32F472)
 #if defined (RT_SERIAL_USING_DMA)
 #if defined (BSP_UART5_RX_USING_DMA)
 static void hc32_uart5_dma_rx_irq_handler(void)
@@ -1324,7 +1328,7 @@ void USART5_TxComplete_Handler(void)
     /* leave interrupt */
     rt_interrupt_leave();
 }
-#endif /* HC32F448 */
+#endif /* HC32F448, HC32F472 */
 #endif /* BSP_USING_UART5 */
 
 #if defined (BSP_USING_UART6)
@@ -1402,7 +1406,7 @@ static void hc32_uart6_dma_rx_irq_handler(void)
 #endif /* BSP_UART6_RX_USING_DMA */
 #endif /* RT_SERIAL_USING_DMA */
 
-#if defined (HC32F448)
+#if defined (HC32F448) || defined (HC32F472)
 void USART6_Handler(void)
 {
     /* enter interrupt */
@@ -1424,7 +1428,7 @@ void USART6_TxComplete_Handler(void)
     /* leave interrupt */
     rt_interrupt_leave();
 }
-#endif /* HC32F448 */
+#endif /* HC32F448, HC32F472 */
 #endif /* BSP_USING_UART6 */
 
 #if defined (BSP_USING_UART7)
@@ -1698,7 +1702,7 @@ static void hc32_uart_get_info(void)
     uart_obj[UART3_INDEX].serial.config = config;
     uart_obj[UART3_INDEX].serial.config.rx_bufsz = BSP_UART3_RX_BUFSIZE;
     uart_obj[UART3_INDEX].serial.config.tx_bufsz = BSP_UART3_TX_BUFSIZE;
-#if defined (HC32F460) || defined (HC32F4A0)
+#if defined (HC32F460)
 #ifdef BSP_UART3_RX_USING_DMA
     uart_obj[UART3_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
     static struct dma_config uart3_dma_rx = UART3_DMA_RX_CONFIG;
@@ -1721,12 +1725,13 @@ static void hc32_uart_get_info(void)
     uart_obj[UART4_INDEX].serial.config = config;
     uart_obj[UART4_INDEX].serial.config.rx_bufsz = BSP_UART4_RX_BUFSIZE;
     uart_obj[UART4_INDEX].serial.config.tx_bufsz = BSP_UART4_TX_BUFSIZE;
+#if defined (HC32F460) || defined (HC32F448) || defined (HC32F472)
 #ifdef BSP_UART4_RX_USING_DMA
     uart_obj[UART4_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
     static struct dma_config uart4_dma_rx = UART4_DMA_RX_CONFIG;
     static struct hc32_uart_rxto uart4_rx_timeout = UART4_RXTO_CONFIG;
     uart4_dma_rx.irq_callback = hc32_uart4_dma_rx_irq_handler;
-#if defined (HC32F460) || defined (HC32F4A0)
+#if defined (HC32F460)
     uart4_rx_timeout.irq_callback = hc32_uart4_rxto_irq_handler;
 #endif
     uart_config[UART4_INDEX].rx_timeout = &uart4_rx_timeout;
@@ -1738,13 +1743,14 @@ static void hc32_uart_get_info(void)
     uart_config[UART4_INDEX].dma_tx = &uart4_dma_tx;
 #endif
 #endif
+#endif
 
 #ifdef BSP_USING_UART5
     uart_obj[UART5_INDEX].uart_dma_flag = 0;
     uart_obj[UART5_INDEX].serial.config = config;
     uart_obj[UART5_INDEX].serial.config.rx_bufsz = BSP_UART5_RX_BUFSIZE;
     uart_obj[UART5_INDEX].serial.config.tx_bufsz = BSP_UART5_TX_BUFSIZE;
-#if defined (HC32F460)
+#if defined (HC32F448) || defined (HC32F472)
 #ifdef BSP_UART5_RX_USING_DMA
     uart_obj[UART5_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
     static struct dma_config uart5_dma_rx = UART5_DMA_RX_CONFIG;
@@ -1766,7 +1772,7 @@ static void hc32_uart_get_info(void)
     uart_obj[UART6_INDEX].serial.config = config;
     uart_obj[UART6_INDEX].serial.config.rx_bufsz = BSP_UART6_RX_BUFSIZE;
     uart_obj[UART6_INDEX].serial.config.tx_bufsz = BSP_UART6_TX_BUFSIZE;
-#if defined (HC32F460) || defined (HC32F4A0)
+#if defined (HC32F4A0)
 #ifdef BSP_UART6_RX_USING_DMA
     uart_obj[UART6_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
     static struct dma_config uart6_dma_rx = UART6_DMA_RX_CONFIG;
@@ -1789,6 +1795,7 @@ static void hc32_uart_get_info(void)
     uart_obj[UART7_INDEX].serial.config = config;
     uart_obj[UART7_INDEX].serial.config.rx_bufsz = BSP_UART7_RX_BUFSIZE;
     uart_obj[UART7_INDEX].serial.config.tx_bufsz = BSP_UART7_TX_BUFSIZE;
+#if defined (HC32F4A0)
 #ifdef BSP_UART7_RX_USING_DMA
     uart_obj[UART7_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
     static struct dma_config uart7_dma_rx = UART7_DMA_RX_CONFIG;
@@ -1804,6 +1811,7 @@ static void hc32_uart_get_info(void)
     uart_config[UART7_INDEX].dma_tx = &uart7_dma_tx;
 #endif
 #endif
+#endif
 
 #ifdef BSP_USING_UART8
     uart_obj[UART8_INDEX].uart_dma_flag = 0;
@@ -1916,7 +1924,7 @@ static void hc32_get_uart_callback(void)
     uart_config[UART10_INDEX].tc_irq.irq_callback = hc32_uart10_tc_irq_handler;
 #endif
 }
-#elif defined (HC32F448)
+#elif defined (HC32F448) || defined (HC32F472)
 /**
   * @brief  This function gets uart irq handle.
   * @param  None
@@ -1955,7 +1963,7 @@ static void hc32_get_uart_callback(void)
     uart_config[UART6_INDEX].tc_irq.irq_callback = hc32_uart6_tc_irq_handler;
 #endif
 }
-#endif /* HC32F448 */
+#endif /* HC32F448, HC32F472 */
 
 static const struct rt_uart_ops hc32_uart_ops =
 {

bsp/hc32/libraries/hc32_drivers/drv_usart_v2.h

@@ -57,7 +57,7 @@ struct hc32_uart_config
     struct hc32_uart_irq_config rxerr_irq;
     struct hc32_uart_irq_config rx_irq;
     struct hc32_uart_irq_config tx_irq;
-#elif defined (HC32F448)
+#elif defined (HC32F448) || defined (HC32F472)
     IRQn_Type                   irq_num;
     en_int_src_t                rxerr_int_src;
     en_int_src_t                tx_int_src;

bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_common.h

@@ -1,145 +0,0 @@
-/**
- *******************************************************************************
- * @file  stl_common.h
- * @brief This file contains STL common definitions: enumeration, macros and
- *        structures definitions.
- @verbatim
-   Change Logs:
-   Date             Author          Notes
-   2022-03-31       CDT             First version
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- *                    opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-
-#ifndef __STL_COMMON_H__
-#define __STL_COMMON_H__
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "hc32_ll_def.h"
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/**
- * @addtogroup IEC60730_STL
- * @{
- */
-
-/**
- * @addtogroup IEC60730_STL_Common
- * @{
- */
-
-/*******************************************************************************
- * Global type definitions ('typedef')
-*******************************************************************************/
-
-/*******************************************************************************
- * Global pre-processor symbols/macros ('#define')
- ******************************************************************************/
-
-/**
- * @defgroup STL_Common_Global_Macros STL Common Global Macros
- * @{
- */
-
-/**
- * @defgroup STL_Generic_Error_Codes STL Generic Error Codes
- * @{
- */
-#define STL_OK                          (0UL)   /*!< No error occurs */
-#define STL_ERR                         (1UL)   /*!< Error occurs */
-/**
- * @}
- */
-
-/**
- * @defgroup STL_Module_Switch STL Module Switch
- * @{
- */
-#define STL_ON                          (1U)
-#define STL_OFF                         (0U)
-/**
- * @}
- */
-
-/**
- * @defgroup Compiler_Macros Compiler Macros
- * @{
- */
-#ifdef __CC_ARM                         /*!< ARM Compiler */
-/* CPU will start executing at the program entry label __main when the CPU is reset */
-extern void __main(void);
-
-/* CC */
-#define STL_SECTION(x)              __attribute__((section(x)))
-#define STL_UNUSED                  __attribute__((unused))
-#define STL_USED                    __attribute__((used))
-#define STL_ALIGN(n)                __attribute__((aligned(n)))
-#define STL_WEAK                    __WEAKDEF
-#define STL_INLINE                  static __inline
-
-#define CallApplicationStartUp( )   __main()
-
-#elif defined (__ICCARM__)              /*!< IAR Compiler */
-/* CPU will start executing at the program entry label __iar_program_start when the CPU is reset */
-extern void __iar_program_start(void);
-
-/* CC */
-#define STL_SECTION(x)              @ x
-#define STL_UNUSED
-#define STL_USED                    __root
-#define STL_PRAGMA(x)               _Pragma(#x)
-#define STL_ALIGN(n)                STL_PRAGMA(data_alignment=n)
-#define STL_WEAK                    __WEAKDEF
-#define STL_INLINE                  static inline
-
-#define CallApplicationStartUp( )   __iar_program_start()
-#else
-#error Unsupported tool chain
-#endif
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/*******************************************************************************
- * Global variable definitions ('extern')
- ******************************************************************************/
-
-/*******************************************************************************
- * Global function prototypes (definition in C source)
- ******************************************************************************/
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STL_COMMON_H__ */
-
-/*******************************************************************************
- * EOF (not truncated)
- ******************************************************************************/

bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_conf.h

@@ -1,106 +0,0 @@
-/**
- *******************************************************************************
- * @file  stl_conf.h
- * @brief This file contains STL resource configure.
- @verbatim
-   Change Logs:
-   Date             Author          Notes
-   2022-03-31       CDT             First version
-   2022-06-30       CDT             Optimize macros definitions
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- *                    opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-
-#ifndef __STL_CONF_H__
-#define __STL_CONF_H__
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "stl_bsp_conf.h"
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/**
- * @addtogroup IEC60730_STL
- * @{
- */
-
-/**
- * @addtogroup IEC60730_STL_Configure
- * @{
- */
-
-/*******************************************************************************
- * Global type definitions ('typedef')
-*******************************************************************************/
-
-/*******************************************************************************
- * Global pre-processor symbols/macros ('#define')
- ******************************************************************************/
-
-/**
- * @defgroup IEC60730_STL_Configure_ROM_CRC32_Parameters IEC60730 STL Configure ROM CRC32 Parameters
- * @{
- */
-#define STL_ROM_CRC32_START             (STL_ROM_START)
-#define STL_ROM_CRC32_END               ((uint32_t)(&__checksum))
-#define STL_ROM_CRC32_BLOCK_SIZE        (128UL)
-#define STL_ROM_CRC32_CC_CHECKSUM       (__checksum)
-/**
- * @}
- */
-
-/**
- * @defgroup IEC60730_STL_Configure_RAM_Parameters IEC60730 STL Configure RAM Parameters
- * @{
- */
-#define STL_MARCH_RAM_SIZE              (32UL)
-#define STL_MARCH_RAM_WORDS             (STL_MARCH_RAM_SIZE >> 2)
-#define STL_MARCH_RAM_BUF_SIZE          (16UL)
-#define STL_MARCH_RAM_BUF_WORDS         (STL_MARCH_RAM_BUF_SIZE >> 2)
-
-#define STL_MARCH_RAM_BCKGRND           (0x00000000UL)
-#define STL_MARCH_RAM_INVBCKGRND        (0xFFFFFFFFUL)
-
-#define STL_STACK_BOUNDARY_WORDS        (4UL)
-/**
- * @}
- */
-
-/*******************************************************************************
- * Global variable definitions ('extern')
- ******************************************************************************/
-
-/*******************************************************************************
- * Global function prototypes (definition in C source)
- ******************************************************************************/
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STL_CONF_H__ */
-
-/*******************************************************************************
- * EOF (not truncated)
- ******************************************************************************/

bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_sw_crc32.h

@@ -1,93 +0,0 @@
-/**
- *******************************************************************************
- * @file  stl_test_flash.h
- * @brief This file contains all the functions prototypes of the flash test.
- @verbatim
-   Change Logs:
-   Date             Author          Notes
-   2022-03-31       CDT             First version
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- *                    opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-
-#ifndef __STL_SW_CRC32_H__
-#define __STL_SW_CRC32_H__
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "stl_common.h"
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/**
- * @addtogroup STL_IEC60730
- * @{
- */
-
-/**
- * @addtogroup STL_IEC60730_CRC32
- * @{
- */
-
-/*******************************************************************************
- * Global type definitions ('typedef')
-*******************************************************************************/
-
-/*******************************************************************************
- * Global pre-processor symbols/macros ('#define')
- ******************************************************************************/
-
-/**
- * @defgroup STL_IEC60730_CRC32_Global_Macros STL IEC60730 CRC32 Global Macros
- * @{
- */
-#define STL_CRC32_INIT_VALUE    (0xFFFFFFFFUL)
-/**
- * @}
- */
-
-/*******************************************************************************
- * Global variable definitions ('extern')
- ******************************************************************************/
-
-/*******************************************************************************
- * Global function prototypes (definition in C source)
- ******************************************************************************/
-/**
- * @addtogroup STL_IEC60730_CRC32_Global_Functions
- * @{
- */
-uint32_t STL_CalculateCRC32Value(uint32_t u32Crc32Value, uint8_t *pu8Data, uint32_t u32Len);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STL_SW_CRC32_H__ */
-
-/*******************************************************************************
- * EOF (not truncated)
- ******************************************************************************/

bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_cpu.h

@@ -1,85 +0,0 @@
-/**
- *******************************************************************************
- * @file  stl_test_cpu.h
- * @brief This file contains all the functions prototypes of the CPU test.
- @verbatim
-   Change Logs:
-   Date             Author          Notes
-   2022-03-31       CDT             First version
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- *                    opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-
-#ifndef __STL_TEST_CPU_H__
-#define __STL_TEST_CPU_H__
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "stl_common.h"
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/**
- * @addtogroup STL_IEC60730
- * @{
- */
-
-/**
- * @addtogroup STL_IEC60730_CPU
- * @{
- */
-
-/*******************************************************************************
- * Global type definitions ('typedef')
-*******************************************************************************/
-
-/*******************************************************************************
- * Global pre-processor symbols/macros ('#define')
- ******************************************************************************/
-
-/*******************************************************************************
- * Global variable definitions ('extern')
- ******************************************************************************/
-
-/*******************************************************************************
- * Global function prototypes (definition in C source)
- ******************************************************************************/
-/**
- * @addtogroup STL_IEC60730_CPU_Global_Functions
- * @{
- */
-uint32_t STL_CpuTestStartup(void);
-uint32_t STL_CpuTestRuntime(void);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STL_TEST_CPU_H__ */
-
-/*******************************************************************************
- * EOF (not truncated)
- ******************************************************************************/

bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_flash.h

@@ -1,85 +0,0 @@
-/**
- *******************************************************************************
- * @file  stl_test_flash.h
- * @brief This file contains all the functions prototypes of the flash test.
- @verbatim
-   Change Logs:
-   Date             Author          Notes
-   2022-03-31       CDT             First version
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- *                    opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-
-#ifndef __STL_TEST_FLASH_H__
-#define __STL_TEST_FLASH_H__
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "stl_common.h"
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/**
- * @addtogroup STL_IEC60730
- * @{
- */
-
-/**
- * @addtogroup STL_IEC60730_Flash
- * @{
- */
-
-/*******************************************************************************
- * Global type definitions ('typedef')
-*******************************************************************************/
-
-/*******************************************************************************
- * Global pre-processor symbols/macros ('#define')
- ******************************************************************************/
-
-/*******************************************************************************
- * Global variable definitions ('extern')
- ******************************************************************************/
-
-/*******************************************************************************
- * Global function prototypes (definition in C source)
- ******************************************************************************/
-/**
- * @addtogroup STL_IEC60730_Flash_Global_Functions
- * @{
- */
-uint32_t STL_FlashStartupTest(void);
-uint32_t STL_FlashRuntimeTest(void);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STL_TEST_FLASH_H__ */
-
-/*******************************************************************************
- * EOF (not truncated)
- ******************************************************************************/

bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_interrupt.h

@@ -1,99 +0,0 @@
-/**
- *******************************************************************************
- * @file  stl_test_interrupt.h
- * @brief This file contains all the functions prototypes of the interrupt test.
- @verbatim
-   Change Logs:
-   Date             Author          Notes
-   2022-03-31       CDT             First version
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- *                    opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-
-#ifndef __STL_TEST_INTERRUPT_H__
-#define __STL_TEST_INTERRUPT_H__
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "stl_common.h"
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/**
- * @addtogroup STL_IEC60730
- * @{
- */
-
-/**
- * @addtogroup STL_IEC60730_Interrupt
- * @{
- */
-
-/*******************************************************************************
- * Global type definitions ('typedef')
-*******************************************************************************/
-/**
- * @defgroup STL_IEC60730_Interrupt_Global_Type STL IEC60730 Interrupt Global Type
- * @{
- */
-typedef struct stc_stl_int_params {
-    uint32_t u32FreqInitVal;
-    uint32_t u32FreqLowerVal;
-    uint32_t u32FreqUpperVal;
-    uint32_t u32PrivateParam;
-} stc_stl_int_params_t;
-/**
- * @}
- */
-
-/*******************************************************************************
- * Global pre-processor symbols/macros ('#define')
- ******************************************************************************/
-
-/*******************************************************************************
- * Global variable definitions ('extern')
- ******************************************************************************/
-
-/*******************************************************************************
- * Global function prototypes (definition in C source)
- ******************************************************************************/
-/**
- * @addtogroup STL_IEC60730_Interrupt_Global_Functions
- * @{
- */
-uint32_t STL_IntRuntimeTableInit(stc_stl_int_params_t *pstcParamsTable, uint32_t u32TableSize);
-uint32_t STL_IntRuntimeTest(void);
-void STL_IntUpdateCount(uint8_t u8ParamIndex);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STL_TEST_INTERRUPT_H__ */
-
-/*******************************************************************************
- * EOF (not truncated)
- ******************************************************************************/

bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_pc.h

@@ -1,84 +0,0 @@
-/**
- *******************************************************************************
- * @file  stl_test_pc.h
- * @brief This file contains all the functions prototypes of the PC test.
- @verbatim
-   Change Logs:
-   Date             Author          Notes
-   2022-03-31       CDT             First version
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- *                    opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-
-#ifndef __STL_TEST_PC_H__
-#define __STL_TEST_PC_H__
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "stl_common.h"
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/**
- * @addtogroup STL_IEC60730
- * @{
- */
-
-/**
- * @addtogroup STL_IEC60730_PC
- * @{
- */
-
-/*******************************************************************************
- * Global type definitions ('typedef')
-*******************************************************************************/
-
-/*******************************************************************************
- * Global pre-processor symbols/macros ('#define')
- ******************************************************************************/
-
-/*******************************************************************************
- * Global variable definitions ('extern')
- ******************************************************************************/
-
-/*******************************************************************************
- * Global function prototypes (definition in C source)
- ******************************************************************************/
-/**
- * @addtogroup STL_IEC60730_PC_Global_Functions
- * @{
- */
-uint32_t STL_PcTest(void);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STL_TEST_PC_H__ */
-
-/*******************************************************************************
- * EOF (not truncated)
- ******************************************************************************/

bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_ram.h

@@ -1,88 +0,0 @@
-/**
- *******************************************************************************
- * @file  stl_test_ram.h
- * @brief This file contains all the functions prototypes of the RAM test.
- @verbatim
-   Change Logs:
-   Date             Author          Notes
-   2022-03-31       CDT             First version
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- *                    opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-
-#ifndef __STL_TEST_RAM_H__
-#define __STL_TEST_RAM_H__
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "stl_common.h"
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/**
- * @addtogroup STL_IEC60730
- * @{
- */
-
-/**
- * @addtogroup STL_IEC60730_RAM
- * @{
- */
-
-/*******************************************************************************
- * Global type definitions ('typedef')
-*******************************************************************************/
-
-/*******************************************************************************
- * Global pre-processor symbols/macros ('#define')
- ******************************************************************************/
-
-/*******************************************************************************
- * Global variable definitions ('extern')
- ******************************************************************************/
-
-/*******************************************************************************
- * Global function prototypes (definition in C source)
- ******************************************************************************/
-/**
- * @addtogroup STL_IEC60730_RAM_Global_Functions
- * @{
- */
-uint32_t STL_StackRuntimeInit(void);
-uint32_t STL_StackRuntimeTest(void);
-uint32_t STL_RamRuntimeInit(void);
-uint32_t STL_RamRuntimeTest(void);
-uint32_t STL_FullRamTestStartup(uint32_t u32StartAddr, uint32_t u32EndAddr);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STL_TEST_RAM_H__ */
-
-/*******************************************************************************
- * EOF (not truncated)
- ******************************************************************************/

bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/EWARM/stl_test_cpu_cm0_startup.s

@@ -1,372 +0,0 @@
-;/*****************************************************************************
-; * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
-; *
-; * This software component is licensed by XHSC under BSD 3-Clause license
-; * (the "License"); You may not use this file except in compliance with the
-; * License. You may obtain a copy of the License at:
-; *                    opensource.org/licenses/BSD-3-Clause
-; *
-; */
-;/****************************************************************************/
-;/*  Test for IAR                                                            */
-;/*  Version     V1.0                                                        */
-;/*  Date        2022-09-14                                                  */
-;/****************************************************************************/
-
-            SECTION constdata:CONST(2)
-data0xAAAAAAAA       DCD     0xAAAAAAAA
-data0x55555555       DCD     0x55555555
-data0x80000000       DCD     0x80000000
-data0xAAAAAAA8       DCD     0xAAAAAAA8
-data0x55555554       DCD     0x55555554
-data0x00000000       DCD     0x00000000
-data0x00000001       DCD     0x00000001
-data0x50000000       DCD     0x50000000
-data0xA0000000       DCD     0xA0000000
-
-            ; Exported function
-            EXPORT STL_CpuTestStartup
-
-;*******************************************************************************
-; Function Name  : STL_CpuTestStartup
-; Description    : Test CPU at start-up
-; Input          : None.
-; Output         : Perform routine when detect failure at set of self test cases
-; Return         : STL_OK (=0):test pass; STL_ERR (=1):test fail;
-; WARNING        : all registers destroyed when exiting this function (including
-;                  preserved registers R4 to R11) and excluding stack point R13)
-;*******************************************************************************/
-            THUMB
-            SECTION .text:CODE(2)
-STL_CpuTestStartup:
-            PUSH {R4-R7}                         ; Save registers
-
-_test_cpu_reg0_reg8
-            MOVS R0, #0x00
-            UXTB R0, R0
-            ADDS R0, #0                          ; Set Z(ero) Flag
-            BNE _test_cpu_reg0_reg13_fail        ; Fails if Z clear
-            BMI _test_cpu_reg0_reg13_fail        ; Fails if N is set
-            SUBS R0, #1                          ; Set N(egative) Flag
-            BPL _test_cpu_reg0_reg13_fail        ; Fails if N clear
-            ADDS R0, #2                          ; Set C(arry) Flag and do not set Z
-            BCC _test_cpu_reg0_reg13_fail        ; Fails if C clear
-            BEQ _test_cpu_reg0_reg13_fail        ; Fails if Z is set
-            BMI _test_cpu_reg0_reg13_fail        ; Fails if N is set
-
-            LDR R0, =data0x80000000              ; Prepares Overflow test
-            LDR R0, [R0]
-            ADDS R0, R0, R0                      ; Set V(overflow) Flag
-            BVC _test_cpu_reg0_reg13_fail        ; Fails if V clear
-
-            ; Register R1
-            LDR R0, =data0xAAAAAAAA
-            LDR R1, [R0]
-            LDR R0, [R0]
-            CMP R0, R1
-            BNE _test_cpu_reg0_reg13_fail
-            LDR R0, =data0x55555555
-            LDR R1, [R0]
-            LDR R0, [R0]
-            CMP R0, R1
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R1, #0x1
-
-            ; Register R2
-            LDR R0, =data0xAAAAAAAA
-            LDR R2, [R0]
-            LDR R0, [R0]
-            CMP R0, R2
-            BNE _test_cpu_reg0_reg13_fail
-            LDR R0, =data0x55555555
-            LDR R2, [R0]
-            LDR R0, [R0]
-            CMP R0, R2
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R2, #0x2
-
-            ; Register R3
-            LDR R0, =data0xAAAAAAAA
-            LDR R3, [R0]
-            LDR R0, [R0]
-            CMP R0, R3
-            BNE _test_cpu_reg0_reg13_fail
-            LDR R0, =data0x55555555
-            LDR R3, [R0]
-            LDR R0, [R0]
-            CMP R0, R3
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R3, #0x3
-
-            ; Register R4
-            LDR R0, =data0xAAAAAAAA
-            LDR R4, [R0]
-            LDR R0, [R0]
-            CMP R0, R4
-            BNE _test_cpu_reg0_reg13_fail
-            LDR R0, =data0x55555555
-            LDR R4, [R0]
-            LDR R0, [R0]
-            CMP R0, R4
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R4, #0x4
-
-            ; Register R5
-            LDR R0, =data0xAAAAAAAA
-            LDR R5, [R0]
-            LDR R0, [R0]
-            CMP R0, R5
-            BNE _test_cpu_reg0_reg13_fail
-            LDR R0, =data0x55555555
-            LDR R5, [R0]
-            LDR R0, [R0]
-            CMP R0, R5
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R5, #0x5
-
-            ; Register R6
-            LDR R0, =data0xAAAAAAAA
-            LDR R6, [R0]
-            LDR R0, [R0]
-            CMP R0, R6
-            BNE _test_cpu_reg0_reg13_fail
-            LDR R0, =data0x55555555
-            LDR R6, [R0]
-            LDR R0, [R0]
-            CMP R0, R6
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R6, #0x6
-
-            ; Register R7
-            LDR R0, =data0xAAAAAAAA
-            LDR R7, [R0]
-            LDR R0, [R0]
-            CMP R0, R7
-            BNE _test_cpu_reg0_reg13_fail
-            LDR R0, =data0x55555555
-            LDR R7, [R0]
-            LDR R0, [R0]
-            CMP R0, R7
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R7, #0x7
-
-            ; Register R8
-            LDR R0, =data0xAAAAAAAA
-            LDR R0, [R0]
-            MOV R8, R0
-            CMP R0, R8
-            BNE _test_cpu_reg0_reg13_fail
-            LDR R0, =data0x55555555
-            LDR R0, [R0]
-            MOV R8, R0
-            CMP R0, R8
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R0, #0x08
-            MOV R8, R0
-
-            BAL _test_cpu_continue
-
-_test_cpu_reg0_reg13_fail
-            ; test fail, R0 will hold value 1
-            MOVS R0, #0x1                        ; STL_ERR
-            B _test_exit
-
-_test_cpu_continue
-            ; Register R9
-            LDR R0, =data0xAAAAAAAA
-            LDR R0, [R0]
-            MOV R9, R0
-            CMP R0, R9
-            BNE _test_cpu_reg0_reg13_fail
-            LDR R0, =data0x55555555
-            LDR R0, [R0]
-            MOV R9, R0
-            CMP R0, R9
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R0, #0x09
-            MOV R9, R0
-
-            ; Register R10
-            LDR R0, =data0xAAAAAAAA
-            LDR R0, [R0]
-            MOV R10, R0
-            CMP R0, R10
-            BNE _test_cpu_reg0_reg13_fail
-            LDR R0, =data0x55555555
-            LDR R0, [R0]
-            MOV R10, R0
-            CMP R0, R10
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R0, #0x0A
-            MOV R10, R0
-
-            ; Register R11
-            LDR R0, =data0xAAAAAAAA
-            LDR R0, [R0]
-            MOV R11, R0
-            CMP R0, R11
-            BNE _test_cpu_reg0_reg13_fail
-            LDR R0, =data0x55555555
-            LDR R0, [R0]
-            MOV R11, R0
-            CMP R0, R11
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R0, #0x0B
-            MOV R11, R0
-
-            ; Register R12
-            LDR R0, =data0xAAAAAAAA
-            LDR R0, [R0]
-            MOV R12, R0
-            CMP R0, R12
-            BNE _test_cpu_reg0_reg13_fail
-            LDR R0, =data0x55555555
-            LDR R0, [R0]
-            MOV R12, R0
-            CMP R0, R12
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R0, #0x0C
-            MOV R12, R0
-            LDR R0, =_test_cpu_continue
-
-            ; pattern verification (R0 is not tested)
-            CMP R1, #0x01
-            BNE _test_cpu_reg0_reg13_fail
-            CMP R2, #0x02
-            BNE _test_cpu_reg0_reg13_fail
-            CMP R3, #0x03
-            BNE _test_cpu_reg0_reg13_fail
-            CMP R4, #0x04
-            BNE _test_cpu_reg0_reg13_fail
-            CMP R5, #0x05
-            BNE _test_cpu_reg0_reg13_fail
-            CMP R6, #0x06
-            BNE _test_cpu_reg0_reg13_fail
-            CMP R7, #0x07
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R0, #0x08
-            CMP R0, R8
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R0, #0x09
-            CMP R0, R9
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R0, #0x0A
-            CMP R0, R10
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R0, #0x0B
-            CMP R0, R11
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R0, #0x0C
-            CMP R0, R12
-            BNE _test_cpu_reg0_reg13_fail
-
-            ; Process Stack pointer (banked Register R13)
-            MRS R0, PSP                          ; Save process stack value
-            LDR R1, =data0xAAAAAAA8              ; Test is different (PSP is word aligned, 2 LSB cleared)
-            LDR R1, [R1]
-            MSR PSP, R1                          ; load process stack value
-            MRS R2, PSP                          ; Get back process stack value
-            CMP R2, R1                           ; Verify value
-            BNE _test_cpu_reg0_reg13_fail
-            LDR R1, =data0x55555554              ; Test is different (PSP is word aligned, 2 LSB cleared)
-            LDR R1, [R1]
-            MSR PSP, R1                          ; load process stack value
-            MRS R2, PSP                          ; Get back process stack value
-            CMP R2, R1                           ; Verify value
-            BNE _test_cpu_reg0_reg13_fail
-            MSR PSP, R0                          ; Restore process stack value
-
-            ; Stack pointer (Register R13)
-            MRS R0, MSP                          ; Save stack pointer value
-            LDR R1, =data0xAAAAAAA8              ; Test is different (SP is word aligned, 2 LSB cleared)
-            LDR R1, [R1]
-            MSR MSP, R1                          ; load SP value
-            MRS R2, MSP                          ; Get back SP value
-            CMP R2, R1                           ; Verify value
-            BNE _test_cpu_reg0_reg13_fail
-            LDR R1, =data0x55555554
-            LDR R1, [R1]                         ; load SP value
-            MSR MSP, R1                          ; Get back SP value
-            MRS R2, MSP                          ; Verify value
-            CMP R2, R1
-            BNE _test_cpu_reg0_reg13_fail
-            MSR MSP, R0                          ; Restore stack pointer value
-
-_test_cpu_r14_sfr
-            ; Link register R14
-            MOV R1, LR
-            LDR R0, =data0x55555555
-            LDR R0, [R0]
-            MOV R14, R0
-            CMP R0, R14
-            BNE _test_cpu_r14_sfr_fail
-
-            LDR R0, =data0xAAAAAAAA
-            LDR R0, [R0]
-            MOV R14, R0
-            CMP R0, R14
-            BNE _test_cpu_r14_sfr_fail
-
-            LDR R0, =data0x55555555
-            LDR R0, [R0]
-            MOV R14, R0
-            CMP R0, R14
-            BNE _test_cpu_r14_sfr_fail
-
-            LDR R0, =data0xAAAAAAAA
-            LDR R0, [R0]
-            MOV R14, R0
-            CMP R0, R14
-            BNE _test_cpu_r14_sfr_fail
-            MOV LR, R1
-
-            ; APSR
-            MRS R0, APSR
-            LDR R1, =data0x50000000
-            LDR R1,[R1]
-            MSR APSR,R1
-            MRS R2, APSR
-            CMP R1, R2
-            BNE _test_cpu_r14_sfr_fail
-
-            LDR R1, =data0xA0000000
-            LDR R1,[R1]
-            MSR APSR,R1
-            MRS R2, APSR
-            CMP R1, R2
-            BNE _test_cpu_r14_sfr_fail
-            MSR APSR,R0
-
-            ; PRIMASK register
-            MRS R0, PRIMASK
-            LDR R1, =data0x00000000
-            LDR R1, [R1]
-            MSR PRIMASK, R1
-            MRS R2, PRIMASK
-            CMP R1, R2
-            BNE _test_cpu_r14_sfr_fail
-
-            LDR R1, =data0x00000001
-            LDR R1, [R1]
-            MSR PRIMASK, R1
-            MRS R2, PRIMASK
-            CMP R1, R2
-            BNE _test_cpu_r14_sfr_fail
-            MSR PRIMASK, R0
-            B _test_cpu_pass
-
-_test_cpu_r14_sfr_fail
-            ; test fail, R0 will hold value 1
-            MOVS R0, #0x1                        ; STL_ERR
-            B _test_exit
-
-_test_cpu_pass
-            ; test pass, R0 will hold value 0
-            MOVS R0, #0x0                        ; STL_OK
-            B _test_exit
-
-_test_exit
-            POP {R4-R7}                          ; Restore registers
-            BX LR
-
-            END

bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/EWARM/stl_test_cpu_cm4_startup.s

@@ -1,420 +0,0 @@
-;/*****************************************************************************
-; * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
-; *
-; * This software component is licensed by XHSC under BSD 3-Clause license
-; * (the "License"); You may not use this file except in compliance with the
-; * License. You may obtain a copy of the License at:
-; *                    opensource.org/licenses/BSD-3-Clause
-; *
-; */
-;/****************************************************************************/
-;/*  Test for IAR                                                            */
-;/*  Date             Author          Notes                                  */
-;/*  2022-09-14       CDT             First version                          */
-;/*  2022-12-20       CDT             Load data to R0 before USAT            */
-;/*  2023-05-31       CDT             Typo: Veriry -> Verify                 */
-;/****************************************************************************/
-
-            SECTION constdata:CONST(2)
-data0xAAAAAAAA       DCD     0xAAAAAAAA
-data0x55555555       DCD     0x55555555
-data0x80000000       DCD     0x80000000
-data0xAAAAAAA8       DCD     0xAAAAAAA8
-data0x55555554       DCD     0x55555554
-data0x00000000       DCD     0x00000000
-data0x00000001       DCD     0x00000001
-data0x50000000       DCD     0x50000000
-data0xA8000000       DCD     0xA8000000
-data0x00000050       DCD     0x00000050
-data0x000000A0       DCD     0x000000A0
-data0xFFFFFFFF       DCD     0xFFFFFFFF
-
-            ; Exported function
-            EXPORT STL_CpuTestStartup
-
-;*******************************************************************************
-; Function Name  : STL_CpuTestStartup
-; Description    : Test CPU at start-up
-; Input          : None.
-; Output         : Perform routine when detect failure at set of self test cases
-; Return         : STL_OK (=0):test pass; STL_ERR (=1):test fail;
-; WARNING        : all registers destroyed when exiting this function (including
-;                  preserved registers R4 to R11) and excluding stack point R13)
-;*******************************************************************************/
-            THUMB
-            SECTION .text:CODE(2)
-STL_CpuTestStartup:
-            PUSH {R4-R7}                         ; Save registers
-
-_test_cpu_reg0_reg8
-            MOVS R0, #0x00
-            UXTB R0, R0
-            ADDS R0, #0                          ; Set Z(ero) Flag
-            BNE _test_cpu_reg0_reg13_fail        ; Fails if Z clear
-            BMI _test_cpu_reg0_reg13_fail        ; Fails if N is set
-            SUBS R0, #1                          ; Set N(egative) Flag
-            BPL _test_cpu_reg0_reg13_fail        ; Fails if N clear
-            ADDS R0, #2                          ; Set C(arry) Flag and do not set Z
-            BCC _test_cpu_reg0_reg13_fail        ; Fails if C clear
-            BEQ _test_cpu_reg0_reg13_fail        ; Fails if Z is set
-            BMI _test_cpu_reg0_reg13_fail        ; Fails if N is set
-
-            LDR R0, =data0x80000000              ; Prepares Overflow test
-            LDR R0, [R0]
-            ADDS R0, R0, R0                      ; Set V(overflow) Flag
-            BVC _test_cpu_reg0_reg13_fail        ; Fails if V clear
-
-            MOV R0, #0
-            MSR APSR, R0
-            LDR R0, =data0xFFFFFFFF              ; Prepares Saturation test
-            LDR R0, [R0]
-            USAT R1, #10, R0                     ; Set Q(saturation) flag
-            MRS R0, APSR                         ; Get APSR status register
-            CMP R0, #0x08000000                  ; Verify Q=1
-            BNE _test_cpu_reg0_reg13_fail        ; Fails if Q is set
-
-            ; Register R1
-            LDR R0, =data0xAAAAAAAA
-            LDR R1, [R0]
-            LDR R0, [R0]
-            CMP R0, R1
-            BNE _test_cpu_reg0_reg13_fail
-            LDR R0, =data0x55555555
-            LDR R1, [R0]
-            LDR R0, [R0]
-            CMP R0, R1
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R1, #0x1
-
-            ; Register R2
-            LDR R0, =data0xAAAAAAAA
-            LDR R2, [R0]
-            LDR R0, [R0]
-            CMP R0, R2
-            BNE _test_cpu_reg0_reg13_fail
-            LDR R0, =data0x55555555
-            LDR R2, [R0]
-            LDR R0, [R0]
-            CMP R0, R2
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R2, #0x2
-
-            ; Register R3
-            LDR R0, =data0xAAAAAAAA
-            LDR R3, [R0]
-            LDR R0, [R0]
-            CMP R0, R3
-            BNE _test_cpu_reg0_reg13_fail
-            LDR R0, =data0x55555555
-            LDR R3, [R0]
-            LDR R0, [R0]
-            CMP R0, R3
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R3, #0x3
-
-            ; Register R4
-            LDR R0, =data0xAAAAAAAA
-            LDR R4, [R0]
-            LDR R0, [R0]
-            CMP R0, R4
-            BNE _test_cpu_reg0_reg13_fail
-            LDR R0, =data0x55555555
-            LDR R4, [R0]
-            LDR R0, [R0]
-            CMP R0, R4
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R4, #0x4
-
-            ; Register R5
-            LDR R0, =data0xAAAAAAAA
-            LDR R5, [R0]
-            LDR R0, [R0]
-            CMP R0, R5
-            BNE _test_cpu_reg0_reg13_fail
-            LDR R0, =data0x55555555
-            LDR R5, [R0]
-            LDR R0, [R0]
-            CMP R0, R5
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R5, #0x5
-
-            ; Register R6
-            LDR R0, =data0xAAAAAAAA
-            LDR R6, [R0]
-            LDR R0, [R0]
-            CMP R0, R6
-            BNE _test_cpu_reg0_reg13_fail
-            LDR R0, =data0x55555555
-            LDR R6, [R0]
-            LDR R0, [R0]
-            CMP R0, R6
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R6, #0x6
-
-            ; Register R7
-            LDR R0, =data0xAAAAAAAA
-            LDR R7, [R0]
-            LDR R0, [R0]
-            CMP R0, R7
-            BNE _test_cpu_reg0_reg13_fail
-            LDR R0, =data0x55555555
-            LDR R7, [R0]
-            LDR R0, [R0]
-            CMP R0, R7
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R7, #0x7
-
-            ; Register R8
-            LDR R0, =data0xAAAAAAAA
-            LDR R0, [R0]
-            MOV R8, R0
-            CMP R0, R8
-            BNE _test_cpu_reg0_reg13_fail
-            LDR R0, =data0x55555555
-            LDR R0, [R0]
-            MOV R8, R0
-            CMP R0, R8
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R0, #0x08
-            MOV R8, R0
-
-            BAL _test_cpu_continue
-
-_test_cpu_reg0_reg13_fail
-            ; test fail, R0 will hold value 1
-            MOVS R0, #0x1                        ; STL_ERR
-            B _test_exit
-
-_test_cpu_continue
-            ; Register R9
-            LDR R0, =data0xAAAAAAAA
-            LDR R0, [R0]
-            MOV R9, R0
-            CMP R0, R9
-            BNE _test_cpu_reg0_reg13_fail
-            LDR R0, =data0x55555555
-            LDR R0, [R0]
-            MOV R9, R0
-            CMP R0, R9
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R0, #0x09
-            MOV R9, R0
-
-            ; Register R10
-            LDR R0, =data0xAAAAAAAA
-            LDR R0, [R0]
-            MOV R10, R0
-            CMP R0, R10
-            BNE _test_cpu_reg0_reg13_fail
-            LDR R0, =data0x55555555
-            LDR R0, [R0]
-            MOV R10, R0
-            CMP R0, R10
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R0, #0x0A
-            MOV R10, R0
-
-            ; Register R11
-            LDR R0, =data0xAAAAAAAA
-            LDR R0, [R0]
-            MOV R11, R0
-            CMP R0, R11
-            BNE _test_cpu_reg0_reg13_fail
-            LDR R0, =data0x55555555
-            LDR R0, [R0]
-            MOV R11, R0
-            CMP R0, R11
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R0, #0x0B
-            MOV R11, R0
-
-            ; Register R12
-            LDR R0, =data0xAAAAAAAA
-            LDR R0, [R0]
-            MOV R12, R0
-            CMP R0, R12
-            BNE _test_cpu_reg0_reg13_fail
-            LDR R0, =data0x55555555
-            LDR R0, [R0]
-            MOV R12, R0
-            CMP R0, R12
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R0, #0x0C
-            MOV R12, R0
-            LDR R0, =_test_cpu_continue
-
-            ; pattern verification (R0 is not tested)
-            CMP R1, #0x01
-            BNE _test_cpu_reg0_reg13_fail
-            CMP R2, #0x02
-            BNE _test_cpu_reg0_reg13_fail
-            CMP R3, #0x03
-            BNE _test_cpu_reg0_reg13_fail
-            CMP R4, #0x04
-            BNE _test_cpu_reg0_reg13_fail
-            CMP R5, #0x05
-            BNE _test_cpu_reg0_reg13_fail
-            CMP R6, #0x06
-            BNE _test_cpu_reg0_reg13_fail
-            CMP R7, #0x07
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R0, #0x08
-            CMP R0, R8
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R0, #0x09
-            CMP R0, R9
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R0, #0x0A
-            CMP R0, R10
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R0, #0x0B
-            CMP R0, R11
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R0, #0x0C
-            CMP R0, R12
-            BNE _test_cpu_reg0_reg13_fail
-
-            ; Process Stack pointer (banked Register R13)
-            MRS R0, PSP                          ; Save process stack value
-            LDR R1, =data0xAAAAAAA8              ; Test is different (PSP is word aligned, 2 LSB cleared)
-            LDR R1, [R1]
-            MSR PSP, R1                          ; load process stack value
-            MRS R2, PSP                          ; Get back process stack value
-            CMP R2, R1                           ; Verify value
-            BNE _test_cpu_reg0_reg13_fail
-            LDR R1, =data0x55555554              ; Test is different (PSP is word aligned, 2 LSB cleared)
-            LDR R1, [R1]
-            MSR PSP, R1                          ; load process stack value
-            MRS R2, PSP                          ; Get back process stack value
-            CMP R2, R1                           ; Verify value
-            BNE _test_cpu_reg0_reg13_fail
-            MSR PSP, R0                          ; Restore process stack value
-
-            ; Stack pointer (Register R13)
-            MRS R0, MSP                          ; Save stack pointer value
-            LDR R1, =data0xAAAAAAA8              ; Test is different (SP is word aligned, 2 LSB cleared)
-            LDR R1, [R1]
-            MSR MSP, R1                          ; load SP value
-            MRS R2, MSP                          ; Get back SP value
-            CMP R2, R1                           ; Verify value
-            BNE _test_cpu_reg0_reg13_fail
-            LDR R1, =data0x55555554
-            LDR R1, [R1]                         ; load SP value
-            MSR MSP, R1                          ; Get back SP value
-            MRS R2, MSP                          ; Verify value
-            CMP R2, R1
-            BNE _test_cpu_reg0_reg13_fail
-            MSR MSP, R0                          ; Restore stack pointer value
-
-_test_cpu_r14_sfr
-            ; Link register R14
-            MOV R1, LR
-            LDR R0, =data0x55555555
-            LDR R0, [R0]
-            MOV R14, R0
-            CMP R0, R14
-            BNE _test_cpu_r14_sfr_fail
-
-            LDR R0, =data0xAAAAAAAA
-            LDR R0, [R0]
-            MOV R14, R0
-            CMP R0, R14
-            BNE _test_cpu_r14_sfr_fail
-
-            LDR R0, =data0x55555555
-            LDR R0, [R0]
-            MOV R14, R0
-            CMP R0, R14
-            BNE _test_cpu_r14_sfr_fail
-
-            LDR R0, =data0xAAAAAAAA
-            LDR R0, [R0]
-            MOV R14, R0
-            CMP R0, R14
-            BNE _test_cpu_r14_sfr_fail
-            MOV LR, R1
-
-            ; APSR
-            MRS R0, APSR
-            LDR R1, =data0x50000000
-            LDR R1,[R1]
-            MSR APSR,R1
-            MRS R2, APSR
-            CMP R1, R2
-            BNE _test_cpu_r14_sfr_fail
-
-            LDR R1, =data0xA8000000
-            LDR R1,[R1]
-            MSR APSR,R1
-            MRS R2, APSR
-            CMP R1, R2
-            BNE _test_cpu_r14_sfr_fail
-            MSR APSR,R0
-
-            ; PRIMASK register
-            MRS R0, PRIMASK
-            LDR R1, =data0x00000000
-            LDR R1, [R1]
-            MSR PRIMASK, R1
-            MRS R2, PRIMASK
-            CMP R1, R2
-            BNE _test_cpu_r14_sfr_fail
-
-            LDR R1, =data0x00000001
-            LDR R1, [R1]
-            MSR PRIMASK, R1
-            MRS R2, PRIMASK
-            CMP R1, R2
-            BNE _test_cpu_r14_sfr_fail
-            MSR PRIMASK, R0
-
-            ; FAULTMASK register
-            MRS R0, FAULTMASK
-            LDR R1, =data0x00000000
-            LDR R1, [R1]
-            MSR FAULTMASK, R1
-            MRS R2, FAULTMASK
-            CMP R1, R2
-            BNE _test_cpu_r14_sfr_fail
-
-            LDR R1, =data0x00000001
-            LDR R1, [R1]
-            MSR FAULTMASK, R1
-            MRS R2, FAULTMASK
-            CMP R1, R2
-            BNE _test_cpu_r14_sfr_fail
-            MSR FAULTMASK, R0
-
-            ; BASEPRI register
-            MRS R0, BASEPRI
-            LDR R1, =data0x000000A0
-            LDR R1, [R1]
-            MSR BASEPRI, R1
-            MRS R2, BASEPRI
-            CMP R1, R2
-            BNE _test_cpu_r14_sfr_fail
-
-            LDR R1, =data0x00000050
-            LDR R1, [R1]
-            MSR BASEPRI, R1
-            MRS R2, BASEPRI
-            CMP R1, R2
-            BNE _test_cpu_r14_sfr_fail
-            MSR BASEPRI, R0
-            B _test_cpu_pass
-
-_test_cpu_r14_sfr_fail
-            ; test fail, R0 will hold value 1
-            MOVS R0, #0x1                        ; STL_ERR
-            B _test_exit
-
-_test_cpu_pass
-            ; test pass, R0 will hold value 0
-            MOVS R0, #0x0                        ; STL_OK
-            B _test_exit
-
-_test_exit
-            POP {R4-R7}                          ; Restore registers
-            BX LR
-
-            END

bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/EWARM/stl_test_cpu_runtime.s

@@ -1,245 +0,0 @@
-;/*****************************************************************************
-; * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
-; *
-; * This software component is licensed by XHSC under BSD 3-Clause license
-; * (the "License"); You may not use this file except in compliance with the
-; * License. You may obtain a copy of the License at:
-; *                    opensource.org/licenses/BSD-3-Clause
-; *
-; */
-;/****************************************************************************/
-;/*  Test for IAR                                                            */
-;/*  Version     V1.0                                                        */
-;/*  Date        2022-03-31                                                  */
-;/****************************************************************************/
-
-            SECTION constdata:CONST(2)
-data0xAAAAAAAA       DCD     0xAAAAAAAA
-data0x55555555       DCD     0x55555555
-
-            ; Exported function
-            EXPORT STL_CpuTestRuntime
-
-;*******************************************************************************
-; Function Name  : STL_CpuTestRuntime
-; Description    : Test CPU at run-time
-; Input          : None.
-; Output         : Perform routine when detect failure at set of self test cases
-; Return         : STL_OK (=0):test pass; STL_ERR (=1):test fail;
-; WARNING        : all registers destroyed when exiting this function (including
-;                  preserved registers R4 to R11) and excluding stack point R13)
-;*******************************************************************************/
-            THUMB
-            SECTION .text:CODE(2)
-STL_CpuTestRuntime:
-            PUSH {R4-R7}              ; Save registers
-
-            ; Register R1
-            LDR R0, =data0xAAAAAAAA
-            LDR R1, [R0]
-            LDR R0, [R0]
-            CMP R0, R1
-            BNE _test_cpu_fail
-            LDR R0, =data0x55555555
-            LDR R1, [R0]
-            LDR R0, [R0]
-            CMP R0, R1
-            BNE _test_cpu_fail
-            MOVS R1, #0x1
-
-            ; Register R2
-            LDR R0, =data0xAAAAAAAA
-            LDR R2, [R0]
-            LDR R0, [R0]
-            CMP R0, R2
-            BNE _test_cpu_fail
-            LDR R0, =data0x55555555
-            LDR R2, [R0]
-            LDR R0, [R0]
-            CMP R0, R2
-            BNE _test_cpu_fail
-            MOVS R2, #0x2
-
-            ; Register R3
-            LDR R0, =data0xAAAAAAAA
-            LDR R3, [R0]
-            LDR R0, [R0]
-            CMP R0, R3
-            BNE _test_cpu_fail
-            LDR R0, =data0x55555555
-            LDR R3, [R0]
-            LDR R0, [R0]
-            CMP R0, R3
-            BNE _test_cpu_fail
-            MOVS R3, #0x3
-
-            ; Register R4
-            LDR R0, =data0xAAAAAAAA
-            LDR R4, [R0]
-            LDR R0, [R0]
-            CMP R0, R4
-            BNE _test_cpu_fail
-            LDR R0, =data0x55555555
-            LDR R4, [R0]
-            LDR R0, [R0]
-            CMP R0, R4
-            BNE _test_cpu_fail
-            MOVS R4, #0x4
-
-            ; Register R5
-            LDR R0, =data0xAAAAAAAA
-            LDR R5, [R0]
-            LDR R0, [R0]
-            CMP R0, R5
-            BNE _test_cpu_fail
-            LDR R0, =data0x55555555
-            LDR R5, [R0]
-            LDR R0, [R0]
-            CMP R0, R5
-            BNE _test_cpu_fail
-            MOVS R5, #0x5
-
-            ; Register R6
-            LDR R0, =data0xAAAAAAAA
-            LDR R6, [R0]
-            LDR R0, [R0]
-            CMP R0, R6
-            BNE _test_cpu_fail
-            LDR R0, =data0x55555555
-            LDR R6, [R0]
-            LDR R0, [R0]
-            CMP R0, R6
-            BNE _test_cpu_fail
-            MOVS R6, #0x6
-
-            ; Register R7
-            LDR R0, =data0xAAAAAAAA
-            LDR R7, [R0]
-            LDR R0, [R0]
-            CMP R0, R7
-            BNE _test_cpu_fail
-            LDR R0, =data0x55555555
-            LDR R7, [R0]
-            LDR R0, [R0]
-            CMP R0, R7
-            BNE _test_cpu_fail
-            MOVS R7, #0x7
-
-            ; Register R8
-            LDR R0, =data0xAAAAAAAA
-            LDR R0, [R0]
-            MOV R8, R0
-            CMP R0, R8
-            BNE _test_cpu_fail
-            LDR R0, =data0x55555555
-            LDR R0, [R0]
-            MOV R8, R0
-            CMP R0, R8
-            BNE _test_cpu_fail
-            MOVS R0, #0x08
-            MOV R8, R0
-
-            BAL _test_cpu_continue
-
-_test_cpu_fail
-            ; test fail, R0 will hold value 1
-            MOVS R0, #0x1       ; STL_ERR
-            B _test_exit
-
-_test_cpu_continue
-            ; Register R9
-            LDR R0, =data0xAAAAAAAA
-            LDR R0, [R0]
-            MOV R9, R0
-            CMP R0, R9
-            BNE _test_cpu_fail
-            LDR R0, =data0x55555555
-            LDR R0, [R0]
-            MOV R9, R0
-            CMP R0, R9
-            BNE _test_cpu_fail
-            MOVS R0, #0x09
-            MOV R9, R0
-
-            ; Register R10
-            LDR R0, =data0xAAAAAAAA
-            LDR R0, [R0]
-            MOV R10, R0
-            CMP R0, R10
-            BNE _test_cpu_fail
-            LDR R0, =data0x55555555
-            LDR R0, [R0]
-            MOV R10, R0
-            CMP R0, R10
-            BNE _test_cpu_fail
-            MOVS R0, #0x0A
-            MOV R10, R0
-
-            ; Register R11
-            LDR R0, =data0xAAAAAAAA
-            LDR R0, [R0]
-            MOV R11, R0
-            CMP R0, R11
-            BNE _test_cpu_fail
-            LDR R0, =data0x55555555
-            LDR R0, [R0]
-            MOV R11, R0
-            CMP R0, R11
-            BNE _test_cpu_fail
-            MOVS R0, #0x0B
-            MOV R11, R0
-
-            ; Register R12
-            LDR R0, =data0xAAAAAAAA
-            LDR R0, [R0]
-            MOV R12, R0
-            CMP R0, R12
-            BNE _test_cpu_fail
-            LDR R0, =data0x55555555
-            LDR R0, [R0]
-            MOV R12, R0
-            CMP R0, R12
-            BNE _test_cpu_fail
-            MOVS R0, #0x0C
-            MOV R12, R0
-            LDR R0, =_test_cpu_continue
-
-            ; pattern verification  (R0 is not tested)
-            CMP R1, #0x01
-            BNE _test_cpu_fail
-            CMP R2, #0x02
-            BNE _test_cpu_fail
-            CMP R3, #0x03
-            BNE _test_cpu_fail
-            CMP R4, #0x04
-            BNE _test_cpu_fail
-            CMP R5, #0x05
-            BNE _test_cpu_fail
-            CMP R6, #0x06
-            BNE _test_cpu_fail
-            CMP R7, #0x07
-            BNE _test_cpu_fail
-            MOVS R0, #0x08
-            CMP R0, R8
-            BNE _test_cpu_fail
-            MOVS R0, #0x09
-            CMP R0, R9
-            BNE _test_cpu_fail
-            MOVS R0, #0x0A
-            CMP R0, R10
-            BNE _test_cpu_fail
-            MOVS R0, #0x0B
-            CMP R0, R11
-            BNE _test_cpu_fail
-            MOVS R0, #0x0C
-            CMP R0, R12
-            BNE _test_cpu_fail
-
-            ; Link register R14
-            ; test pass, R0 will hold value 0
-            MOVS R0, #0x0       ; STL_OK
-_test_exit
-            POP {R4-R7}         ; Restore registers
-            BX LR               ; return
-
-            END

bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/EWARM/stl_test_full_ram_startup.s

@@ -1,186 +0,0 @@
-;/*****************************************************************************
-; * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
-; *
-; * This software component is licensed by XHSC under BSD 3-Clause license
-; * (the "License"); You may not use this file except in compliance with the
-; * License. You may obtain a copy of the License at:
-; *                    opensource.org/licenses/BSD-3-Clause
-; *
-; */
-;/****************************************************************************/
-;/*  Test for IAR                                                            */
-;/*  Version     V1.0                                                        */
-;/*  Date        2022-03-31                                                  */
-;/****************************************************************************/
-            SECTION constdata:CONST(2)
-data0x00000000       DCD     0x00000000
-data0xFFFFFFFF       DCD     0xFFFFFFFF
-
-            ; Exported function
-            EXPORT STL_FullRamTestStartup
-
-;*******************************************************************************
-; Function Name  : STL_FullRamTestStartup
-; Description    : Full RAM test at start-up
-; Input          : R0 .. RAM begin address
-;                  R1 .. RAM end address
-; Return         : STL_OK (=0):test pass; STL_ERR (=1):test fail;
-; WARNING        : all registers destroyed when exiting this function (including
-;                  preserved registers R4 to R11) and excluding stack point R13)
-;*******************************************************************************/
-            THUMB
-            SECTION .text:CODE(2)
-STL_FullRamTestStartup:
-            MOVS  R4, #0x0               ; STL_OK:Test success status by default
-
-            LDR   R2, =data0x00000000    ; Prepares background pattern
-            LDR   R2, [R2]
-            LDR   R3, =data0xFFFFFFFF    ; Prepares inverted background pattern
-            LDR   R3, [R3]
-
-            ; *** Step 1 ***
-            ; Write background pattern with addresses increasing
-            MOVS  R5, R0
-_step1_loop:
-            CMP   R5, R1
-            BHI   _step_2
-            STR   R2, [R5, #+0]
-            ADDS  R5, R5, #+4
-            B     _step1_loop
-
-            ; *** Step 2 ***
-            ; Verify background and write inverted background with addresses increasing
-_step_2:
-            MOVS  R5, R0
-_step_2_loop:
-            CMP   R5, R1
-            BHI   _step_3
-            LDR   R6, [R5, #+0]
-            CMP   R6, R2
-            BNE   _full_ram1_test_fail
-            STR   R3, [R5, #+0]
-            LDR   R6, [R5, #+4]
-            CMP   R6, R2
-            BNE   _full_ram1_test_fail
-            STR   R3, [R5, #+4]
-
-            LDR   R6, [R5, #+8]
-            CMP   R6, R2
-            BNE   _full_ram1_test_fail
-            STR   R3, [R5, #+8]
-            LDR   R6, [R5, #+12]
-            CMP   R6, R2
-            BNE   _full_ram1_test_fail
-            STR   R3, [R5, #+12]
-
-            ADDS  R5, R5, #+16
-            B     _step_2_loop
-
-            ; *** Step 3 ***
-            ; Verify inverted background and write background with addresses increasing
-_step_3:
-            MOVS  R5, R0
-_step_3_loop:
-            CMP   R5, R1
-            BHI   _step_4
-            LDR   R6, [R5, #+0]
-            CMP   R6, R3
-            BNE   _full_ram1_test_fail
-            STR   R2, [R5, #+0]
-            LDR   R6, [R5, #+4]
-            CMP   R6, R3
-            BNE   _full_ram1_test_fail
-            STR   R2, [R5, #+4]
-
-            LDR   R6, [R5, #+8]
-            CMP   R6, R3
-            BNE   _full_ram1_test_fail
-            STR   R2, [R5, #+8]
-            LDR   R6, [R5, #+12]
-            CMP   R6, R3
-            BNE   _full_ram1_test_fail
-            STR   R2, [R5, #+12]
-
-            ADDS  R5, R5, #+16
-            B     _step_3_loop
-
-            ; *** Step 4 ***
-            ; Verify background and write inverted background with addresses decreasing
-_step_4:
-            MOVS  R5, R1
-            SUBS  R5, R5, #+15
-_step_4_loop:
-            CMP   R5, R0
-            BLO   _step_5
-
-            LDR   R6, [R5, #+12]
-            CMP   R6, R2
-            BNE   _full_ram1_test_fail
-            STR   R3, [R5, #+12]
-            LDR   R6, [R5, #+8]
-            CMP   R6, R2
-            BNE   _full_ram1_test_fail
-            STR   R3, [R5, #+8]
-
-            LDR   R6, [R5, #+4]
-            CMP   R6, R2
-            BNE   _full_ram1_test_fail
-            STR   R3, [R5, #+4]
-            LDR   R6, [R5, #+0]
-            CMP   R6, R2
-            BNE   _full_ram1_test_fail
-            STR   R3, [R5, #+0]
-
-            SUBS  R5, R5, #+16
-            B     _step_4_loop
-
-            ; *** Step 5 ***
-            ; Verify inverted background and write background with addresses decreasing
-_step_5:
-            MOVS  R5, R1
-            SUBS  R5, R5, #+15
-_step_5_loop:
-            CMP   R5, R0
-            BLO   _step_6
-
-            LDR   R6, [R5, #+12]
-            CMP   R6, R3
-            BNE   _full_ram1_test_fail
-            STR   R2, [R5, #+12]
-            LDR   R6, [R5, #+8]
-            CMP   R6, R3
-            BNE   _full_ram1_test_fail
-            STR   R2, [R5, #+8]
-
-            LDR   R6, [R5, #+4]
-            CMP   R6, R3
-            BNE   _full_ram1_test_fail
-            STR   R2, [R5, #+4]
-            LDR   R6, [R5, #+0]
-            CMP   R6, R3
-            BNE   _full_ram1_test_fail
-            STR   R2, [R5, #+0]
-            SUBS  R5, R5, #+16
-            B     _step_5_loop
-
-            ; *** Step 6 ***
-            ; Verify background with addresses increasing
-_step_6:
-            MOVS  R5, R0
-_step_6_loop:
-            CMP   R5, R1
-            BHI   _full_ram1_test_pass
-            LDR   R6, [R5, #+0]
-            CMP   R6, R2
-            BNE   _full_ram1_test_fail
-            ADDS  R5, R5, #+4
-            B     _step_6_loop
-
-_full_ram1_test_fail:
-            MOVS  R4, #1      ; STL_ERR
-
-_full_ram1_test_pass:
-            MOVS  R0, R4
-            BX    LR          ; return to the caller
-
-            END

bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/EWARM/stl_test_pc.s

@@ -1,148 +0,0 @@
-;/*****************************************************************************
-; * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
-; *
-; * This software component is licensed by XHSC under BSD 3-Clause license
-; * (the "License"); You may not use this file except in compliance with the
-; * License. You may obtain a copy of the License at:
-; *                    opensource.org/licenses/BSD-3-Clause
-; *
-; */
-;/****************************************************************************/
-;/*  Test for IAR                                                            */
-;/*  Date             Author          Notes                                  */
-;/*  2022-03-31       CDT             First version                          */
-;/*  2023-05-31       CDT             Typo: subrouitne -> subroutine         */
-;/****************************************************************************/
-
-                ; Exported function
-                EXPORT STL_PcTest
-
-;*******************************************************************************
-; Function Name  : STL_PcTest
-; Description    : Test PC
-; Input          : None.
-; Output         : Perform routine when detect failure at set of self test cases
-; Return         : STL_OK (=0):test pass; STL_ERR (=1):test fail;
-; WARNING        : all registers destroyed when exiting this function (including
-;                  preserved registers R4 to R11) and excluding stack point R13)
-;*******************************************************************************/
-
-            SECTION .text:CODE(2)
-            THUMB
-STL_PcTest
-            PUSH {R4-R7}            ; Save registers
-            MOVS R0, #0
-            MOVS R1, #0             ; clr R0,R1
-            MOV  R3, LR
-
-_subroutine_1
-            LDR R0, =_return_pc_test_addr_1
-            BL  _return_pc_test_addr_1
-            CMP R0, R1              ; verify return address?
-            BEQ _subroutine_2
-            B _pc_test_fail
-
-_subroutine_2
-            LDR R0, =_return_pc_test_addr_2
-            BL  _return_pc_test_addr_2
-            CMP R0, R1              ; verify return address?
-            BEQ _subroutine_3
-            B _pc_test_fail
-
-_subroutine_3
-            LDR R0, =_return_pc_test_addr_3
-            BL  _return_pc_test_addr_3
-            CMP R0, R1              ; verify return address?
-            BEQ _subroutine_4
-            B _pc_test_fail
-
-_subroutine_4
-            LDR R0, =_return_pc_test_addr_4
-            BL  _return_pc_test_addr_4
-            CMP R0, R1              ; verify return address?
-            BEQ _subroutine_5
-            B _pc_test_fail
-
-_subroutine_5
-            LDR R0, =_return_pc_test_addr_5
-            BL  _return_pc_test_addr_5
-            CMP R0, R1              ; verify return address?
-            BEQ _subroutine_6
-            B _pc_test_fail
-
-_subroutine_6
-            LDR R0, =_return_pc_test_addr_6
-            BL  _return_pc_test_addr_6
-            CMP R0, R1              ; verify return address?
-            BEQ _subroutine_7
-            B _pc_test_fail
-
-_subroutine_7
-            LDR R0, =_return_pc_test_addr_7
-            BL  _return_pc_test_addr_7
-            CMP R0, R1              ; verify return address?
-            BEQ _subroutine_8
-            B _pc_test_fail
-
-_subroutine_8
-            LDR R0, =_return_pc_test_addr_8
-            BL  _return_pc_test_addr_8
-            CMP R0, R1              ; verify return address?
-            BEQ _pc_test_pass
-            B _pc_test_fail
-
-_pc_test_fail
-            ; when test fail, R0 will hold value 1
-            MOVS R0, #0x1           ; STL_ERR
-            B _pc_test_exit
-
-_pc_test_pass
-            ; when test pass, R0 will hold value 0
-            MOVS R0, #0x0           ; STL_OK
-            B _pc_test_exit
-
-_pc_test_exit:
-            POP {R4-R7}             ; Restore registers
-            BX R3                   ; return
-
-            SECTION .pctestaddr1:CODE(2)
-_return_pc_test_addr_1
-            LDR R1, =_return_pc_test_addr_1     ; store subroutine address in R1
-            BX LR
-
-            SECTION .pctestaddr2:CODE(2)
-_return_pc_test_addr_2
-            LDR R1, =_return_pc_test_addr_2     ; store subroutine address in R1
-            BX LR
-
-            SECTION .pctestaddr3:CODE(2)
-_return_pc_test_addr_3
-            LDR R1, =_return_pc_test_addr_3     ; store subroutine address in R1
-            BX LR
-
-            SECTION .pctestaddr4:CODE(2)
-_return_pc_test_addr_4
-            LDR R1, =_return_pc_test_addr_4     ; store subroutine address in R1
-            BX LR
-
-            SECTION .pctestaddr5:CODE(2)
-_return_pc_test_addr_5
-            LDR R1, =_return_pc_test_addr_5     ; store subroutine address in R1
-            BX LR
-
-            SECTION .pctestaddr6:CODE(2)
-_return_pc_test_addr_6
-            LDR R1, =_return_pc_test_addr_6     ; store subroutine address in R1
-            BX LR
-
-            SECTION .pctestaddr7:CODE(2)
-_return_pc_test_addr_7
-            LDR R1, =_return_pc_test_addr_7     ; store subroutine address in R1
-            BX LR
-
-            SECTION .pctestaddr8:CODE(2)
-_return_pc_test_addr_8
-            LDR R1, =_return_pc_test_addr_8     ; store subroutine address in R1
-            BX LR
-
-            END

bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/MDK/stl_test_cpu_cm0_startup.s

@@ -1,378 +0,0 @@
-;/*****************************************************************************
-; * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
-; *
-; * This software component is licensed by XHSC under BSD 3-Clause license
-; * (the "License"); You may not use this file except in compliance with the
-; * License. You may obtain a copy of the License at:
-; *                    opensource.org/licenses/BSD-3-Clause
-; *
-; */
-;/****************************************************************************/
-;/*  Test for MDK                                                            */
-;/*  Version     V1.0                                                        */
-;/*  Date        2022-09-14                                                  */
-;/****************************************************************************/
-
-    THUMB
-    REQUIRE8
-    PRESERVE8
-
-    AREA |.text|, CODE, READONLY, ALIGN=2
-
-data0xAAAAAAAA       DCD     0xAAAAAAAA
-data0x55555555       DCD     0x55555555
-data0x80000000       DCD     0x80000000
-data0xAAAAAAA8       DCD     0xAAAAAAA8
-data0x55555554       DCD     0x55555554
-data0x00000000       DCD     0x00000000
-data0x00000001       DCD     0x00000001
-data0x50000000       DCD     0x50000000
-data0xA0000000       DCD     0xA0000000
-
-;*******************************************************************************
-; Function Name  : STL_CpuTestStartup
-; Description    : Test CPU at start-up
-; Input          : None.
-; Output         : Perform routine when detect failure at set of self test cases
-; Return         : STL_OK (=0):test pass; STL_ERR (=1):test fail;
-; WARNING        : all registers destroyed when exiting this function (including
-;                  preserved registers R4 to R11) and excluding stack point R13)
-;*******************************************************************************/
-STL_CpuTestStartup PROC
-            EXPORT STL_CpuTestStartup
-
-            PUSH {R4-R7}                         ; Save registers
-
-_test_cpu_reg0_reg8
-            MOVS R0, #0x00
-            UXTB R0, R0
-            ADDS R0, #0                          ; Set Z(ero) Flag
-            BNE _test_cpu_reg0_reg13_fail        ; Fails if Z clear
-            BMI _test_cpu_reg0_reg13_fail        ; Fails if N is set
-            SUBS R0, #1                          ; Set N(egative) Flag
-            BPL _test_cpu_reg0_reg13_fail        ; Fails if N clear
-            ADDS R0, #2                          ; Set C(arry) Flag and do not set Z
-            BCC _test_cpu_reg0_reg13_fail        ; Fails if C clear
-            BEQ _test_cpu_reg0_reg13_fail        ; Fails if Z is set
-            BMI _test_cpu_reg0_reg13_fail        ; Fails if N is set
-
-            LDR R0, =data0x80000000              ; Prepares Overflow test
-            LDR R0, [R0]
-            ADDS R0, R0, R0                      ; Set V(overflow) Flag
-            BVC _test_cpu_reg0_reg13_fail        ; Fails if V clear
-
-            ; Register R1
-            LDR R0, =data0xAAAAAAAA
-            LDR R1, [R0]
-            LDR R0, [R0]
-            CMP R0, R1
-            BNE _test_cpu_reg0_reg13_fail
-            LDR R0, =data0x55555555
-            LDR R1, [R0]
-            LDR R0, [R0]
-            CMP R0, R1
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R1, #0x1
-
-            ; Register R2
-            LDR R0, =data0xAAAAAAAA
-            LDR R2, [R0]
-            LDR R0, [R0]
-            CMP R0, R2
-            BNE _test_cpu_reg0_reg13_fail
-            LDR R0, =data0x55555555
-            LDR R2, [R0]
-            LDR R0, [R0]
-            CMP R0, R2
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R2, #0x2
-
-            ; Register R3
-            LDR R0, =data0xAAAAAAAA
-            LDR R3, [R0]
-            LDR R0, [R0]
-            CMP R0, R3
-            BNE _test_cpu_reg0_reg13_fail
-            LDR R0, =data0x55555555
-            LDR R3, [R0]
-            LDR R0, [R0]
-            CMP R0, R3
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R3, #0x3
-
-            ; Register R4
-            LDR R0, =data0xAAAAAAAA
-            LDR R4, [R0]
-            LDR R0, [R0]
-            CMP R0, R4
-            BNE _test_cpu_reg0_reg13_fail
-            LDR R0, =data0x55555555
-            LDR R4, [R0]
-            LDR R0, [R0]
-            CMP R0, R4
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R4, #0x4
-
-            ; Register R5
-            LDR R0, =data0xAAAAAAAA
-            LDR R5, [R0]
-            LDR R0, [R0]
-            CMP R0, R5
-            BNE _test_cpu_reg0_reg13_fail
-            LDR R0, =data0x55555555
-            LDR R5, [R0]
-            LDR R0, [R0]
-            CMP R0, R5
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R5, #0x5
-
-            ; Register R6
-            LDR R0, =data0xAAAAAAAA
-            LDR R6, [R0]
-            LDR R0, [R0]
-            CMP R0, R6
-            BNE _test_cpu_reg0_reg13_fail
-            LDR R0, =data0x55555555
-            LDR R6, [R0]
-            LDR R0, [R0]
-            CMP R0, R6
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R6, #0x6
-
-            ; Register R7
-            LDR R0, =data0xAAAAAAAA
-            LDR R7, [R0]
-            LDR R0, [R0]
-            CMP R0, R7
-            BNE _test_cpu_reg0_reg13_fail
-            LDR R0, =data0x55555555
-            LDR R7, [R0]
-            LDR R0, [R0]
-            CMP R0, R7
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R7, #0x7
-
-            ; Register R8
-            LDR R0, =data0xAAAAAAAA
-            LDR R0, [R0]
-            MOV R8, R0
-            CMP R0, R8
-            BNE _test_cpu_reg0_reg13_fail
-            LDR R0, =data0x55555555
-            LDR R0, [R0]
-            MOV R8, R0
-            CMP R0, R8
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R0, #0x08
-            MOV R8, R0
-
-            BAL _test_cpu_continue
-
-_test_cpu_reg0_reg13_fail
-            ; test fail, R0 will hold value 1
-            MOVS R0, #0x1                        ; STL_ERR
-            B _test_exit
-
-_test_cpu_continue
-            ; Register R9
-            LDR R0, =data0xAAAAAAAA
-            LDR R0, [R0]
-            MOV R9, R0
-            CMP R0, R9
-            BNE _test_cpu_reg0_reg13_fail
-            LDR R0, =data0x55555555
-            LDR R0, [R0]
-            MOV R9, R0
-            CMP R0, R9
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R0, #0x09
-            MOV R9, R0
-
-            ; Register R10
-            LDR R0, =data0xAAAAAAAA
-            LDR R0, [R0]
-            MOV R10, R0
-            CMP R0, R10
-            BNE _test_cpu_reg0_reg13_fail
-            LDR R0, =data0x55555555
-            LDR R0, [R0]
-            MOV R10, R0
-            CMP R0, R10
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R0, #0x0A
-            MOV R10, R0
-
-            ; Register R11
-            LDR R0, =data0xAAAAAAAA
-            LDR R0, [R0]
-            MOV R11, R0
-            CMP R0, R11
-            BNE _test_cpu_reg0_reg13_fail
-            LDR R0, =data0x55555555
-            LDR R0, [R0]
-            MOV R11, R0
-            CMP R0, R11
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R0, #0x0B
-            MOV R11, R0
-
-            ; Register R12
-            LDR R0, =data0xAAAAAAAA
-            LDR R0, [R0]
-            MOV R12, R0
-            CMP R0, R12
-            BNE _test_cpu_reg0_reg13_fail
-            LDR R0, =data0x55555555
-            LDR R0, [R0]
-            MOV R12, R0
-            CMP R0, R12
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R0, #0x0C
-            MOV R12, R0
-            LDR R0, =_test_cpu_continue
-
-            ; pattern verification (R0 is not tested)
-            CMP R1, #0x01
-            BNE _test_cpu_reg0_reg13_fail
-            CMP R2, #0x02
-            BNE _test_cpu_reg0_reg13_fail
-            CMP R3, #0x03
-            BNE _test_cpu_reg0_reg13_fail
-            CMP R4, #0x04
-            BNE _test_cpu_reg0_reg13_fail
-            CMP R5, #0x05
-            BNE _test_cpu_reg0_reg13_fail
-            CMP R6, #0x06
-            BNE _test_cpu_reg0_reg13_fail
-            CMP R7, #0x07
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R0, #0x08
-            CMP R0, R8
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R0, #0x09
-            CMP R0, R9
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R0, #0x0A
-            CMP R0, R10
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R0, #0x0B
-            CMP R0, R11
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R0, #0x0C
-            CMP R0, R12
-            BNE _test_cpu_reg0_reg13_fail
-
-            ; Process Stack pointer (banked Register R13)
-            MRS R0, PSP                          ; Save process stack value
-            LDR R1, =data0xAAAAAAA8              ; Test is different (PSP is word aligned, 2 LSB cleared)
-            LDR R1, [R1]
-            MSR PSP, R1                          ; load process stack value
-            MRS R2, PSP                          ; Get back process stack value
-            CMP R2, R1                           ; Verify value
-            BNE _test_cpu_reg0_reg13_fail
-            LDR R1, =data0x55555554              ; Test is different (PSP is word aligned, 2 LSB cleared)
-            LDR R1, [R1]
-            MSR PSP, R1                          ; load process stack value
-            MRS R2, PSP                          ; Get back process stack value
-            CMP R2, R1                           ; Verify value
-            BNE _test_cpu_reg0_reg13_fail
-            MSR PSP, R0                          ; Restore process stack value
-
-            ; Stack pointer (Register R13)
-            MRS R0, MSP                          ; Save stack pointer value
-            LDR R1, =data0xAAAAAAA8              ; Test is different (SP is word aligned, 2 LSB cleared)
-            LDR R1, [R1]
-            MSR MSP, R1                          ; load SP value
-            MRS R2, MSP                          ; Get back SP value
-            CMP R2, R1                           ; Verify value
-            BNE _test_cpu_reg0_reg13_fail
-            LDR R1, =data0x55555554
-            LDR R1, [R1]                         ; load SP value
-            MSR MSP, R1                          ; Get back SP value
-            MRS R2, MSP                          ; Verify value
-            CMP R2, R1
-            BNE _test_cpu_reg0_reg13_fail
-            MSR MSP, R0                          ; Restore stack pointer value
-
-_test_cpu_r14_sfr
-            ; Link register R14
-            MOV R1, LR
-            LDR R0, =data0x55555555
-            LDR R0, [R0]
-            MOV R14, R0
-            CMP R0, R14
-            BNE _test_cpu_r14_sfr_fail
-
-            LDR R0, =data0xAAAAAAAA
-            LDR R0, [R0]
-            MOV R14, R0
-            CMP R0, R14
-            BNE _test_cpu_r14_sfr_fail
-
-            LDR R0, =data0x55555555
-            LDR R0, [R0]
-            MOV R14, R0
-            CMP R0, R14
-            BNE _test_cpu_r14_sfr_fail
-
-            LDR R0, =data0xAAAAAAAA
-            LDR R0, [R0]
-            MOV R14, R0
-            CMP R0, R14
-            BNE _test_cpu_r14_sfr_fail
-            MOV LR, R1
-
-            ; APSR
-            MRS R0, APSR
-            LDR R1, =data0x50000000
-            LDR R1,[R1]
-            MSR APSR,R1
-            MRS R2, APSR
-            CMP R1, R2
-            BNE _test_cpu_r14_sfr_fail
-
-            LDR R1, =data0xA0000000
-            LDR R1,[R1]
-            MSR APSR,R1
-            MRS R2, APSR
-            CMP R1, R2
-            BNE _test_cpu_r14_sfr_fail
-            MSR APSR,R0
-
-            ; PRIMASK register
-            MRS R0, PRIMASK
-            LDR R1, =data0x00000000
-            LDR R1, [R1]
-            MSR PRIMASK, R1
-            MRS R2, PRIMASK
-            CMP R1, R2
-            BNE _test_cpu_r14_sfr_fail
-
-            LDR R1, =data0x00000001
-            LDR R1, [R1]
-            MSR PRIMASK, R1
-            MRS R2, PRIMASK
-            CMP R1, R2
-            BNE _test_cpu_r14_sfr_fail
-            MSR PRIMASK, R0
-            B _test_cpu_pass
-
-_test_cpu_r14_sfr_fail
-            ; test fail, R0 will hold value 1
-            MOVS R0, #0x1                        ; STL_ERR
-            B _test_exit
-
-_test_cpu_pass
-            ; test pass, R0 will hold value 0
-            MOVS R0, #0x0                        ; STL_OK
-            B _test_exit
-
-_test_exit
-            POP {R4-R7}                          ; Restore registers
-            BX LR
-
-            ENDP
-
-            ALIGN
-
-            END

bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/MDK/stl_test_cpu_cm4_startup.s

@@ -1,426 +0,0 @@
-;/*****************************************************************************
-; * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
-; *
-; * This software component is licensed by XHSC under BSD 3-Clause license
-; * (the "License"); You may not use this file except in compliance with the
-; * License. You may obtain a copy of the License at:
-; *                    opensource.org/licenses/BSD-3-Clause
-; *
-; */
-;/****************************************************************************/
-;/*  Test for MDK                                                            */
-;/*  Date             Author          Notes                                  */
-;/*  2022-09-14       CDT             First version                          */
-;/*  2022-12-20       CDT             Load data to R0 before USAT            */
-;/*  2023-05-31       CDT             Typo: Veriry -> Verify                 */
-;/****************************************************************************/
-
-    THUMB
-    REQUIRE8
-    PRESERVE8
-
-    AREA |.text|, CODE, READONLY, ALIGN=2
-
-data0xAAAAAAAA       DCD     0xAAAAAAAA
-data0x55555555       DCD     0x55555555
-data0x80000000       DCD     0x80000000
-data0xAAAAAAA8       DCD     0xAAAAAAA8
-data0x55555554       DCD     0x55555554
-data0x00000000       DCD     0x00000000
-data0x00000001       DCD     0x00000001
-data0x50000000       DCD     0x50000000
-data0xA8000000       DCD     0xA8000000
-data0x00000050       DCD     0x00000050
-data0x000000A0       DCD     0x000000A0
-data0xFFFFFFFF       DCD     0xFFFFFFFF
-
-;*******************************************************************************
-; Function Name  : STL_CpuTestStartup
-; Description    : Test CPU at start-up
-; Input          : None.
-; Output         : Perform routine when detect failure at set of self test cases
-; Return         : STL_OK (=0):test pass; STL_ERR (=1):test fail;
-; WARNING        : all registers destroyed when exiting this function (including
-;                  preserved registers R4 to R11) and excluding stack point R13)
-;*******************************************************************************/
-STL_CpuTestStartup PROC
-            EXPORT STL_CpuTestStartup
-
-            PUSH {R4-R7}                         ; Save registers
-
-_test_cpu_reg0_reg8
-            MOVS R0, #0x00
-            UXTB R0, R0
-            ADDS R0, #0                          ; Set Z(ero) Flag
-            BNE _test_cpu_reg0_reg13_fail        ; Fails if Z clear
-            BMI _test_cpu_reg0_reg13_fail        ; Fails if N is set
-            SUBS R0, #1                          ; Set N(egative) Flag
-            BPL _test_cpu_reg0_reg13_fail        ; Fails if N clear
-            ADDS R0, #2                          ; Set C(arry) Flag and do not set Z
-            BCC _test_cpu_reg0_reg13_fail        ; Fails if C clear
-            BEQ _test_cpu_reg0_reg13_fail        ; Fails if Z is set
-            BMI _test_cpu_reg0_reg13_fail        ; Fails if N is set
-
-            LDR R0, =data0x80000000              ; Prepares Overflow test
-            LDR R0, [R0]
-            ADDS R0, R0, R0                      ; Set V(overflow) Flag
-            BVC _test_cpu_reg0_reg13_fail        ; Fails if V clear
-
-            MOV R0, #0
-            MSR APSR, R0
-            LDR R0, =data0xFFFFFFFF              ; Prepares Saturation test
-            LDR R0, [R0]
-            USAT R1, #10, R0                     ; Set Q(saturation) flag
-            MRS R0, APSR                         ; Get APSR status register
-            CMP R0, #0x08000000                  ; Verify Q=1
-            BNE _test_cpu_reg0_reg13_fail        ; Fails if Q is set
-
-            ; Register R1
-            LDR R0, =data0xAAAAAAAA
-            LDR R1, [R0]
-            LDR R0, [R0]
-            CMP R0, R1
-            BNE _test_cpu_reg0_reg13_fail
-            LDR R0, =data0x55555555
-            LDR R1, [R0]
-            LDR R0, [R0]
-            CMP R0, R1
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R1, #0x1
-
-            ; Register R2
-            LDR R0, =data0xAAAAAAAA
-            LDR R2, [R0]
-            LDR R0, [R0]
-            CMP R0, R2
-            BNE _test_cpu_reg0_reg13_fail
-            LDR R0, =data0x55555555
-            LDR R2, [R0]
-            LDR R0, [R0]
-            CMP R0, R2
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R2, #0x2
-
-            ; Register R3
-            LDR R0, =data0xAAAAAAAA
-            LDR R3, [R0]
-            LDR R0, [R0]
-            CMP R0, R3
-            BNE _test_cpu_reg0_reg13_fail
-            LDR R0, =data0x55555555
-            LDR R3, [R0]
-            LDR R0, [R0]
-            CMP R0, R3
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R3, #0x3
-
-            ; Register R4
-            LDR R0, =data0xAAAAAAAA
-            LDR R4, [R0]
-            LDR R0, [R0]
-            CMP R0, R4
-            BNE _test_cpu_reg0_reg13_fail
-            LDR R0, =data0x55555555
-            LDR R4, [R0]
-            LDR R0, [R0]
-            CMP R0, R4
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R4, #0x4
-
-            ; Register R5
-            LDR R0, =data0xAAAAAAAA
-            LDR R5, [R0]
-            LDR R0, [R0]
-            CMP R0, R5
-            BNE _test_cpu_reg0_reg13_fail
-            LDR R0, =data0x55555555
-            LDR R5, [R0]
-            LDR R0, [R0]
-            CMP R0, R5
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R5, #0x5
-
-            ; Register R6
-            LDR R0, =data0xAAAAAAAA
-            LDR R6, [R0]
-            LDR R0, [R0]
-            CMP R0, R6
-            BNE _test_cpu_reg0_reg13_fail
-            LDR R0, =data0x55555555
-            LDR R6, [R0]
-            LDR R0, [R0]
-            CMP R0, R6
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R6, #0x6
-
-            ; Register R7
-            LDR R0, =data0xAAAAAAAA
-            LDR R7, [R0]
-            LDR R0, [R0]
-            CMP R0, R7
-            BNE _test_cpu_reg0_reg13_fail
-            LDR R0, =data0x55555555
-            LDR R7, [R0]
-            LDR R0, [R0]
-            CMP R0, R7
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R7, #0x7
-
-            ; Register R8
-            LDR R0, =data0xAAAAAAAA
-            LDR R0, [R0]
-            MOV R8, R0
-            CMP R0, R8
-            BNE _test_cpu_reg0_reg13_fail
-            LDR R0, =data0x55555555
-            LDR R0, [R0]
-            MOV R8, R0
-            CMP R0, R8
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R0, #0x08
-            MOV R8, R0
-
-            BAL _test_cpu_continue
-
-_test_cpu_reg0_reg13_fail
-            ; test fail, R0 will hold value 1
-            MOVS R0, #0x1                        ; STL_ERR
-            B _test_exit
-
-_test_cpu_continue
-            ; Register R9
-            LDR R0, =data0xAAAAAAAA
-            LDR R0, [R0]
-            MOV R9, R0
-            CMP R0, R9
-            BNE _test_cpu_reg0_reg13_fail
-            LDR R0, =data0x55555555
-            LDR R0, [R0]
-            MOV R9, R0
-            CMP R0, R9
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R0, #0x09
-            MOV R9, R0
-
-            ; Register R10
-            LDR R0, =data0xAAAAAAAA
-            LDR R0, [R0]
-            MOV R10, R0
-            CMP R0, R10
-            BNE _test_cpu_reg0_reg13_fail
-            LDR R0, =data0x55555555
-            LDR R0, [R0]
-            MOV R10, R0
-            CMP R0, R10
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R0, #0x0A
-            MOV R10, R0
-
-            ; Register R11
-            LDR R0, =data0xAAAAAAAA
-            LDR R0, [R0]
-            MOV R11, R0
-            CMP R0, R11
-            BNE _test_cpu_reg0_reg13_fail
-            LDR R0, =data0x55555555
-            LDR R0, [R0]
-            MOV R11, R0
-            CMP R0, R11
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R0, #0x0B
-            MOV R11, R0
-
-            ; Register R12
-            LDR R0, =data0xAAAAAAAA
-            LDR R0, [R0]
-            MOV R12, R0
-            CMP R0, R12
-            BNE _test_cpu_reg0_reg13_fail
-            LDR R0, =data0x55555555
-            LDR R0, [R0]
-            MOV R12, R0
-            CMP R0, R12
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R0, #0x0C
-            MOV R12, R0
-            LDR R0, =_test_cpu_continue
-
-            ; pattern verification (R0 is not tested)
-            CMP R1, #0x01
-            BNE _test_cpu_reg0_reg13_fail
-            CMP R2, #0x02
-            BNE _test_cpu_reg0_reg13_fail
-            CMP R3, #0x03
-            BNE _test_cpu_reg0_reg13_fail
-            CMP R4, #0x04
-            BNE _test_cpu_reg0_reg13_fail
-            CMP R5, #0x05
-            BNE _test_cpu_reg0_reg13_fail
-            CMP R6, #0x06
-            BNE _test_cpu_reg0_reg13_fail
-            CMP R7, #0x07
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R0, #0x08
-            CMP R0, R8
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R0, #0x09
-            CMP R0, R9
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R0, #0x0A
-            CMP R0, R10
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R0, #0x0B
-            CMP R0, R11
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R0, #0x0C
-            CMP R0, R12
-            BNE _test_cpu_reg0_reg13_fail
-
-            ; Process Stack pointer (banked Register R13)
-            MRS R0, PSP                          ; Save process stack value
-            LDR R1, =data0xAAAAAAA8              ; Test is different (PSP is word aligned, 2 LSB cleared)
-            LDR R1, [R1]
-            MSR PSP, R1                          ; load process stack value
-            MRS R2, PSP                          ; Get back process stack value
-            CMP R2, R1                           ; Verify value
-            BNE _test_cpu_reg0_reg13_fail
-            LDR R1, =data0x55555554              ; Test is different (PSP is word aligned, 2 LSB cleared)
-            LDR R1, [R1]
-            MSR PSP, R1                          ; load process stack value
-            MRS R2, PSP                          ; Get back process stack value
-            CMP R2, R1                           ; Verify value
-            BNE _test_cpu_reg0_reg13_fail
-            MSR PSP, R0                          ; Restore process stack value
-
-            ; Stack pointer (Register R13)
-            MRS R0, MSP                          ; Save stack pointer value
-            LDR R1, =data0xAAAAAAA8              ; Test is different (SP is word aligned, 2 LSB cleared)
-            LDR R1, [R1]
-            MSR MSP, R1                          ; load SP value
-            MRS R2, MSP                          ; Get back SP value
-            CMP R2, R1                           ; Verify value
-            BNE _test_cpu_reg0_reg13_fail
-            LDR R1, =data0x55555554
-            LDR R1, [R1]                         ; load SP value
-            MSR MSP, R1                          ; Get back SP value
-            MRS R2, MSP                          ; Verify value
-            CMP R2, R1
-            BNE _test_cpu_reg0_reg13_fail
-            MSR MSP, R0                          ; Restore stack pointer value
-
-_test_cpu_r14_sfr
-            ; Link register R14
-            MOV R1, LR
-            LDR R0, =data0x55555555
-            LDR R0, [R0]
-            MOV R14, R0
-            CMP R0, R14
-            BNE _test_cpu_r14_sfr_fail
-
-            LDR R0, =data0xAAAAAAAA
-            LDR R0, [R0]
-            MOV R14, R0
-            CMP R0, R14
-            BNE _test_cpu_r14_sfr_fail
-
-            LDR R0, =data0x55555555
-            LDR R0, [R0]
-            MOV R14, R0
-            CMP R0, R14
-            BNE _test_cpu_r14_sfr_fail
-
-            LDR R0, =data0xAAAAAAAA
-            LDR R0, [R0]
-            MOV R14, R0
-            CMP R0, R14
-            BNE _test_cpu_r14_sfr_fail
-            MOV LR, R1
-
-            ; APSR
-            MRS R0, APSR
-            LDR R1, =data0x50000000
-            LDR R1,[R1]
-            MSR APSR,R1
-            MRS R2, APSR
-            CMP R1, R2
-            BNE _test_cpu_r14_sfr_fail
-
-            LDR R1, =data0xA8000000
-            LDR R1,[R1]
-            MSR APSR,R1
-            MRS R2, APSR
-            CMP R1, R2
-            BNE _test_cpu_r14_sfr_fail
-            MSR APSR,R0
-
-            ; PRIMASK register
-            MRS R0, PRIMASK
-            LDR R1, =data0x00000000
-            LDR R1, [R1]
-            MSR PRIMASK, R1
-            MRS R2, PRIMASK
-            CMP R1, R2
-            BNE _test_cpu_r14_sfr_fail
-
-            LDR R1, =data0x00000001
-            LDR R1, [R1]
-            MSR PRIMASK, R1
-            MRS R2, PRIMASK
-            CMP R1, R2
-            BNE _test_cpu_r14_sfr_fail
-            MSR PRIMASK, R0
-
-            ; FAULTMASK register
-            MRS R0, FAULTMASK
-            LDR R1, =data0x00000000
-            LDR R1, [R1]
-            MSR FAULTMASK, R1
-            MRS R2, FAULTMASK
-            CMP R1, R2
-            BNE _test_cpu_r14_sfr_fail
-
-            LDR R1, =data0x00000001
-            LDR R1, [R1]
-            MSR FAULTMASK, R1
-            MRS R2, FAULTMASK
-            CMP R1, R2
-            BNE _test_cpu_r14_sfr_fail
-            MSR FAULTMASK, R0
-
-            ; BASEPRI register
-            MRS R0, BASEPRI
-            LDR R1, =data0x000000A0
-            LDR R1, [R1]
-            MSR BASEPRI, R1
-            MRS R2, BASEPRI
-            CMP R1, R2
-            BNE _test_cpu_r14_sfr_fail
-
-            LDR R1, =data0x00000050
-            LDR R1, [R1]
-            MSR BASEPRI, R1
-            MRS R2, BASEPRI
-            CMP R1, R2
-            BNE _test_cpu_r14_sfr_fail
-            MSR BASEPRI, R0
-            B _test_cpu_pass
-
-_test_cpu_r14_sfr_fail
-            ; test fail, R0 will hold value 1
-            MOVS R0, #0x1                        ; STL_ERR
-            B _test_exit
-
-_test_cpu_pass
-            ; test pass, R0 will hold value 0
-            MOVS R0, #0x0                        ; STL_OK
-            B _test_exit
-
-_test_exit
-            POP {R4-R7}                          ; Restore registers
-            BX LR
-
-            ENDP
-
-            ALIGN
-
-            END

bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/MDK/stl_test_cpu_runtime.s

@@ -1,251 +0,0 @@
-;/*****************************************************************************
-; * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
-; *
-; * This software component is licensed by XHSC under BSD 3-Clause license
-; * (the "License"); You may not use this file except in compliance with the
-; * License. You may obtain a copy of the License at:
-; *                    opensource.org/licenses/BSD-3-Clause
-; *
-; */
-;/****************************************************************************/
-;/*  Test for MDK                                                            */
-;/*  Version     V1.0                                                        */
-;/*  Date        2022-03-31                                                  */
-;/****************************************************************************/
-
-    THUMB
-    REQUIRE8
-    PRESERVE8
-
-    AREA |.text|, CODE, READONLY, ALIGN=2
-
-data0xAAAAAAAA       DCD     0xAAAAAAAA
-data0x55555555       DCD     0x55555555
-
-;*******************************************************************************
-; Function Name  : STL_CpuTestRuntime
-; Description    : Test CPU at run-time
-; Input          : None.
-; Output         : Perform routine when detect failure at set of self test cases
-; Return         : STL_OK (=0):test pass; STL_ERR (=1):test fail;
-; WARNING        : all registers destroyed when exiting this function (including
-;                  preserved registers R4 to R11) and excluding stack point R13)
-;*******************************************************************************/
-STL_CpuTestRuntime PROC
-            EXPORT STL_CpuTestRuntime
-
-            PUSH {R4-R7}              ; Save registers
-
-            ; Register R1
-            LDR R0, =data0xAAAAAAAA
-            LDR R1, [R0]
-            LDR R0, [R0]
-            CMP R0, R1
-            BNE _test_cpu_fail
-            LDR R0, =data0x55555555
-            LDR R1, [R0]
-            LDR R0, [R0]
-            CMP R0, R1
-            BNE _test_cpu_fail
-            MOVS R1, #0x1
-
-            ; Register R2
-            LDR R0, =data0xAAAAAAAA
-            LDR R2, [R0]
-            LDR R0, [R0]
-            CMP R0, R2
-            BNE _test_cpu_fail
-            LDR R0, =data0x55555555
-            LDR R2, [R0]
-            LDR R0, [R0]
-            CMP R0, R2
-            BNE _test_cpu_fail
-            MOVS R2, #0x2
-
-            ; Register R3
-            LDR R0, =data0xAAAAAAAA
-            LDR R3, [R0]
-            LDR R0, [R0]
-            CMP R0, R3
-            BNE _test_cpu_fail
-            LDR R0, =data0x55555555
-            LDR R3, [R0]
-            LDR R0, [R0]
-            CMP R0, R3
-            BNE _test_cpu_fail
-            MOVS R3, #0x3
-
-            ; Register R4
-            LDR R0, =data0xAAAAAAAA
-            LDR R4, [R0]
-            LDR R0, [R0]
-            CMP R0, R4
-            BNE _test_cpu_fail
-            LDR R0, =data0x55555555
-            LDR R4, [R0]
-            LDR R0, [R0]
-            CMP R0, R4
-            BNE _test_cpu_fail
-            MOVS R4, #0x4
-
-            ; Register R5
-            LDR R0, =data0xAAAAAAAA
-            LDR R5, [R0]
-            LDR R0, [R0]
-            CMP R0, R5
-            BNE _test_cpu_fail
-            LDR R0, =data0x55555555
-            LDR R5, [R0]
-            LDR R0, [R0]
-            CMP R0, R5
-            BNE _test_cpu_fail
-            MOVS R5, #0x5
-
-            ; Register R6
-            LDR R0, =data0xAAAAAAAA
-            LDR R6, [R0]
-            LDR R0, [R0]
-            CMP R0, R6
-            BNE _test_cpu_fail
-            LDR R0, =data0x55555555
-            LDR R6, [R0]
-            LDR R0, [R0]
-            CMP R0, R6
-            BNE _test_cpu_fail
-            MOVS R6, #0x6
-
-            ; Register R7
-            LDR R0, =data0xAAAAAAAA
-            LDR R7, [R0]
-            LDR R0, [R0]
-            CMP R0, R7
-            BNE _test_cpu_fail
-            LDR R0, =data0x55555555
-            LDR R7, [R0]
-            LDR R0, [R0]
-            CMP R0, R7
-            BNE _test_cpu_fail
-            MOVS R7, #0x7
-
-            ; Register R8
-            LDR R0, =data0xAAAAAAAA
-            LDR R0, [R0]
-            MOV R8, R0
-            CMP R0, R8
-            BNE _test_cpu_fail
-            LDR R0, =data0x55555555
-            LDR R0, [R0]
-            MOV R8, R0
-            CMP R0, R8
-            BNE _test_cpu_fail
-            MOVS R0, #0x08
-            MOV R8, R0
-
-            BAL _test_cpu_continue
-
-_test_cpu_fail
-            ; test fail, R0 will hold value 1
-            MOVS R0, #0x1       ; STL_ERR
-            B _test_exit
-
-_test_cpu_continue
-            ; Register R9
-            LDR R0, =data0xAAAAAAAA
-            LDR R0, [R0]
-            MOV R9, R0
-            CMP R0, R9
-            BNE _test_cpu_fail
-            LDR R0, =data0x55555555
-            LDR R0, [R0]
-            MOV R9, R0
-            CMP R0, R9
-            BNE _test_cpu_fail
-            MOVS R0, #0x09
-            MOV R9, R0
-
-            ; Register R10
-            LDR R0, =data0xAAAAAAAA
-            LDR R0, [R0]
-            MOV R10, R0
-            CMP R0, R10
-            BNE _test_cpu_fail
-            LDR R0, =data0x55555555
-            LDR R0, [R0]
-            MOV R10, R0
-            CMP R0, R10
-            BNE _test_cpu_fail
-            MOVS R0, #0x0A
-            MOV R10, R0
-
-            ; Register R11
-            LDR R0, =data0xAAAAAAAA
-            LDR R0, [R0]
-            MOV R11, R0
-            CMP R0, R11
-            BNE _test_cpu_fail
-            LDR R0, =data0x55555555
-            LDR R0, [R0]
-            MOV R11, R0
-            CMP R0, R11
-            BNE _test_cpu_fail
-            MOVS R0, #0x0B
-            MOV R11, R0
-
-            ; Register R12
-            LDR R0, =data0xAAAAAAAA
-            LDR R0, [R0]
-            MOV R12, R0
-            CMP R0, R12
-            BNE _test_cpu_fail
-            LDR R0, =data0x55555555
-            LDR R0, [R0]
-            MOV R12, R0
-            CMP R0, R12
-            BNE _test_cpu_fail
-            MOVS R0, #0x0C
-            MOV R12, R0
-            LDR R0, =_test_cpu_continue
-
-            ; pattern verification  (R0 is not tested)
-            CMP R1, #0x01
-            BNE _test_cpu_fail
-            CMP R2, #0x02
-            BNE _test_cpu_fail
-            CMP R3, #0x03
-            BNE _test_cpu_fail
-            CMP R4, #0x04
-            BNE _test_cpu_fail
-            CMP R5, #0x05
-            BNE _test_cpu_fail
-            CMP R6, #0x06
-            BNE _test_cpu_fail
-            CMP R7, #0x07
-            BNE _test_cpu_fail
-            MOVS R0, #0x08
-            CMP R0, R8
-            BNE _test_cpu_fail
-            MOVS R0, #0x09
-            CMP R0, R9
-            BNE _test_cpu_fail
-            MOVS R0, #0x0A
-            CMP R0, R10
-            BNE _test_cpu_fail
-            MOVS R0, #0x0B
-            CMP R0, R11
-            BNE _test_cpu_fail
-            MOVS R0, #0x0C
-            CMP R0, R12
-            BNE _test_cpu_fail
-
-            ; Link register R14
-            ; test pass, R0 will hold value 0
-            MOVS R0, #0x0       ; STL_OK
-_test_exit
-            POP {R4-R7}         ; Restore registers
-            BX LR               ; return
-
-            ENDP
-
-            ALIGN
-
-            END

bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/MDK/stl_test_full_ram_startup.s

@@ -1,191 +0,0 @@
-;/*****************************************************************************
-; * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
-; *
-; * This software component is licensed by XHSC under BSD 3-Clause license
-; * (the "License"); You may not use this file except in compliance with the
-; * License. You may obtain a copy of the License at:
-; *                    opensource.org/licenses/BSD-3-Clause
-; *
-; */
-;/****************************************************************************/
-;/*  Test for MDK                                                            */
-;/*  Version     V1.0                                                        */
-;/*  Date        2022-03-31                                                  */
-;/****************************************************************************/
-    THUMB
-    REQUIRE8
-    PRESERVE8
-
-    AREA |.text|, CODE, READONLY, ALIGN=2
-data0x00000000       DCD     0x00000000
-data0xFFFFFFFF       DCD     0xFFFFFFFF
-
-;*******************************************************************************
-; Function Name  : STL_FullRamTestStartup
-; Description    : Full RAM test at start-up
-; Input          : R0 .. RAM begin address
-;                  R1 .. RAM end address
-; Return         : STL_OK (=0):test pass; STL_ERR (=1):test fail;
-; WARNING        : all registers destroyed when exiting this function (including
-;                  preserved registers R4 to R11) and excluding stack point R13)
-;*******************************************************************************/
-STL_FullRamTestStartup PROC
-            EXPORT STL_FullRamTestStartup
-
-            MOVS  R4, #0x0               ; STL_OK:Test success status by default
-
-            LDR   R2, =data0x00000000    ; Prepares background pattern
-            LDR   R2, [R2]
-            LDR   R3, =data0xFFFFFFFF    ; Prepares inverted background pattern
-            LDR   R3, [R3]
-
-            ; *** Step 1 ***
-            ; Write background pattern with addresses increasing
-            MOVS  R5, R0
-_step1_loop
-            CMP   R5, R1
-            BHI   _step_2
-            STR   R2, [R5, #+0]
-            ADDS  R5, R5, #+4
-            B     _step1_loop
-
-            ; *** Step 2 ***
-            ; Verify background and write inverted background with addresses increasing
-_step_2
-            MOVS  R5, R0
-_step_2_loop
-            CMP   R5, R1
-            BHI   _step_3
-            LDR   R6, [R5, #+0]
-            CMP   R6, R2
-            BNE   _full_ram1_test_fail
-            STR   R3, [R5, #+0]
-            LDR   R6, [R5, #+4]
-            CMP   R6, R2
-            BNE   _full_ram1_test_fail
-            STR   R3, [R5, #+4]
-
-            LDR   R6, [R5, #+8]
-            CMP   R6, R2
-            BNE   _full_ram1_test_fail
-            STR   R3, [R5, #+8]
-            LDR   R6, [R5, #+12]
-            CMP   R6, R2
-            BNE   _full_ram1_test_fail
-            STR   R3, [R5, #+12]
-
-            ADDS  R5, R5, #+16
-            B     _step_2_loop
-
-            ; *** Step 3 ***
-            ; Verify inverted background and write background with addresses increasing
-_step_3
-            MOVS  R5, R0
-_step_3_loop
-            CMP   R5, R1
-            BHI   _step_4
-            LDR   R6, [R5, #+0]
-            CMP   R6, R3
-            BNE   _full_ram1_test_fail
-            STR   R2, [R5, #+0]
-            LDR   R6, [R5, #+4]
-            CMP   R6, R3
-            BNE   _full_ram1_test_fail
-            STR   R2, [R5, #+4]
-
-            LDR   R6, [R5, #+8]
-            CMP   R6, R3
-            BNE   _full_ram1_test_fail
-            STR   R2, [R5, #+8]
-            LDR   R6, [R5, #+12]
-            CMP   R6, R3
-            BNE   _full_ram1_test_fail
-            STR   R2, [R5, #+12]
-
-            ADDS  R5, R5, #+16
-            B     _step_3_loop
-
-            ; *** Step 4 ***
-            ; Verify background and write inverted background with addresses decreasing
-_step_4
-            MOVS  R5, R1
-            SUBS  R5, R5, #+15
-_step_4_loop
-            CMP   R5, R0
-            BLO   _step_5
-
-            LDR   R6, [R5, #+12]
-            CMP   R6, R2
-            BNE   _full_ram1_test_fail
-            STR   R3, [R5, #+12]
-            LDR   R6, [R5, #+8]
-            CMP   R6, R2
-            BNE   _full_ram1_test_fail
-            STR   R3, [R5, #+8]
-
-            LDR   R6, [R5, #+4]
-            CMP   R6, R2
-            BNE   _full_ram1_test_fail
-            STR   R3, [R5, #+4]
-            LDR   R6, [R5, #+0]
-            CMP   R6, R2
-            BNE   _full_ram1_test_fail
-            STR   R3, [R5, #+0]
-
-            SUBS  R5, R5, #+16
-            B     _step_4_loop
-
-            ; *** Step 5 ***
-            ; Verify inverted background and write background with addresses decreasing
-_step_5
-            MOVS  R5, R1
-            SUBS  R5, R5, #+15
-_step_5_loop
-            CMP   R5, R0
-            BLO   _step_6
-
-            LDR   R6, [R5, #+12]
-            CMP   R6, R3
-            BNE   _full_ram1_test_fail
-            STR   R2, [R5, #+12]
-            LDR   R6, [R5, #+8]
-            CMP   R6, R3
-            BNE   _full_ram1_test_fail
-            STR   R2, [R5, #+8]
-
-            LDR   R6, [R5, #+4]
-            CMP   R6, R3
-            BNE   _full_ram1_test_fail
-            STR   R2, [R5, #+4]
-            LDR   R6, [R5, #+0]
-            CMP   R6, R3
-            BNE   _full_ram1_test_fail
-            STR   R2, [R5, #+0]
-            SUBS  R5, R5, #+16
-            B     _step_5_loop
-
-            ; *** Step 6 ***
-            ; Verify background with addresses increasing
-_step_6
-            MOVS  R5, R0
-_step_6_loop
-            CMP   R5, R1
-            BHI   _full_ram1_test_pass
-            LDR   R6, [R5, #+0]
-            CMP   R6, R2
-            BNE   _full_ram1_test_fail
-            ADDS  R5, R5, #+4
-            B     _step_6_loop
-
-_full_ram1_test_fail
-            MOVS  R4, #1       ; STL_ERR
-
-_full_ram1_test_pass
-            MOVS  R0, R4
-            BX    LR          ; return to the caller
-
-            ENDP
-
-            ALIGN
-
-            END

bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/MDK/stl_test_pc.s

@@ -1,147 +0,0 @@
-;/*****************************************************************************
-; * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
-; *
-; * This software component is licensed by XHSC under BSD 3-Clause license
-; * (the "License"); You may not use this file except in compliance with the
-; * License. You may obtain a copy of the License at:
-; *                    opensource.org/licenses/BSD-3-Clause
-; *
-; */
-;/****************************************************************************/
-;/*  Test for MDK                                                            */
-;/*  Date             Author          Notes                                  */
-;/*  2022-03-31       CDT             First version                          */
-;/*  2023-05-31       CDT             Typo: subrouitne -> subroutine         */
-;/****************************************************************************/
-
-    THUMB
-    REQUIRE8
-    PRESERVE8
-
-    AREA |.text|, CODE, READONLY, ALIGN=2
-
-;*******************************************************************************
-; Function Name  : STL_PcTest
-; Description    : Test PC
-; Input          : None.
-; Output         : Perform routine when detect failure at set of self test cases
-; Return         : STL_OK (=0):test pass; STL_ERR (=1):test fail;
-; WARNING        : all registers destroyed when exiting this function (including
-;                  preserved registers R4 to R11) and excluding stack point R13)
-;*******************************************************************************/
-
-STL_PcTest PROC
-            EXPORT STL_PcTest
-
-            PUSH {R4-R7}            ; Save registers
-            MOVS R0, #0
-            MOVS R1, #0             ; clr R0,R1
-            MOV  R3, LR
-
-_subroutine_1
-            LDR R0, =_return_pc_test_addr_1
-            BL  _return_pc_test_addr_1
-            CMP R0, R1              ; verify return address?
-            BEQ _subroutine_2
-            B _pc_test_fail
-
-_subroutine_2
-            LDR R0, =_return_pc_test_addr_2
-            BL  _return_pc_test_addr_2
-            CMP R0, R1              ; verify return address?
-            BEQ _subroutine_3
-            B _pc_test_fail
-
-_subroutine_3
-            LDR R0, =_return_pc_test_addr_3
-            BL  _return_pc_test_addr_3
-            CMP R0, R1              ; verify return address?
-            BEQ _subroutine_4
-            B _pc_test_fail
-
-_subroutine_4
-            LDR R0, =_return_pc_test_addr_4
-            BL  _return_pc_test_addr_4
-            CMP R0, R1              ; verify return address?
-            BEQ _subroutine_5
-            B _pc_test_fail
-
-_subroutine_5
-            LDR R0, =_return_pc_test_addr_5
-            BL  _return_pc_test_addr_5
-            CMP R0, R1              ; verify return address?
-            BEQ _subroutine_6
-            B _pc_test_fail
-
-_subroutine_6
-            LDR R0, =_return_pc_test_addr_6
-            BL  _return_pc_test_addr_6
-            CMP R0, R1              ; verify return address?
-            BEQ _subroutine_7
-            B _pc_test_fail
-
-_subroutine_7
-            LDR R0, =_return_pc_test_addr_7
-            BL  _return_pc_test_addr_7
-            CMP R0, R1              ; verify return address?
-            BEQ _subroutine_8
-            B _pc_test_fail
-
-_subroutine_8
-            LDR R0, =_return_pc_test_addr_8
-            BL  _return_pc_test_addr_8
-            CMP R0, R1              ; verify return address?
-            BEQ _pc_test_pass
-            B _pc_test_fail
-
-_pc_test_fail
-            ; when test fail, R0 will hold value 1
-            MOVS R0, #0x1           ; STL_ERR
-            B _pc_test_exit
-
-_pc_test_pass
-            ; when test pass, R0 will hold value 0
-            MOVS R0, #0x0           ; STL_OK
-            B _pc_test_exit
-
-_pc_test_exit
-            POP {R4-R7}             ; Restore registers
-            BX R3                   ; return
-
-_return_pc_test_addr_1
-            LDR R1, =_return_pc_test_addr_1     ; store subroutine address in R1
-            BX LR
-
-_return_pc_test_addr_2
-            LDR R1, =_return_pc_test_addr_2     ; store subroutine address in R1
-            BX LR
-
-_return_pc_test_addr_3
-            LDR R1, =_return_pc_test_addr_3     ; store subroutine address in R1
-            BX LR
-
-_return_pc_test_addr_4
-            LDR R1, =_return_pc_test_addr_4     ; store subroutine address in R1
-            BX LR
-
-_return_pc_test_addr_5
-            LDR R1, =_return_pc_test_addr_5     ; store subroutine address in R1
-            BX LR
-
-_return_pc_test_addr_6
-            LDR R1, =_return_pc_test_addr_6     ; store subroutine address in R1
-            BX LR
-
-_return_pc_test_addr_7
-            LDR R1, =_return_pc_test_addr_7     ; store subroutine address in R1
-            BX LR
-
-_return_pc_test_addr_8
-            LDR R1, =_return_pc_test_addr_8     ; store subroutine address in R1
-            BX LR
-
-            ENDP
-
-            ALIGN
-
-            END

bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/stl_sw_crc32.c

@@ -1,154 +0,0 @@
-/**
- *******************************************************************************
- * @file  stl_sw_crc32.c
- * @brief This file provides firmware functions to manage the software CRC32.
- @verbatim
-   Change Logs:
-   Date             Author          Notes
-   2022-03-31       CDT             First version
-   2022-06-30       CDT             Fix warning: MISRAC2012-Rule-18.4
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- *                    opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "stl_sw_crc32.h"
-
-/**
- * @addtogroup STL_IEC60730
- * @{
- */
-
-/**
- * @defgroup STL_IEC60730_CRC32 STL IEC60730 CRC32
- * @brief IEC60730 software CRC32
- * @{
- */
-
-/*******************************************************************************
- * Local type definitions ('typedef')
- ******************************************************************************/
-
-/*******************************************************************************
- * Local pre-processor symbols/macros ('#define')
- ******************************************************************************/
-
-/*******************************************************************************
- * Global variable definitions (declared in header file with 'extern')
- ******************************************************************************/
-
-/*******************************************************************************
- * Local function prototypes ('static')
- ******************************************************************************/
-
-/*******************************************************************************
- * Local variable definitions ('static')
- ******************************************************************************/
-
-/**
- * @defgroup STL_IEC60730_CRC32_Local_Variables STL IEC60730 CRC32 Local Variables
- * @{
- */
-static const uint32_t m_au32Crc32Table[256] = {
-    0x00000000, 0x77073096, 0xEE0E612C, 0x990951BA, 0x076DC419, 0x706AF48F,
-    0xE963A535, 0x9E6495A3, 0x0EDB8832, 0x79DCB8A4, 0xE0D5E91E, 0x97D2D988,
-    0x09B64C2B, 0x7EB17CBD, 0xE7B82D07, 0x90BF1D91, 0x1DB71064, 0x6AB020F2,
-    0xF3B97148, 0x84BE41DE, 0x1ADAD47D, 0x6DDDE4EB, 0xF4D4B551, 0x83D385C7,
-    0x136C9856, 0x646BA8C0, 0xFD62F97A, 0x8A65C9EC, 0x14015C4F, 0x63066CD9,
-    0xFA0F3D63, 0x8D080DF5, 0x3B6E20C8, 0x4C69105E, 0xD56041E4, 0xA2677172,
-    0x3C03E4D1, 0x4B04D447, 0xD20D85FD, 0xA50AB56B, 0x35B5A8FA, 0x42B2986C,
-    0xDBBBC9D6, 0xACBCF940, 0x32D86CE3, 0x45DF5C75, 0xDCD60DCF, 0xABD13D59,
-    0x26D930AC, 0x51DE003A, 0xC8D75180, 0xBFD06116, 0x21B4F4B5, 0x56B3C423,
-    0xCFBA9599, 0xB8BDA50F, 0x2802B89E, 0x5F058808, 0xC60CD9B2, 0xB10BE924,
-    0x2F6F7C87, 0x58684C11, 0xC1611DAB, 0xB6662D3D, 0x76DC4190, 0x01DB7106,
-    0x98D220BC, 0xEFD5102A, 0x71B18589, 0x06B6B51F, 0x9FBFE4A5, 0xE8B8D433,
-    0x7807C9A2, 0x0F00F934, 0x9609A88E, 0xE10E9818, 0x7F6A0DBB, 0x086D3D2D,
-    0x91646C97, 0xE6635C01, 0x6B6B51F4, 0x1C6C6162, 0x856530D8, 0xF262004E,
-    0x6C0695ED, 0x1B01A57B, 0x8208F4C1, 0xF50FC457, 0x65B0D9C6, 0x12B7E950,
-    0x8BBEB8EA, 0xFCB9887C, 0x62DD1DDF, 0x15DA2D49, 0x8CD37CF3, 0xFBD44C65,
-    0x4DB26158, 0x3AB551CE, 0xA3BC0074, 0xD4BB30E2, 0x4ADFA541, 0x3DD895D7,
-    0xA4D1C46D, 0xD3D6F4FB, 0x4369E96A, 0x346ED9FC, 0xAD678846, 0xDA60B8D0,
-    0x44042D73, 0x33031DE5, 0xAA0A4C5F, 0xDD0D7CC9, 0x5005713C, 0x270241AA,
-    0xBE0B1010, 0xC90C2086, 0x5768B525, 0x206F85B3, 0xB966D409, 0xCE61E49F,
-    0x5EDEF90E, 0x29D9C998, 0xB0D09822, 0xC7D7A8B4, 0x59B33D17, 0x2EB40D81,
-    0xB7BD5C3B, 0xC0BA6CAD, 0xEDB88320, 0x9ABFB3B6, 0x03B6E20C, 0x74B1D29A,
-    0xEAD54739, 0x9DD277AF, 0x04DB2615, 0x73DC1683, 0xE3630B12, 0x94643B84,
-    0x0D6D6A3E, 0x7A6A5AA8, 0xE40ECF0B, 0x9309FF9D, 0x0A00AE27, 0x7D079EB1,
-    0xF00F9344, 0x8708A3D2, 0x1E01F268, 0x6906C2FE, 0xF762575D, 0x806567CB,
-    0x196C3671, 0x6E6B06E7, 0xFED41B76, 0x89D32BE0, 0x10DA7A5A, 0x67DD4ACC,
-    0xF9B9DF6F, 0x8EBEEFF9, 0x17B7BE43, 0x60B08ED5, 0xD6D6A3E8, 0xA1D1937E,
-    0x38D8C2C4, 0x4FDFF252, 0xD1BB67F1, 0xA6BC5767, 0x3FB506DD, 0x48B2364B,
-    0xD80D2BDA, 0xAF0A1B4C, 0x36034AF6, 0x41047A60, 0xDF60EFC3, 0xA867DF55,
-    0x316E8EEF, 0x4669BE79, 0xCB61B38C, 0xBC66831A, 0x256FD2A0, 0x5268E236,
-    0xCC0C7795, 0xBB0B4703, 0x220216B9, 0x5505262F, 0xC5BA3BBE, 0xB2BD0B28,
-    0x2BB45A92, 0x5CB36A04, 0xC2D7FFA7, 0xB5D0CF31, 0x2CD99E8B, 0x5BDEAE1D,
-    0x9B64C2B0, 0xEC63F226, 0x756AA39C, 0x026D930A, 0x9C0906A9, 0xEB0E363F,
-    0x72076785, 0x05005713, 0x95BF4A82, 0xE2B87A14, 0x7BB12BAE, 0x0CB61B38,
-    0x92D28E9B, 0xE5D5BE0D, 0x7CDCEFB7, 0x0BDBDF21, 0x86D3D2D4, 0xF1D4E242,
-    0x68DDB3F8, 0x1FDA836E, 0x81BE16CD, 0xF6B9265B, 0x6FB077E1, 0x18B74777,
-    0x88085AE6, 0xFF0F6A70, 0x66063BCA, 0x11010B5C, 0x8F659EFF, 0xF862AE69,
-    0x616BFFD3, 0x166CCF45, 0xA00AE278, 0xD70DD2EE, 0x4E048354, 0x3903B3C2,
-    0xA7672661, 0xD06016F7, 0x4969474D, 0x3E6E77DB, 0xAED16A4A, 0xD9D65ADC,
-    0x40DF0B66, 0x37D83BF0, 0xA9BCAE53, 0xDEBB9EC5, 0x47B2CF7F, 0x30B5FFE9,
-    0xBDBDF21C, 0xCABAC28A, 0x53B39330, 0x24B4A3A6, 0xBAD03605, 0xCDD70693,
-    0x54DE5729, 0x23D967BF, 0xB3667A2E, 0xC4614AB8, 0x5D681B02, 0x2A6F2B94,
-    0xB40BBE37, 0xC30C8EA1, 0x5A05DF1B, 0x2D02EF8D
-};
-/**
- * @}
- */
-
-/*******************************************************************************
- * Function implementation - global ('extern') and local ('static')
- ******************************************************************************/
-
-/**
- * @defgroup STL_IEC60730_CRC32_Global_Functions STL IEC60730 CRC32 Global Functions
- * @{
- */
-
-/**
- * @brief  Calculate CRC32 value.
- * @param  [in] u32Crc32Value       CRC32 value
- * @param  [in] pu8Data             Pointer to data buffer
- * @param  [in] u32Len              Data length
- * @retval CRC32 value
- * @note Poly=0x04C11DB7, Init=0xFFFFFFFF, RefIn=true, RefOut=true, XorOut=0x00000000
- */
-uint32_t STL_CalculateCRC32Value(uint32_t u32Crc32Value, uint8_t *pu8Data, uint32_t u32Len)
-{
-    uint32_t i;
-    uint32_t u32CurrCrc32Value = u32Crc32Value;
-
-    for (i = 0UL; i < u32Len; i++) {
-        u32CurrCrc32Value = (u32CurrCrc32Value >> 8) ^ m_au32Crc32Table[(u32CurrCrc32Value & 0xFFUL) ^ pu8Data[i]];
-    }
-
-    return u32CurrCrc32Value;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/*******************************************************************************
- * EOF (not truncated)
- *****************************************************************************/

bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/stl_test_flash.c

@@ -1,179 +0,0 @@
-/**
- *******************************************************************************
- * @file  stl_test_flash.c
- * @brief This file provides firmware functions to manage the flash test.
- @verbatim
-   Change Logs:
-   Date             Author          Notes
-   2022-03-31       CDT             First version
-   2022-06-30       CDT             Fix warning: MISRAC2012-Rule-18.4
-   2023-01-15       CDT             Fix bug: Reading CC Build CRC32 value is error in release project
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- *                    opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "stl_conf.h"
-#include "stl_utility.h"
-#include "stl_sw_crc32.h"
-#include "stl_test_flash.h"
-
-/**
- * @addtogroup STL_IEC60730
- * @{
- */
-
-/**
- * @defgroup STL_IEC60730_Flash STL IEC60730 Flash
- * @brief IEC60730 flash test
- * @{
- */
-
-/*******************************************************************************
- * Local type definitions ('typedef')
- ******************************************************************************/
-
-/*******************************************************************************
- * Local pre-processor symbols/macros ('#define')
- ******************************************************************************/
-#if defined (__CC_ARM)                  /* keil Compiler */
-#define STL_CRC32_XOR_VALUE     (0xFFFFFFFFUL)
-#elif defined (__IAR_SYSTEMS_ICC__)     /* IAR Compiler */
-#define STL_CRC32_XOR_VALUE     (0x00000000UL)
-#endif
-
-#define SW_CRC32_VALUE_XOR(x)   ((x) ^ STL_CRC32_XOR_VALUE)
-
-/*******************************************************************************
- * Global variable definitions (declared in header file with 'extern')
- ******************************************************************************/
-/**
- * @defgroup STL_IEC60730_Flash_Local_Variables STL IEC60730 Flash Local Variables
- * @{
- */
-STL_USED const uint32_t __checksum STL_SECTION(".checksum") = 0UL;
-/**
- * @}
- */
-
-/*******************************************************************************
- * Local function prototypes ('static')
- ******************************************************************************/
-
-/*******************************************************************************
- * Local variable definitions ('static')
- ******************************************************************************/
-
-/*******************************************************************************
- * Function implementation - global ('extern') and local ('static')
- ******************************************************************************/
-
-/**
- * @defgroup STL_IEC60730_Flash_Global_Functions STL IEC60730 Flash Global Functions
- * @{
- */
-
-/**
- * @brief  Flash test in startup.
- * @param  None
- * @retval uint32_t:
- *           - STL_OK:          Test pass.
- *           - STL_ERR:         Flash CRC value error.
- */
-uint32_t STL_FlashStartupTest(void)
-{
-    uint32_t u32RomStart = STL_ROM_CRC32_START;
-    uint32_t u32RomEnd = STL_ROM_CRC32_END;
-    uint32_t u32RomSize = (u32RomEnd - u32RomStart);
-    uint8_t *pu8CrcData = (uint8_t *)u32RomStart;
-    uint32_t u32CalcCrc32Value;
-    volatile uint32_t u32CcBulidCrc32Addr;
-    volatile uint32_t u32CcBulidCrc32Value;
-    uint32_t u32Ret = STL_ERR;
-
-    u32CcBulidCrc32Addr = (uint32_t)(&STL_ROM_CRC32_CC_CHECKSUM);
-    u32CcBulidCrc32Value =  *(uint32_t *)(u32CcBulidCrc32Addr);
-    u32CalcCrc32Value = STL_CalculateCRC32Value(STL_CRC32_INIT_VALUE, pu8CrcData, u32RomSize);
-    u32CalcCrc32Value = SW_CRC32_VALUE_XOR(u32CalcCrc32Value);
-    if (u32CcBulidCrc32Value == u32CalcCrc32Value) {
-        u32Ret = STL_OK;
-    }
-
-    return u32Ret;
-}
-
-/**
- * @brief  Flash test in runtime.
- * @param  None
- * @retval uint32_t:
- *           - STL_OK:          Test pass.
- *           - STL_ERR:         Flash CRC value error.
- */
-uint32_t STL_FlashRuntimeTest(void)
-{
-    uint32_t u32Ret = STL_OK;
-    uint32_t u32RomStart = STL_ROM_CRC32_START;
-    uint32_t u32RomEnd = STL_ROM_CRC32_END;
-    uint32_t u32RomSize = (u32RomEnd - u32RomStart);
-    volatile uint32_t u32CcBulidCrc32Addr;
-    volatile uint32_t u32CcBulidCrc32Value;
-    const uint32_t u32CheckEndAddr = u32RomSize + 3UL - STL_ROM_CRC32_BLOCK_SIZE;
-    static uint32_t u32CalcLen;
-    static uint32_t u32CheckAddr = STL_ROM_CRC32_START;
-    static uint32_t u32CalcCrc32Value = STL_CRC32_INIT_VALUE;
-
-    if (u32CheckAddr < STL_ROM_CRC32_END) {
-        if (u32CheckAddr == STL_ROM_CRC32_START) {
-            u32CalcCrc32Value = STL_CRC32_INIT_VALUE;   /* Update CRC32 init value */
-        }
-
-        if (u32CheckAddr < u32CheckEndAddr) {
-            u32CalcLen = STL_ROM_CRC32_BLOCK_SIZE;
-        } else {
-            u32CalcLen = u32RomEnd - u32CheckAddr;
-        }
-        u32CalcCrc32Value = STL_CalculateCRC32Value(u32CalcCrc32Value, (uint8_t *)u32CheckAddr, u32CalcLen);
-
-        u32CheckAddr += u32CalcLen;       /* Update address */
-    } else {
-        u32CcBulidCrc32Addr = (uint32_t)(&STL_ROM_CRC32_CC_CHECKSUM);
-        u32CcBulidCrc32Value =  *(uint32_t *)(u32CcBulidCrc32Addr);
-        u32CheckAddr = STL_ROM_CRC32_START;             /* Update address */
-        u32CalcCrc32Value = SW_CRC32_VALUE_XOR(u32CalcCrc32Value);
-        if (u32CcBulidCrc32Value == u32CalcCrc32Value) {
-            STL_Printf("********   CRC32 verify ok in runtime                   ********\r\n");
-        } else {
-            STL_Printf("********   CRC32 verify error in runtime                ********\r\n");
-            STL_Printf("* Calc_CRC32= 0x%x:CC Build_CRC32= 0x%x *\r\n", u32CalcCrc32Value, u32CcBulidCrc32Value);
-            u32Ret = STL_ERR;
-        }
-    }
-
-    return u32Ret;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/*******************************************************************************
- * EOF (not truncated)
- *****************************************************************************/

bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/stl_test_interrupt.c

@@ -1,165 +0,0 @@
-/**
- *******************************************************************************
- * @file  stl_test_interrupt.c
- * @brief This file provides firmware functions to manage the interrupt test.
- @verbatim
-   Change Logs:
-   Date             Author          Notes
-   2022-03-31       CDT             First version
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- *                    opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "stl_conf.h"
-#include "stl_test_interrupt.h"
-
-/**
- * @addtogroup STL_IEC60730
- * @{
- */
-
-/**
- * @defgroup STL_IEC60730_Interrupt_Runtime STL IEC60730 Interrupt Runtime
- * @brief IEC60730 interrupt runtime test
- * @{
- */
-
-/*******************************************************************************
- * Local pre-processor symbols/macros ('#define')
- ******************************************************************************/
-
-/*******************************************************************************
- * Global variable definitions (declared in header file with 'extern')
- ******************************************************************************/
-
-/*******************************************************************************
- * Local type definitions ('typedef')
- ******************************************************************************/
-
-/*******************************************************************************
- * Local function prototypes ('static')
- ******************************************************************************/
-
-/*******************************************************************************
- * Local variable definitions ('static')
- ******************************************************************************/
-/**
- * @defgroup STL_IEC60730_RAM_Local_Variables STL IEC60730 RAM Local Variables
- * @{
- */
-static uint32_t m_u32TestParamTableSize;
-static stc_stl_int_params_t *m_pstcTestParamTable;
-/**
- * @}
- */
-
-/*******************************************************************************
- * Local pre-processor symbols/macros ('#define')
- ******************************************************************************/
-
-/*******************************************************************************
- * Function implementation - global ('extern') and local ('static')
- ******************************************************************************/
-
-/**
- * @defgroup STL_IEC60730_Interrupt_Global_Functions STL IEC60730 Interrupt Global Functions
- * @{
- */
-
-/**
- * @brief  Interrupt test table initialize in runtime.
- * @param  [in] pstcParamsTable     Test case table
- * @param  [in] u32TableSize        Test case size
- * @retval uint32_t:
- *           - STL_OK:              Initialize successfully.
- *           - STL_ERR:             Initialize unsuccessfully.
- */
-uint32_t STL_IntRuntimeTableInit(stc_stl_int_params_t *pstcParamsTable, uint32_t u32TableSize)
-{
-    uint32_t i;
-    uint32_t u32Ret = STL_ERR;
-
-    if ((pstcParamsTable != NULL) && (u32TableSize != 0UL)) {
-        for (i = 0UL; i < u32TableSize; i++) {
-            pstcParamsTable[i].u32PrivateParam = 0UL;
-        }
-
-        m_pstcTestParamTable = pstcParamsTable;
-        m_u32TestParamTableSize = u32TableSize;
-        u32Ret = STL_OK;
-    }
-
-    return u32Ret;
-}
-
-/**
- * @brief  Interrupt test in runtime.
- * @param  None
- * @retval uint32_t:
- *           - STL_OK:              Test pass.
- *           - STL_ERR:             Test error.
- */
-uint32_t STL_IntRuntimeTest(void)
-{
-    uint32_t i;
-    uint32_t u32Ret = STL_OK;
-    stc_stl_int_params_t *pstcTestParam;
-    static uint32_t u32SystickCount;
-
-    if (++u32SystickCount == STL_SYSTICK_TICK_FREQ) {
-        for (i = 0UL; i < m_u32TestParamTableSize; i++) {
-            pstcTestParam = &m_pstcTestParamTable[i];
-
-            if ((pstcTestParam->u32PrivateParam < pstcTestParam->u32FreqLowerVal) || \
-                (pstcTestParam->u32PrivateParam > pstcTestParam->u32FreqUpperVal)) {
-                u32Ret = STL_ERR;
-            }
-            pstcTestParam->u32PrivateParam = 0UL;
-        }
-        u32SystickCount = 0UL;
-    }
-
-    return u32Ret;
-}
-
-/**
- * @brief  Update interrupt count in runtime.
- * @param  [in] u8ParamIndex        Params index
- * @retval None
- */
-void STL_IntUpdateCount(uint8_t u8ParamIndex)
-{
-    stc_stl_int_params_t *pstcTestParam;
-
-    if (u8ParamIndex < m_u32TestParamTableSize) {
-        pstcTestParam = &m_pstcTestParamTable[u8ParamIndex];
-        pstcTestParam->u32PrivateParam++;
-    }
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/*******************************************************************************
- * EOF (not truncated)
- ******************************************************************************/

bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/stl_test_ram_runtime.c

@@ -1,269 +0,0 @@
-/**
- *******************************************************************************
- * @file  stl_test_ram_runtime.c
- * @brief This file provides firmware functions to manage the RAM test.
- @verbatim
-   Change Logs:
-   Date             Author          Notes
-   2022-03-31       CDT             First version
-   2022-06-30       CDT             Fix warning: MISRAC2012-Rule-18.4
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- *                    opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "stl_conf.h"
-#include "stl_test_ram.h"
-
-/**
- * @addtogroup STL_IEC60730
- * @{
- */
-
-/**
- * @defgroup STL_IEC60730_RAM_Runtime STL IEC60730 RAM Runtime
- * @brief IEC60730 RAM runtime test
- * @{
- */
-
-/*******************************************************************************
- * Local type definitions ('typedef')
- ******************************************************************************/
-
-/*******************************************************************************
- * Local pre-processor symbols/macros ('#define')
- ******************************************************************************/
-
-/*******************************************************************************
- * Global variable definitions (declared in header file with 'extern')
- ******************************************************************************/
-
-/*******************************************************************************
- * Local function prototypes ('static')
- ******************************************************************************/
-
-/*******************************************************************************
- * Local variable definitions ('static')
- ******************************************************************************/
-/**
- * @defgroup STL_IEC60730_RAM_Local_Variables STL IEC60730 RAM Local Variables
- * @{
- */
-STL_USED uint32_t  m_au32MarchRAM[STL_MARCH_RAM_WORDS] STL_SECTION(".march_ram");
-STL_USED uint32_t  m_au32MarchRAMBuf[STL_MARCH_RAM_BUF_WORDS] STL_SECTION(".march_ram_buf");
-STL_USED uint32_t *m_pu32MarchRAM STL_SECTION(".march_ram_pointer");
-STL_USED uint32_t  m_au32StackBoundary[STL_STACK_BOUNDARY_WORDS] STL_SECTION(".stack_boundary");
-/**
- * @}
- */
-
-/*******************************************************************************
- * Function implementation - global ('extern') and local ('static')
- ******************************************************************************/
-
-/**
- * @defgroup STL_IEC60730_RAM_Global_Functions STL IEC60730 RAM Global Functions
- * @{
- */
-
-/**
- * @brief  Stack test initialize in runtime.
- * @param  None
- * @retval uint32_t:
- *           - STL_OK:          Initialization pass.
- */
-uint32_t STL_StackRuntimeInit(void)
-{
-    m_au32StackBoundary[0] = 0x5A5A5A5AUL;
-    m_au32StackBoundary[1] = 0xA5A5A5A5UL;
-    m_au32StackBoundary[2] = 0xAAAAAAAAUL;
-    m_au32StackBoundary[3] = 0x55555555UL;
-    return STL_OK;
-}
-
-/**
- * @brief  Stack test in runtime.
- * @param  None
- * @retval uint32_t:
- *           - STL_OK:          Test pass.
- *           - STL_ERR:         Stack boundary value error.
- */
-uint32_t STL_StackRuntimeTest(void)
-{
-    if ((m_au32StackBoundary[0] != 0x5A5A5A5AUL) || \
-        (m_au32StackBoundary[1] != 0xA5A5A5A5UL) || \
-        (m_au32StackBoundary[2] != 0xAAAAAAAAUL) || \
-        (m_au32StackBoundary[3] != 0x55555555UL)) {
-        return STL_ERR;
-    }
-
-    return STL_OK;
-}
-
-/**
- * @brief  RAM test initialize in runtime.
- * @param  None
- * @retval uint32_t:
- *           - STL_OK:          Initialization pass.
- */
-uint32_t STL_RamRuntimeInit(void)
-{
-    m_pu32MarchRAM = (uint32_t *)STL_MARCH_RAM_START;
-    return STL_OK;
-}
-
-/**
- * @brief  RAM test in runtime.
- * @param  None
- * @retval uint32_t:
- *           - STL_OK:          Test pass.
- *           - STL_ERR:         Test fail.
- */
-uint32_t STL_RamRuntimeTest(void)
-{
-    uint32_t i;        /* Index for RAM physical addressing */
-    uint32_t u32Ret = STL_OK;
-
-    if (m_pu32MarchRAM >= (uint32_t *)STL_MARCH_RAM_END) {
-        /*------------- March C- to the RAM Buffer itself --------------- */
-        m_pu32MarchRAM = &m_au32MarchRAMBuf[0];
-
-        /*---------------------------- STEP 1 --------------------------------- */
-        /* Write background with addresses increasing */
-        for (i = 0UL; i < STL_MARCH_RAM_BUF_WORDS; ++i) {
-            m_pu32MarchRAM[i] = STL_MARCH_RAM_BCKGRND;
-        }
-
-        /*---------------------------- STEP 2 --------------------------------- */
-        /* Verify background and write inverted background addresses increasing */
-        for (i = 0UL; i < STL_MARCH_RAM_BUF_WORDS; ++i) {
-            if (m_pu32MarchRAM[i] != STL_MARCH_RAM_BCKGRND) {
-                u32Ret = STL_ERR;
-            }
-            m_pu32MarchRAM[i] = STL_MARCH_RAM_INVBCKGRND;
-        }
-
-        /*---------------------------- STEP 3 --------------------------------- */
-        /* Verify inverted background and write background addresses increasing */
-        for (i = 0UL; i < STL_MARCH_RAM_BUF_WORDS; ++i) {
-            if (m_pu32MarchRAM[i] != STL_MARCH_RAM_INVBCKGRND) {
-                u32Ret = STL_ERR;
-            }
-            m_pu32MarchRAM[i] = STL_MARCH_RAM_BCKGRND;
-        }
-
-        /*---------------------------- STEP 4 --------------------------------- */
-        /* Verify background and write inverted background addresses decreasing */
-        for (i = STL_MARCH_RAM_BUF_WORDS; i > 0UL ; --i) {
-            if (m_pu32MarchRAM[i - 1UL] != STL_MARCH_RAM_BCKGRND) {
-                u32Ret = STL_ERR;
-            }
-            m_pu32MarchRAM[i - 1UL] = STL_MARCH_RAM_INVBCKGRND;
-        }
-
-        /*---------------------------- STEP 5 --------------------------------- */
-        /* Verify inverted background and write background addresses decreasing */
-        for (i = STL_MARCH_RAM_BUF_WORDS; i > 0UL ; --i) {
-            if (m_pu32MarchRAM[i - 1UL] != STL_MARCH_RAM_INVBCKGRND) {
-                u32Ret = STL_ERR;
-            }
-            m_pu32MarchRAM[i - 1UL] = STL_MARCH_RAM_BCKGRND;
-        }
-
-        /*---------------------------- STEP 6 --------------------------------- */
-        /* Verify background with addresses increasing */
-        for (i = 0UL; i < STL_MARCH_RAM_BUF_WORDS; ++i) {
-            if (m_pu32MarchRAM[i] != STL_MARCH_RAM_BCKGRND) {
-                u32Ret = STL_ERR;
-            }
-        }
-
-        /* Prepare next Tranparent RAM test from the beginning of Class A area */
-        m_pu32MarchRAM = (uint32_t *)STL_MARCH_RAM_START;
-    } else {
-        /*---------------------------- STEP 1 --------------------------------- */
-        /* Save the content of the 6 words to be tested and start MarchC -
-           Write background with addresses increasing */
-        for (i = 0UL; i < STL_MARCH_RAM_BUF_WORDS; ++i) {
-            m_au32MarchRAMBuf[i] = m_pu32MarchRAM[i];
-            m_pu32MarchRAM[i] = STL_MARCH_RAM_BCKGRND;
-        }
-
-        /*---------------------------- STEP 2 --------------------------------- */
-        /* Verify background and write inverted background addresses increasing */
-        for (i = 0UL; i < STL_MARCH_RAM_BUF_WORDS; ++i) {
-            if (m_pu32MarchRAM[i] != STL_MARCH_RAM_BCKGRND) {
-                u32Ret = STL_ERR;
-            }
-            m_pu32MarchRAM[i] = STL_MARCH_RAM_INVBCKGRND;
-        }
-
-        /*---------------------------- STEP 3 --------------------------------- */
-        /* Verify inverted background and write background addresses increasing */
-        for (i = 0UL; i < STL_MARCH_RAM_BUF_WORDS; ++i) {
-            if (m_pu32MarchRAM[i] != STL_MARCH_RAM_INVBCKGRND) {
-                u32Ret = STL_ERR;
-            }
-            m_pu32MarchRAM[i] = STL_MARCH_RAM_BCKGRND;
-        }
-
-        /*---------------------------- STEP 4 --------------------------------- */
-        /* Verify background and write inverted background addresses decreasing */
-        for (i = STL_MARCH_RAM_BUF_WORDS; i > 0UL; --i) {
-            if (m_pu32MarchRAM[i - 1UL] != STL_MARCH_RAM_BCKGRND) {
-                u32Ret = STL_ERR;
-            }
-            m_pu32MarchRAM[i - 1UL] = STL_MARCH_RAM_INVBCKGRND;
-        }
-
-        /*---------------------------- STEP 5 --------------------------------- */
-        /* Verify inverted background and write background addresses decreasing */
-        for (i = STL_MARCH_RAM_BUF_WORDS; i > 0UL; --i) {
-            if (m_pu32MarchRAM[i - 1UL] != STL_MARCH_RAM_INVBCKGRND) {
-                u32Ret = STL_ERR;
-            }
-            m_pu32MarchRAM[i - 1UL] = STL_MARCH_RAM_BCKGRND;
-        }
-
-        /*---------------------------- STEP 6 --------------------------------- */
-        /* Verify background with addresses increasing */
-        /* and restore the content of the 6 tested words */
-        for (i = 0UL; i < STL_MARCH_RAM_BUF_WORDS; ++i) {
-            if (m_pu32MarchRAM[i] != STL_MARCH_RAM_BCKGRND) {
-                u32Ret = STL_ERR;
-            }
-            m_pu32MarchRAM[i] = m_au32MarchRAMBuf[i];
-        }
-
-        /* Prepare next Row Tranparent RAM test */
-        m_pu32MarchRAM = &m_pu32MarchRAM[STL_MARCH_RAM_BUF_WORDS];
-    }
-
-    return u32Ret;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/*******************************************************************************
- * EOF (not truncated)
- *****************************************************************************/

bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_runtime.c

@@ -1,145 +0,0 @@
-/**
- *******************************************************************************
- * @file  stl_test_runtime.c
- * @brief This file provides firmware functions to manage the runtime self-test.
- @verbatim
-   Change Logs:
-   Date             Author          Notes
-   2022-03-31       CDT             First version
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- *                    opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "stl_test_runtime.h"
-#include "stl_conf.h"
-#include "stl_utility.h"
-
-/**
- * @addtogroup STL_IEC60730
- * @{
- */
-
-/**
- * @defgroup STL_IEC60730_Runtime STL IEC60730 Runtime
- * @brief IEC60730 runtime test
- * @{
- */
-
-/*******************************************************************************
- * Local type definitions ('typedef')
- ******************************************************************************/
-
-/*******************************************************************************
- * Local pre-processor symbols/macros ('#define')
- ******************************************************************************/
-
-/*******************************************************************************
- * Global variable definitions (declared in header file with 'extern')
- ******************************************************************************/
-
-/*******************************************************************************
- * Local function prototypes ('static')
- ******************************************************************************/
-
-/*******************************************************************************
- * Local variable definitions ('static')
- ******************************************************************************/
-
-/*******************************************************************************
- * Function implementation - global ('extern') and local ('static')
- ******************************************************************************/
-
-/**
- * @defgroup STL_IEC60730_Runtime_Global_Macros STL IEC60730 Runtime Global Macros
- * @{
- */
-
-/**
- * @brief  Self-test initialization in runtime.
- * @param  [in] pstcCaseTable       Test case table
- * @param  [in] u32TableSize        Test case size
- * @retval None
- */
-void STL_RuntimeTestInit(const stc_stl_case_runtime_t *pstcCaseTable, uint32_t u32TableSize)
-{
-    uint32_t i;
-#if (STL_PRINT_ENABLE == STL_ON)
-    static en_flag_status_t enPrintInitActived = RESET;
-#endif
-
-#if (STL_PRINT_ENABLE == STL_ON)
-    /* startup debug print */
-    if (enPrintInitActived == RESET) {
-        (void)STL_PrintfInit();
-        enPrintInitActived = SET;
-    }
-#endif
-
-    STL_Printf("********   Self-test runtime initialize                 ********\r\n");
-
-    if ((pstcCaseTable != NULL) && (u32TableSize != 0UL)) {
-        for (i = 0UL; i < u32TableSize; i++) {
-            if (pstcCaseTable[i].pfnInit != NULL) {
-                if (pstcCaseTable[i].pfnInit() != STL_OK) {
-                    STL_Printf("********   Init fail in runtime: %-20s   ********\r\n", pstcCaseTable[i].pcCaseName);
-                }
-            }
-        }
-    }
-}
-
-/**
- * @brief  Self-test on runtime.
- * @param  [in] pstcCaseTable       Test case table
- * @param  [in] u32TableSize        Test case size
- * @retval None
- */
-void STL_RuntimeTestCase(const stc_stl_case_runtime_t *pstcCaseTable, uint32_t u32TableSize)
-{
-    uint32_t i;
-
-    if ((pstcCaseTable != NULL) && (u32TableSize != 0UL)) {
-        for (i = 0UL; i < u32TableSize; i++) {
-            if (pstcCaseTable[i].pfnTest != NULL) {
-                if (pstcCaseTable[i].pfnTest() != STL_OK) {
-                    STL_Printf("********   Test fail in runtime: %-20s   ********\r\n", pstcCaseTable[i].pcCaseName);
-
-                    if (pstcCaseTable[i].pfnFailHandler != NULL) {
-                        pstcCaseTable[i].pfnFailHandler();
-                    }
-                }
-            }
-
-            if (pstcCaseTable[i].pfnFeedDog != NULL) {
-                pstcCaseTable[i].pfnFeedDog();
-            }
-        }
-    }
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/*******************************************************************************
- * EOF (not truncated)
- *****************************************************************************/

bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_utility.c

@@ -1,236 +0,0 @@
-/**
- *******************************************************************************
- * @file  stl_utility.c
- * @brief This file provides utility functions for STL.
- @verbatim
-   Change Logs:
-   Date             Author          Notes
-   2022-03-31       CDT             First version
-   2023-01-15       CDT             Modify USART_SR_TXE to USART_SR_TC in STL_ConsoleOutputChar()
-   2023-05-31       CDT             Modify register USART DR to USART TDR
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- *                    opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "stl_utility.h"
-#include "hc32_ll_fcg.h"
-#include "hc32_ll_gpio.h"
-#include "hc32_ll_usart.h"
-#include "hc32_ll_utility.h"
-
-/**
- * @addtogroup IEC60730_STL
- * @{
- */
-
-/**
- * @defgroup IEC60730_STL_Utility IEC60730 STL Utility
- * @{
- */
-
-/*******************************************************************************
- * Local type definitions ('typedef')
- ******************************************************************************/
-
-/*******************************************************************************
- * Local pre-processor symbols/macros ('#define')
- ******************************************************************************/
-
-/*******************************************************************************
- * Global variable definitions (declared in header file with 'extern')
- ******************************************************************************/
-
-/*******************************************************************************
- * Local function prototypes ('static')
- ******************************************************************************/
-
-/*******************************************************************************
- * Local variable definitions ('static')
- ******************************************************************************/
-
-/*******************************************************************************
- * Function implementation - global ('extern') and local ('static')
- ******************************************************************************/
-
-/**
- * @defgroup STL_IEC60730_Utility_Global_Functions STL IEC60730 Utility Global Functions
- * @{
- */
-
-/**
- * @brief Delay function, delay us approximately
- * @param [in] u32Count                 us
- * @retval None
- */
-void STL_DelayUS(uint32_t u32Count)
-{
-    DDL_DelayUS(u32Count);
-}
-
-/**
- * @brief Delay function, delay ms approximately
- * @param [in] u32Count                 ms
- * @retval None
- */
-void STL_DelayMS(uint32_t u32Count)
-{
-    DDL_DelayMS(u32Count);
-}
-
-/**
- * @brief STL test safety failure handle
- * @param None
- * @retval None
- */
-void STL_SafetyFailure(void)
-{
-#if (STL_RESET_AT_FAILURE == STL_ON)
-    NVIC_SystemReset(); /* Generate system reset */
-#endif
-}
-
-#if (STL_PRINT_ENABLE == STL_ON)
-
-/**
- * @brief  Transmit character.
- * @param  [in] cData                   The character for transmitting
- * @retval uint32_t:
- *           - STL_OK:                  Transmit successfully.
- *           - STL_ERR:                 Transmit timeout.
- */
-__WEAKDEF uint32_t STL_ConsoleOutputChar(char cData)
-{
-    uint32_t u32Ret = STL_ERR;
-    uint32_t u32TxEmpty = 0UL;
-    __IO uint32_t u32TmpCount = 0UL;
-    uint32_t u32Timeout = 10000UL;
-
-    /* Wait TX data register empty */
-    while ((u32TmpCount <= u32Timeout) && (0UL == u32TxEmpty)) {
-        u32TxEmpty = READ_REG32_BIT(STL_PRINTF_DEVICE->SR, USART_SR_TC);
-        u32TmpCount++;
-    }
-
-    if (0UL != u32TxEmpty) {
-        WRITE_REG16(STL_PRINTF_DEVICE->TDR, (uint16_t)cData);
-        u32Ret = STL_OK;
-    }
-
-    return u32Ret;
-}
-
-#if (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || \
-    (defined (__ICCARM__)) || (defined (__CC_ARM))
-/**
- * @brief  Re-target fputc function.
- * @param  [in] ch
- * @param  [in] f
- * @retval int32_t
- */
-int32_t fputc(int32_t ch, FILE *f)
-{
-    (void)f;  /* Prevent unused argument compilation warning */
-
-    return (STL_OK == STL_ConsoleOutputChar((char)ch)) ? ch : -1;
-}
-
-#elif defined (__GNUC__) && !defined (__CC_ARM)
-/**
- * @brief  Re-target _write function.
- * @param  [in] fd
- * @param  [in] data
- * @param  [in] size
- * @retval int32_t
- */
-int32_t _write(int fd, char data[], int32_t size)
-{
-    int32_t i = -1;
-
-    if (NULL != data) {
-        (void)fd;  /* Prevent unused argument compilation warning */
-
-        for (i = 0; i < size; i++) {
-            if (STL_OK != STL_ConsoleOutputChar(data[i])) {
-                break;
-            }
-        }
-    }
-
-    return i ? i : -1;
-}
-#endif
-
-/**
- * @brief  Initialize printf function
- * @param  None
- * @retval None
- */
-uint32_t STL_PrintfInit(void)
-{
-    uint32_t u32Div;
-    float32_t f32Error;
-    uint32_t u32Ret = STL_ERR;
-    stc_usart_uart_init_t stcUartInit;
-
-    /* Set TX port function */
-    GPIO_SetFunc(STL_PRINTF_PORT, STL_PRINTF_PIN, STL_PRINTF_PORT_FUNC);
-
-    /* Enable clock  */
-    STL_PRINTF_DEVICE_FCG_ENALBE();
-
-    /***************************************************************************
-     * Configure UART
-     ***************************************************************************
-     * Baud rate: STL_PRINTF_BAUDRATE
-     * Bit direction: LSB
-     * Data bits: 8
-     * Stop bits: 1
-     * Parity: None
-     * Sampling bits: 8
-     **************************************************************************/
-    /* Configure UART */
-    (void)USART_UART_StructInit(&stcUartInit);
-    stcUartInit.u32OverSampleBit = USART_OVER_SAMPLE_8BIT;
-    (void)USART_UART_Init(STL_PRINTF_DEVICE, &stcUartInit, NULL);
-
-    for (u32Div = 0UL; u32Div <= USART_CLK_DIV64; u32Div++) {
-        USART_SetClockDiv(STL_PRINTF_DEVICE, u32Div);
-        if ((LL_OK == USART_SetBaudrate(STL_PRINTF_DEVICE, STL_PRINTF_BAUDRATE, &f32Error)) && \
-            ((-STL_PRINTF_BAUDRATE_ERR_MAX <= f32Error) && (f32Error <= STL_PRINTF_BAUDRATE_ERR_MAX))) {
-            USART_FuncCmd(STL_PRINTF_DEVICE, USART_TX, ENABLE);
-            u32Ret = STL_OK;
-            break;
-        }
-    }
-
-    return u32Ret;
-}
-
-#endif /* STL_PRINT_ENABLE */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/*******************************************************************************
- * EOF (not truncated)
- ******************************************************************************/

bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_utility.h

@@ -1,107 +0,0 @@
-/**
- *******************************************************************************
- * @file  stl_utility.h
- * @brief This file contains all the functions prototypes of utility.
- @verbatim
-   Change Logs:
-   Date             Author          Notes
-   2022-03-31       CDT             First version
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- *                    opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-
-#ifndef __STL_UTILITY_H__
-#define __STL_UTILITY_H__
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "stl_common.h"
-#include "stl_conf.h"
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/**
- * @addtogroup IEC60730_STL
- * @{
- */
-
-/**
- * @addtogroup IEC60730_STL_Utility
- * @{
- */
-
-/*******************************************************************************
- * Global type definitions ('typedef')
-*******************************************************************************/
-
-/*******************************************************************************
- * Global pre-processor symbols/macros ('#define')
- ******************************************************************************/
-/**
- * @addtogroup STL_UTILITY_Global_Functions
- * @{
- */
-
-#if (STL_PRINT_ENABLE == STL_ON)
-#include <stdio.h>
-uint32_t STL_ConsoleOutputChar(char cData);
-#define STL_Printf                      (void)printf
-#else
-#define STL_Printf(...)
-#endif
-
-/**
- * @}
- */
-
-/*******************************************************************************
- * Global variable definitions ('extern')
- ******************************************************************************/
-
-/*******************************************************************************
- * Global function prototypes (definition in C source)
- ******************************************************************************/
-
-/**
- * @addgroup STL_Utility_Global_Functions
- * @{
- */
-void STL_DelayUS(uint32_t u32Count);
-void STL_DelayMS(uint32_t u32Count);
-
-void STL_SafetyFailure(void);
-
-uint32_t STL_PrintfInit(void);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STL_UTILITY_H__ */
-
-/*******************************************************************************
- * EOF (not truncated)
- ******************************************************************************/

bsp/hc32/libraries/hc32f460_ddl/config/linker/HC32F460_ram.icf

@@ -1,58 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x1FFF8000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_IROM1_start__ = 0x1FFF8000;
-define symbol __ICFEDIT_region_IROM1_end__   = 0x1FFFCFFF;
-define symbol __ICFEDIT_region_IROM2_start__ = 0x0;
-define symbol __ICFEDIT_region_IROM2_end__   = 0x0;
-define symbol __ICFEDIT_region_EROM1_start__ = 0x0;
-define symbol __ICFEDIT_region_EROM1_end__   = 0x0;
-define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
-define symbol __ICFEDIT_region_EROM2_end__   = 0x0;
-define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
-define symbol __ICFEDIT_region_EROM3_end__   = 0x0;
-define symbol __ICFEDIT_region_IRAM1_start__ = 0x1FFFD000;
-define symbol __ICFEDIT_region_IRAM1_end__   = 0x1FFFFFFF;
-define symbol __ICFEDIT_region_IRAM2_start__ = 0x20000000;
-define symbol __ICFEDIT_region_IRAM2_end__   = 0x2000FFFF;
-define symbol __ICFEDIT_region_IRAM3_start__ = 0x20010000;
-define symbol __ICFEDIT_region_IRAM3_end__   = 0x2001FFFF;
-define symbol __ICFEDIT_region_IRAM4_start__ = 0x20020000;
-define symbol __ICFEDIT_region_IRAM4_end__   = 0x20026FFF;
-define symbol __ICFEDIT_region_IRAM5_start__ = 0x200F0000;
-define symbol __ICFEDIT_region_IRAM5_end__   = 0x200F0FFF;
-define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
-define symbol __ICFEDIT_region_ERAM1_end__   = 0x0;
-define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
-define symbol __ICFEDIT_region_ERAM2_end__   = 0x0;
-define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
-define symbol __ICFEDIT_region_ERAM3_end__   = 0x0;
-
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x100;
-define symbol __ICFEDIT_size_proc_stack__ = 0x0;
-define symbol __ICFEDIT_size_heap__   = 0x100;
-/**** End of ICF editor section. ###ICF###*/
-
-define memory mem with size = 4G;
-define region ROM_region       = mem:[from __ICFEDIT_region_IROM1_start__   to __ICFEDIT_region_IROM1_end__];
-define region RAM_region       =   mem:[from __ICFEDIT_region_IRAM1_start__   to __ICFEDIT_region_IRAM1_end__]
-                                 | mem:[from __ICFEDIT_region_IRAM2_start__   to __ICFEDIT_region_IRAM2_end__]
-                                 | mem:[from __ICFEDIT_region_IRAM3_start__   to __ICFEDIT_region_IRAM3_end__]
-                                 | mem:[from __ICFEDIT_region_IRAM4_start__   to __ICFEDIT_region_IRAM4_end__]
-                                 | mem:[from __ICFEDIT_region_IRAM5_start__   to __ICFEDIT_region_IRAM5_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };

bsp/hc32/libraries/hc32f460_ddl/config/linker/HC32F460xC.icf

@@ -1,50 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x00000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_IROM1_start__  = 0x00000000;
-define symbol __ICFEDIT_region_IROM1_end__    = 0x0003FFFF;
-define symbol __ICFEDIT_region_IROM2_start__ = 0x03000C00;
-define symbol __ICFEDIT_region_IROM2_end__   = 0x03000FFB;
-define symbol __ICFEDIT_region_EROM1_start__ = 0x0;
-define symbol __ICFEDIT_region_EROM1_end__   = 0x0;
-define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
-define symbol __ICFEDIT_region_EROM2_end__   = 0x0;
-define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
-define symbol __ICFEDIT_region_EROM3_end__   = 0x0;
-define symbol __ICFEDIT_region_IRAM1_start__ = 0x1FFF8000;
-define symbol __ICFEDIT_region_IRAM1_end__   = 0x20026FFF;
-define symbol __ICFEDIT_region_IRAM2_start__ = 0x200F0000;
-define symbol __ICFEDIT_region_IRAM2_end__   = 0x200F0FFF;
-define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
-define symbol __ICFEDIT_region_ERAM1_end__   = 0x0;
-define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
-define symbol __ICFEDIT_region_ERAM2_end__   = 0x0;
-define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
-define symbol __ICFEDIT_region_ERAM3_end__   = 0x0;
-
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0xC00;
-define symbol __ICFEDIT_size_proc_stack__ = 0x0;
-define symbol __ICFEDIT_size_heap__   = 0x400;
-/**** End of ICF editor section. ###ICF###*/
-
-define memory mem with size = 4G;
-define region ROM_region       =   mem:[from __ICFEDIT_region_IROM1_start__   to __ICFEDIT_region_IROM1_end__]
-                                 | mem:[from __ICFEDIT_region_IROM2_start__   to __ICFEDIT_region_IROM2_end__];
-define region RAM_region       =   mem:[from __ICFEDIT_region_IRAM1_start__   to __ICFEDIT_region_IRAM1_end__]
-                                 | mem:[from __ICFEDIT_region_IRAM2_start__   to __ICFEDIT_region_IRAM2_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };

bsp/hc32/libraries/hc32f460_ddl/config/linker/HC32F460xE.icf

@@ -1,50 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x00000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_IROM1_start__ = 0x00000000;
-define symbol __ICFEDIT_region_IROM1_end__   = 0x0007FFFF;
-define symbol __ICFEDIT_region_IROM2_start__ = 0x03000C00;
-define symbol __ICFEDIT_region_IROM2_end__   = 0x03000FFB;
-define symbol __ICFEDIT_region_EROM1_start__ = 0x0;
-define symbol __ICFEDIT_region_EROM1_end__   = 0x0;
-define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
-define symbol __ICFEDIT_region_EROM2_end__   = 0x0;
-define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
-define symbol __ICFEDIT_region_EROM3_end__   = 0x0;
-define symbol __ICFEDIT_region_IRAM1_start__ = 0x1FFF8000;
-define symbol __ICFEDIT_region_IRAM1_end__   = 0x20026FFF;
-define symbol __ICFEDIT_region_IRAM2_start__ = 0x200F0000;
-define symbol __ICFEDIT_region_IRAM2_end__   = 0x200F0FFF;
-define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
-define symbol __ICFEDIT_region_ERAM1_end__   = 0x0;
-define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
-define symbol __ICFEDIT_region_ERAM2_end__   = 0x0;
-define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
-define symbol __ICFEDIT_region_ERAM3_end__   = 0x0;
-
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0xC00;
-define symbol __ICFEDIT_size_proc_stack__ = 0x0;
-define symbol __ICFEDIT_size_heap__   = 0x400;
-/**** End of ICF editor section. ###ICF###*/
-
-define memory mem with size = 4G;
-define region ROM_region       =   mem:[from __ICFEDIT_region_IROM1_start__   to __ICFEDIT_region_IROM1_end__]
-                                 | mem:[from __ICFEDIT_region_IROM2_start__   to __ICFEDIT_region_IROM2_end__];
-define region RAM_region       =   mem:[from __ICFEDIT_region_IRAM1_start__   to __ICFEDIT_region_IRAM1_end__]
-                                 | mem:[from __ICFEDIT_region_IRAM2_start__   to __ICFEDIT_region_IRAM2_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };

bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_common.h

@@ -1,145 +0,0 @@
-/**
- *******************************************************************************
- * @file  stl_common.h
- * @brief This file contains STL common definitions: enumeration, macros and
- *        structures definitions.
- @verbatim
-   Change Logs:
-   Date             Author          Notes
-   2022-03-31       CDT             First version
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- *                    opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-
-#ifndef __STL_COMMON_H__
-#define __STL_COMMON_H__
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "hc32_ll_def.h"
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/**
- * @addtogroup IEC60730_STL
- * @{
- */
-
-/**
- * @addtogroup IEC60730_STL_Common
- * @{
- */
-
-/*******************************************************************************
- * Global type definitions ('typedef')
-*******************************************************************************/
-
-/*******************************************************************************
- * Global pre-processor symbols/macros ('#define')
- ******************************************************************************/
-
-/**
- * @defgroup STL_Common_Global_Macros STL Common Global Macros
- * @{
- */
-
-/**
- * @defgroup STL_Generic_Error_Codes STL Generic Error Codes
- * @{
- */
-#define STL_OK                          (0UL)   /*!< No error occurs */
-#define STL_ERR                         (1UL)   /*!< Error occurs */
-/**
- * @}
- */
-
-/**
- * @defgroup STL_Module_Switch STL Module Switch
- * @{
- */
-#define STL_ON                          (1U)
-#define STL_OFF                         (0U)
-/**
- * @}
- */
-
-/**
- * @defgroup Compiler_Macros Compiler Macros
- * @{
- */
-#ifdef __CC_ARM                         /*!< ARM Compiler */
-/* CPU will start executing at the program entry label __main when the CPU is reset */
-extern void __main(void);
-
-/* CC */
-#define STL_SECTION(x)              __attribute__((section(x)))
-#define STL_UNUSED                  __attribute__((unused))
-#define STL_USED                    __attribute__((used))
-#define STL_ALIGN(n)                __attribute__((aligned(n)))
-#define STL_WEAK                    __WEAKDEF
-#define STL_INLINE                  static __inline
-
-#define CallApplicationStartUp( )   __main()
-
-#elif defined (__ICCARM__)              /*!< IAR Compiler */
-/* CPU will start executing at the program entry label __iar_program_start when the CPU is reset */
-extern void __iar_program_start(void);
-
-/* CC */
-#define STL_SECTION(x)              @ x
-#define STL_UNUSED
-#define STL_USED                    __root
-#define STL_PRAGMA(x)               _Pragma(#x)
-#define STL_ALIGN(n)                STL_PRAGMA(data_alignment=n)
-#define STL_WEAK                    __WEAKDEF
-#define STL_INLINE                  static inline
-
-#define CallApplicationStartUp( )   __iar_program_start()
-#else
-#error Unsupported tool chain
-#endif
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/*******************************************************************************
- * Global variable definitions ('extern')
- ******************************************************************************/
-
-/*******************************************************************************
- * Global function prototypes (definition in C source)
- ******************************************************************************/
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STL_COMMON_H__ */
-
-/*******************************************************************************
- * EOF (not truncated)
- ******************************************************************************/

bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_conf.h

@@ -1,106 +0,0 @@
-/**
- *******************************************************************************
- * @file  stl_conf.h
- * @brief This file contains STL resource configure.
- @verbatim
-   Change Logs:
-   Date             Author          Notes
-   2022-03-31       CDT             First version
-   2022-06-30       CDT             Optimize macros definitions
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- *                    opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-
-#ifndef __STL_CONF_H__
-#define __STL_CONF_H__
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "stl_bsp_conf.h"
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/**
- * @addtogroup IEC60730_STL
- * @{
- */
-
-/**
- * @addtogroup IEC60730_STL_Configure
- * @{
- */
-
-/*******************************************************************************
- * Global type definitions ('typedef')
-*******************************************************************************/
-
-/*******************************************************************************
- * Global pre-processor symbols/macros ('#define')
- ******************************************************************************/
-
-/**
- * @defgroup IEC60730_STL_Configure_ROM_CRC32_Parameters IEC60730 STL Configure ROM CRC32 Parameters
- * @{
- */
-#define STL_ROM_CRC32_START             (STL_ROM_START)
-#define STL_ROM_CRC32_END               ((uint32_t)(&__checksum))
-#define STL_ROM_CRC32_BLOCK_SIZE        (128UL)
-#define STL_ROM_CRC32_CC_CHECKSUM       (__checksum)
-/**
- * @}
- */
-
-/**
- * @defgroup IEC60730_STL_Configure_RAM_Parameters IEC60730 STL Configure RAM Parameters
- * @{
- */
-#define STL_MARCH_RAM_SIZE              (32UL)
-#define STL_MARCH_RAM_WORDS             (STL_MARCH_RAM_SIZE >> 2)
-#define STL_MARCH_RAM_BUF_SIZE          (16UL)
-#define STL_MARCH_RAM_BUF_WORDS         (STL_MARCH_RAM_BUF_SIZE >> 2)
-
-#define STL_MARCH_RAM_BCKGRND           (0x00000000UL)
-#define STL_MARCH_RAM_INVBCKGRND        (0xFFFFFFFFUL)
-
-#define STL_STACK_BOUNDARY_WORDS        (4UL)
-/**
- * @}
- */
-
-/*******************************************************************************
- * Global variable definitions ('extern')
- ******************************************************************************/
-
-/*******************************************************************************
- * Global function prototypes (definition in C source)
- ******************************************************************************/
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STL_CONF_H__ */
-
-/*******************************************************************************
- * EOF (not truncated)
- ******************************************************************************/

bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_sw_crc32.h

@@ -1,93 +0,0 @@
-/**
- *******************************************************************************
- * @file  stl_test_flash.h
- * @brief This file contains all the functions prototypes of the flash test.
- @verbatim
-   Change Logs:
-   Date             Author          Notes
-   2022-03-31       CDT             First version
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- *                    opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-
-#ifndef __STL_SW_CRC32_H__
-#define __STL_SW_CRC32_H__
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "stl_common.h"
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/**
- * @addtogroup STL_IEC60730
- * @{
- */
-
-/**
- * @addtogroup STL_IEC60730_CRC32
- * @{
- */
-
-/*******************************************************************************
- * Global type definitions ('typedef')
-*******************************************************************************/
-
-/*******************************************************************************
- * Global pre-processor symbols/macros ('#define')
- ******************************************************************************/
-
-/**
- * @defgroup STL_IEC60730_CRC32_Global_Macros STL IEC60730 CRC32 Global Macros
- * @{
- */
-#define STL_CRC32_INIT_VALUE    (0xFFFFFFFFUL)
-/**
- * @}
- */
-
-/*******************************************************************************
- * Global variable definitions ('extern')
- ******************************************************************************/
-
-/*******************************************************************************
- * Global function prototypes (definition in C source)
- ******************************************************************************/
-/**
- * @addtogroup STL_IEC60730_CRC32_Global_Functions
- * @{
- */
-uint32_t STL_CalculateCRC32Value(uint32_t u32Crc32Value, uint8_t *pu8Data, uint32_t u32Len);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STL_SW_CRC32_H__ */
-
-/*******************************************************************************
- * EOF (not truncated)
- ******************************************************************************/

bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_cpu.h

@@ -1,85 +0,0 @@
-/**
- *******************************************************************************
- * @file  stl_test_cpu.h
- * @brief This file contains all the functions prototypes of the CPU test.
- @verbatim
-   Change Logs:
-   Date             Author          Notes
-   2022-03-31       CDT             First version
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- *                    opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-
-#ifndef __STL_TEST_CPU_H__
-#define __STL_TEST_CPU_H__
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "stl_common.h"
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/**
- * @addtogroup STL_IEC60730
- * @{
- */
-
-/**
- * @addtogroup STL_IEC60730_CPU
- * @{
- */
-
-/*******************************************************************************
- * Global type definitions ('typedef')
-*******************************************************************************/
-
-/*******************************************************************************
- * Global pre-processor symbols/macros ('#define')
- ******************************************************************************/
-
-/*******************************************************************************
- * Global variable definitions ('extern')
- ******************************************************************************/
-
-/*******************************************************************************
- * Global function prototypes (definition in C source)
- ******************************************************************************/
-/**
- * @addtogroup STL_IEC60730_CPU_Global_Functions
- * @{
- */
-uint32_t STL_CpuTestStartup(void);
-uint32_t STL_CpuTestRuntime(void);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STL_TEST_CPU_H__ */
-
-/*******************************************************************************
- * EOF (not truncated)
- ******************************************************************************/

bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_flash.h

@@ -1,85 +0,0 @@
-/**
- *******************************************************************************
- * @file  stl_test_flash.h
- * @brief This file contains all the functions prototypes of the flash test.
- @verbatim
-   Change Logs:
-   Date             Author          Notes
-   2022-03-31       CDT             First version
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- *                    opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-
-#ifndef __STL_TEST_FLASH_H__
-#define __STL_TEST_FLASH_H__
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "stl_common.h"
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/**
- * @addtogroup STL_IEC60730
- * @{
- */
-
-/**
- * @addtogroup STL_IEC60730_Flash
- * @{
- */
-
-/*******************************************************************************
- * Global type definitions ('typedef')
-*******************************************************************************/
-
-/*******************************************************************************
- * Global pre-processor symbols/macros ('#define')
- ******************************************************************************/
-
-/*******************************************************************************
- * Global variable definitions ('extern')
- ******************************************************************************/
-
-/*******************************************************************************
- * Global function prototypes (definition in C source)
- ******************************************************************************/
-/**
- * @addtogroup STL_IEC60730_Flash_Global_Functions
- * @{
- */
-uint32_t STL_FlashStartupTest(void);
-uint32_t STL_FlashRuntimeTest(void);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STL_TEST_FLASH_H__ */
-
-/*******************************************************************************
- * EOF (not truncated)
- ******************************************************************************/

bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_interrupt.h

@@ -1,99 +0,0 @@
-/**
- *******************************************************************************
- * @file  stl_test_interrupt.h
- * @brief This file contains all the functions prototypes of the interrupt test.
- @verbatim
-   Change Logs:
-   Date             Author          Notes
-   2022-03-31       CDT             First version
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- *                    opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-
-#ifndef __STL_TEST_INTERRUPT_H__
-#define __STL_TEST_INTERRUPT_H__
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "stl_common.h"
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/**
- * @addtogroup STL_IEC60730
- * @{
- */
-
-/**
- * @addtogroup STL_IEC60730_Interrupt
- * @{
- */
-
-/*******************************************************************************
- * Global type definitions ('typedef')
-*******************************************************************************/
-/**
- * @defgroup STL_IEC60730_Interrupt_Global_Type STL IEC60730 Interrupt Global Type
- * @{
- */
-typedef struct stc_stl_int_params {
-    uint32_t u32FreqInitVal;
-    uint32_t u32FreqLowerVal;
-    uint32_t u32FreqUpperVal;
-    uint32_t u32PrivateParam;
-} stc_stl_int_params_t;
-/**
- * @}
- */
-
-/*******************************************************************************
- * Global pre-processor symbols/macros ('#define')
- ******************************************************************************/
-
-/*******************************************************************************
- * Global variable definitions ('extern')
- ******************************************************************************/
-
-/*******************************************************************************
- * Global function prototypes (definition in C source)
- ******************************************************************************/
-/**
- * @addtogroup STL_IEC60730_Interrupt_Global_Functions
- * @{
- */
-uint32_t STL_IntRuntimeTableInit(stc_stl_int_params_t *pstcParamsTable, uint32_t u32TableSize);
-uint32_t STL_IntRuntimeTest(void);
-void STL_IntUpdateCount(uint8_t u8ParamIndex);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STL_TEST_INTERRUPT_H__ */
-
-/*******************************************************************************
- * EOF (not truncated)
- ******************************************************************************/

bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_ram.h

@@ -1,88 +0,0 @@
-/**
- *******************************************************************************
- * @file  stl_test_ram.h
- * @brief This file contains all the functions prototypes of the RAM test.
- @verbatim
-   Change Logs:
-   Date             Author          Notes
-   2022-03-31       CDT             First version
- @endverbatim
- *******************************************************************************
- * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
- *
- * This software component is licensed by XHSC under BSD 3-Clause license
- * (the "License"); You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- *                    opensource.org/licenses/BSD-3-Clause
- *
- *******************************************************************************
- */
-
-#ifndef __STL_TEST_RAM_H__
-#define __STL_TEST_RAM_H__
-
-/*******************************************************************************
- * Include files
- ******************************************************************************/
-#include "stl_common.h"
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/**
- * @addtogroup STL_IEC60730
- * @{
- */
-
-/**
- * @addtogroup STL_IEC60730_RAM
- * @{
- */
-
-/*******************************************************************************
- * Global type definitions ('typedef')
-*******************************************************************************/
-
-/*******************************************************************************
- * Global pre-processor symbols/macros ('#define')
- ******************************************************************************/
-
-/*******************************************************************************
- * Global variable definitions ('extern')
- ******************************************************************************/
-
-/*******************************************************************************
- * Global function prototypes (definition in C source)
- ******************************************************************************/
-/**
- * @addtogroup STL_IEC60730_RAM_Global_Functions
- * @{
- */
-uint32_t STL_StackRuntimeInit(void);
-uint32_t STL_StackRuntimeTest(void);
-uint32_t STL_RamRuntimeInit(void);
-uint32_t STL_RamRuntimeTest(void);
-uint32_t STL_FullRamTestStartup(uint32_t u32StartAddr, uint32_t u32EndAddr);
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STL_TEST_RAM_H__ */
-
-/*******************************************************************************
- * EOF (not truncated)
- ******************************************************************************/

bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/EWARM/stl_test_cpu_cm0_startup.s

@@ -1,372 +0,0 @@
-;/*****************************************************************************
-; * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
-; *
-; * This software component is licensed by XHSC under BSD 3-Clause license
-; * (the "License"); You may not use this file except in compliance with the
-; * License. You may obtain a copy of the License at:
-; *                    opensource.org/licenses/BSD-3-Clause
-; *
-; */
-;/****************************************************************************/
-;/*  Test for IAR                                                            */
-;/*  Version     V1.0                                                        */
-;/*  Date        2022-09-14                                                  */
-;/****************************************************************************/
-
-            SECTION constdata:CONST(2)
-data0xAAAAAAAA       DCD     0xAAAAAAAA
-data0x55555555       DCD     0x55555555
-data0x80000000       DCD     0x80000000
-data0xAAAAAAA8       DCD     0xAAAAAAA8
-data0x55555554       DCD     0x55555554
-data0x00000000       DCD     0x00000000
-data0x00000001       DCD     0x00000001
-data0x50000000       DCD     0x50000000
-data0xA0000000       DCD     0xA0000000
-
-            ; Exported function
-            EXPORT STL_CpuTestStartup
-
-;*******************************************************************************
-; Function Name  : STL_CpuTestStartup
-; Description    : Test CPU at start-up
-; Input          : None.
-; Output         : Perform routine when detect failure at set of self test cases
-; Return         : STL_OK (=0):test pass; STL_ERR (=1):test fail;
-; WARNING        : all registers destroyed when exiting this function (including
-;                  preserved registers R4 to R11) and excluding stack point R13)
-;*******************************************************************************/
-            THUMB
-            SECTION .text:CODE(2)
-STL_CpuTestStartup:
-            PUSH {R4-R7}                         ; Save registers
-
-_test_cpu_reg0_reg8
-            MOVS R0, #0x00
-            UXTB R0, R0
-            ADDS R0, #0                          ; Set Z(ero) Flag
-            BNE _test_cpu_reg0_reg13_fail        ; Fails if Z clear
-            BMI _test_cpu_reg0_reg13_fail        ; Fails if N is set
-            SUBS R0, #1                          ; Set N(egative) Flag
-            BPL _test_cpu_reg0_reg13_fail        ; Fails if N clear
-            ADDS R0, #2                          ; Set C(arry) Flag and do not set Z
-            BCC _test_cpu_reg0_reg13_fail        ; Fails if C clear
-            BEQ _test_cpu_reg0_reg13_fail        ; Fails if Z is set
-            BMI _test_cpu_reg0_reg13_fail        ; Fails if N is set
-
-            LDR R0, =data0x80000000              ; Prepares Overflow test
-            LDR R0, [R0]
-            ADDS R0, R0, R0                      ; Set V(overflow) Flag
-            BVC _test_cpu_reg0_reg13_fail        ; Fails if V clear
-
-            ; Register R1
-            LDR R0, =data0xAAAAAAAA
-            LDR R1, [R0]
-            LDR R0, [R0]
-            CMP R0, R1
-            BNE _test_cpu_reg0_reg13_fail
-            LDR R0, =data0x55555555
-            LDR R1, [R0]
-            LDR R0, [R0]
-            CMP R0, R1
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R1, #0x1
-
-            ; Register R2
-            LDR R0, =data0xAAAAAAAA
-            LDR R2, [R0]
-            LDR R0, [R0]
-            CMP R0, R2
-            BNE _test_cpu_reg0_reg13_fail
-            LDR R0, =data0x55555555
-            LDR R2, [R0]
-            LDR R0, [R0]
-            CMP R0, R2
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R2, #0x2
-
-            ; Register R3
-            LDR R0, =data0xAAAAAAAA
-            LDR R3, [R0]
-            LDR R0, [R0]
-            CMP R0, R3
-            BNE _test_cpu_reg0_reg13_fail
-            LDR R0, =data0x55555555
-            LDR R3, [R0]
-            LDR R0, [R0]
-            CMP R0, R3
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R3, #0x3
-
-            ; Register R4
-            LDR R0, =data0xAAAAAAAA
-            LDR R4, [R0]
-            LDR R0, [R0]
-            CMP R0, R4
-            BNE _test_cpu_reg0_reg13_fail
-            LDR R0, =data0x55555555
-            LDR R4, [R0]
-            LDR R0, [R0]
-            CMP R0, R4
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R4, #0x4
-
-            ; Register R5
-            LDR R0, =data0xAAAAAAAA
-            LDR R5, [R0]
-            LDR R0, [R0]
-            CMP R0, R5
-            BNE _test_cpu_reg0_reg13_fail
-            LDR R0, =data0x55555555
-            LDR R5, [R0]
-            LDR R0, [R0]
-            CMP R0, R5
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R5, #0x5
-
-            ; Register R6
-            LDR R0, =data0xAAAAAAAA
-            LDR R6, [R0]
-            LDR R0, [R0]
-            CMP R0, R6
-            BNE _test_cpu_reg0_reg13_fail
-            LDR R0, =data0x55555555
-            LDR R6, [R0]
-            LDR R0, [R0]
-            CMP R0, R6
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R6, #0x6
-
-            ; Register R7
-            LDR R0, =data0xAAAAAAAA
-            LDR R7, [R0]
-            LDR R0, [R0]
-            CMP R0, R7
-            BNE _test_cpu_reg0_reg13_fail
-            LDR R0, =data0x55555555
-            LDR R7, [R0]
-            LDR R0, [R0]
-            CMP R0, R7
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R7, #0x7
-
-            ; Register R8
-            LDR R0, =data0xAAAAAAAA
-            LDR R0, [R0]
-            MOV R8, R0
-            CMP R0, R8
-            BNE _test_cpu_reg0_reg13_fail
-            LDR R0, =data0x55555555
-            LDR R0, [R0]
-            MOV R8, R0
-            CMP R0, R8
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R0, #0x08
-            MOV R8, R0
-
-            BAL _test_cpu_continue
-
-_test_cpu_reg0_reg13_fail
-            ; test fail, R0 will hold value 1
-            MOVS R0, #0x1                        ; STL_ERR
-            B _test_exit
-
-_test_cpu_continue
-            ; Register R9
-            LDR R0, =data0xAAAAAAAA
-            LDR R0, [R0]
-            MOV R9, R0
-            CMP R0, R9
-            BNE _test_cpu_reg0_reg13_fail
-            LDR R0, =data0x55555555
-            LDR R0, [R0]
-            MOV R9, R0
-            CMP R0, R9
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R0, #0x09
-            MOV R9, R0
-
-            ; Register R10
-            LDR R0, =data0xAAAAAAAA
-            LDR R0, [R0]
-            MOV R10, R0
-            CMP R0, R10
-            BNE _test_cpu_reg0_reg13_fail
-            LDR R0, =data0x55555555
-            LDR R0, [R0]
-            MOV R10, R0
-            CMP R0, R10
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R0, #0x0A
-            MOV R10, R0
-
-            ; Register R11
-            LDR R0, =data0xAAAAAAAA
-            LDR R0, [R0]
-            MOV R11, R0
-            CMP R0, R11
-            BNE _test_cpu_reg0_reg13_fail
-            LDR R0, =data0x55555555
-            LDR R0, [R0]
-            MOV R11, R0
-            CMP R0, R11
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R0, #0x0B
-            MOV R11, R0
-
-            ; Register R12
-            LDR R0, =data0xAAAAAAAA
-            LDR R0, [R0]
-            MOV R12, R0
-            CMP R0, R12
-            BNE _test_cpu_reg0_reg13_fail
-            LDR R0, =data0x55555555
-            LDR R0, [R0]
-            MOV R12, R0
-            CMP R0, R12
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R0, #0x0C
-            MOV R12, R0
-            LDR R0, =_test_cpu_continue
-
-            ; pattern verification (R0 is not tested)
-            CMP R1, #0x01
-            BNE _test_cpu_reg0_reg13_fail
-            CMP R2, #0x02
-            BNE _test_cpu_reg0_reg13_fail
-            CMP R3, #0x03
-            BNE _test_cpu_reg0_reg13_fail
-            CMP R4, #0x04
-            BNE _test_cpu_reg0_reg13_fail
-            CMP R5, #0x05
-            BNE _test_cpu_reg0_reg13_fail
-            CMP R6, #0x06
-            BNE _test_cpu_reg0_reg13_fail
-            CMP R7, #0x07
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R0, #0x08
-            CMP R0, R8
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R0, #0x09
-            CMP R0, R9
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R0, #0x0A
-            CMP R0, R10
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R0, #0x0B
-            CMP R0, R11
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R0, #0x0C
-            CMP R0, R12
-            BNE _test_cpu_reg0_reg13_fail
-
-            ; Process Stack pointer (banked Register R13)
-            MRS R0, PSP                          ; Save process stack value
-            LDR R1, =data0xAAAAAAA8              ; Test is different (PSP is word aligned, 2 LSB cleared)
-            LDR R1, [R1]
-            MSR PSP, R1                          ; load process stack value
-            MRS R2, PSP                          ; Get back process stack value
-            CMP R2, R1                           ; Verify value
-            BNE _test_cpu_reg0_reg13_fail
-            LDR R1, =data0x55555554              ; Test is different (PSP is word aligned, 2 LSB cleared)
-            LDR R1, [R1]
-            MSR PSP, R1                          ; load process stack value
-            MRS R2, PSP                          ; Get back process stack value
-            CMP R2, R1                           ; Verify value
-            BNE _test_cpu_reg0_reg13_fail
-            MSR PSP, R0                          ; Restore process stack value
-
-            ; Stack pointer (Register R13)
-            MRS R0, MSP                          ; Save stack pointer value
-            LDR R1, =data0xAAAAAAA8              ; Test is different (SP is word aligned, 2 LSB cleared)
-            LDR R1, [R1]
-            MSR MSP, R1                          ; load SP value
-            MRS R2, MSP                          ; Get back SP value
-            CMP R2, R1                           ; Verify value
-            BNE _test_cpu_reg0_reg13_fail
-            LDR R1, =data0x55555554
-            LDR R1, [R1]                         ; load SP value
-            MSR MSP, R1                          ; Get back SP value
-            MRS R2, MSP                          ; Verify value
-            CMP R2, R1
-            BNE _test_cpu_reg0_reg13_fail
-            MSR MSP, R0                          ; Restore stack pointer value
-
-_test_cpu_r14_sfr
-            ; Link register R14
-            MOV R1, LR
-            LDR R0, =data0x55555555
-            LDR R0, [R0]
-            MOV R14, R0
-            CMP R0, R14
-            BNE _test_cpu_r14_sfr_fail
-
-            LDR R0, =data0xAAAAAAAA
-            LDR R0, [R0]
-            MOV R14, R0
-            CMP R0, R14
-            BNE _test_cpu_r14_sfr_fail
-
-            LDR R0, =data0x55555555
-            LDR R0, [R0]
-            MOV R14, R0
-            CMP R0, R14
-            BNE _test_cpu_r14_sfr_fail
-
-            LDR R0, =data0xAAAAAAAA
-            LDR R0, [R0]
-            MOV R14, R0
-            CMP R0, R14
-            BNE _test_cpu_r14_sfr_fail
-            MOV LR, R1
-
-            ; APSR
-            MRS R0, APSR
-            LDR R1, =data0x50000000
-            LDR R1,[R1]
-            MSR APSR,R1
-            MRS R2, APSR
-            CMP R1, R2
-            BNE _test_cpu_r14_sfr_fail
-
-            LDR R1, =data0xA0000000
-            LDR R1,[R1]
-            MSR APSR,R1
-            MRS R2, APSR
-            CMP R1, R2
-            BNE _test_cpu_r14_sfr_fail
-            MSR APSR,R0
-
-            ; PRIMASK register
-            MRS R0, PRIMASK
-            LDR R1, =data0x00000000
-            LDR R1, [R1]
-            MSR PRIMASK, R1
-            MRS R2, PRIMASK
-            CMP R1, R2
-            BNE _test_cpu_r14_sfr_fail
-
-            LDR R1, =data0x00000001
-            LDR R1, [R1]
-            MSR PRIMASK, R1
-            MRS R2, PRIMASK
-            CMP R1, R2
-            BNE _test_cpu_r14_sfr_fail
-            MSR PRIMASK, R0
-            B _test_cpu_pass
-
-_test_cpu_r14_sfr_fail
-            ; test fail, R0 will hold value 1
-            MOVS R0, #0x1                        ; STL_ERR
-            B _test_exit
-
-_test_cpu_pass
-            ; test pass, R0 will hold value 0
-            MOVS R0, #0x0                        ; STL_OK
-            B _test_exit
-
-_test_exit
-            POP {R4-R7}                          ; Restore registers
-            BX LR
-
-            END

bsp/hc32/libraries/hc32f460_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/EWARM/stl_test_cpu_cm4_startup.s

@@ -1,420 +0,0 @@
-;/*****************************************************************************
-; * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
-; *
-; * This software component is licensed by XHSC under BSD 3-Clause license
-; * (the "License"); You may not use this file except in compliance with the
-; * License. You may obtain a copy of the License at:
-; *                    opensource.org/licenses/BSD-3-Clause
-; *
-; */
-;/****************************************************************************/
-;/*  Test for IAR                                                            */
-;/*  Date             Author          Notes                                  */
-;/*  2022-09-14       CDT             First version                          */
-;/*  2022-12-20       CDT             Load data to R0 before USAT            */
-;/*  2023-05-31       CDT             Typo: Veriry -> Verify                 */
-;/****************************************************************************/
-
-            SECTION constdata:CONST(2)
-data0xAAAAAAAA       DCD     0xAAAAAAAA
-data0x55555555       DCD     0x55555555
-data0x80000000       DCD     0x80000000
-data0xAAAAAAA8       DCD     0xAAAAAAA8
-data0x55555554       DCD     0x55555554
-data0x00000000       DCD     0x00000000
-data0x00000001       DCD     0x00000001
-data0x50000000       DCD     0x50000000
-data0xA8000000       DCD     0xA8000000
-data0x00000050       DCD     0x00000050
-data0x000000A0       DCD     0x000000A0
-data0xFFFFFFFF       DCD     0xFFFFFFFF
-
-            ; Exported function
-            EXPORT STL_CpuTestStartup
-
-;*******************************************************************************
-; Function Name  : STL_CpuTestStartup
-; Description    : Test CPU at start-up
-; Input          : None.
-; Output         : Perform routine when detect failure at set of self test cases
-; Return         : STL_OK (=0):test pass; STL_ERR (=1):test fail;
-; WARNING        : all registers destroyed when exiting this function (including
-;                  preserved registers R4 to R11) and excluding stack point R13)
-;*******************************************************************************/
-            THUMB
-            SECTION .text:CODE(2)
-STL_CpuTestStartup:
-            PUSH {R4-R7}                         ; Save registers
-
-_test_cpu_reg0_reg8
-            MOVS R0, #0x00
-            UXTB R0, R0
-            ADDS R0, #0                          ; Set Z(ero) Flag
-            BNE _test_cpu_reg0_reg13_fail        ; Fails if Z clear
-            BMI _test_cpu_reg0_reg13_fail        ; Fails if N is set
-            SUBS R0, #1                          ; Set N(egative) Flag
-            BPL _test_cpu_reg0_reg13_fail        ; Fails if N clear
-            ADDS R0, #2                          ; Set C(arry) Flag and do not set Z
-            BCC _test_cpu_reg0_reg13_fail        ; Fails if C clear
-            BEQ _test_cpu_reg0_reg13_fail        ; Fails if Z is set
-            BMI _test_cpu_reg0_reg13_fail        ; Fails if N is set
-
-            LDR R0, =data0x80000000              ; Prepares Overflow test
-            LDR R0, [R0]
-            ADDS R0, R0, R0                      ; Set V(overflow) Flag
-            BVC _test_cpu_reg0_reg13_fail        ; Fails if V clear
-
-            MOV R0, #0
-            MSR APSR, R0
-            LDR R0, =data0xFFFFFFFF              ; Prepares Saturation test
-            LDR R0, [R0]
-            USAT R1, #10, R0                     ; Set Q(saturation) flag
-            MRS R0, APSR                         ; Get APSR status register
-            CMP R0, #0x08000000                  ; Verify Q=1
-            BNE _test_cpu_reg0_reg13_fail        ; Fails if Q is set
-
-            ; Register R1
-            LDR R0, =data0xAAAAAAAA
-            LDR R1, [R0]
-            LDR R0, [R0]
-            CMP R0, R1
-            BNE _test_cpu_reg0_reg13_fail
-            LDR R0, =data0x55555555
-            LDR R1, [R0]
-            LDR R0, [R0]
-            CMP R0, R1
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R1, #0x1
-
-            ; Register R2
-            LDR R0, =data0xAAAAAAAA
-            LDR R2, [R0]
-            LDR R0, [R0]
-            CMP R0, R2
-            BNE _test_cpu_reg0_reg13_fail
-            LDR R0, =data0x55555555
-            LDR R2, [R0]
-            LDR R0, [R0]
-            CMP R0, R2
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R2, #0x2
-
-            ; Register R3
-            LDR R0, =data0xAAAAAAAA
-            LDR R3, [R0]
-            LDR R0, [R0]
-            CMP R0, R3
-            BNE _test_cpu_reg0_reg13_fail
-            LDR R0, =data0x55555555
-            LDR R3, [R0]
-            LDR R0, [R0]
-            CMP R0, R3
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R3, #0x3
-
-            ; Register R4
-            LDR R0, =data0xAAAAAAAA
-            LDR R4, [R0]
-            LDR R0, [R0]
-            CMP R0, R4
-            BNE _test_cpu_reg0_reg13_fail
-            LDR R0, =data0x55555555
-            LDR R4, [R0]
-            LDR R0, [R0]
-            CMP R0, R4
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R4, #0x4
-
-            ; Register R5
-            LDR R0, =data0xAAAAAAAA
-            LDR R5, [R0]
-            LDR R0, [R0]
-            CMP R0, R5
-            BNE _test_cpu_reg0_reg13_fail
-            LDR R0, =data0x55555555
-            LDR R5, [R0]
-            LDR R0, [R0]
-            CMP R0, R5
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R5, #0x5
-
-            ; Register R6
-            LDR R0, =data0xAAAAAAAA
-            LDR R6, [R0]
-            LDR R0, [R0]
-            CMP R0, R6
-            BNE _test_cpu_reg0_reg13_fail
-            LDR R0, =data0x55555555
-            LDR R6, [R0]
-            LDR R0, [R0]
-            CMP R0, R6
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R6, #0x6
-
-            ; Register R7
-            LDR R0, =data0xAAAAAAAA
-            LDR R7, [R0]
-            LDR R0, [R0]
-            CMP R0, R7
-            BNE _test_cpu_reg0_reg13_fail
-            LDR R0, =data0x55555555
-            LDR R7, [R0]
-            LDR R0, [R0]
-            CMP R0, R7
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R7, #0x7
-
-            ; Register R8
-            LDR R0, =data0xAAAAAAAA
-            LDR R0, [R0]
-            MOV R8, R0
-            CMP R0, R8
-            BNE _test_cpu_reg0_reg13_fail
-            LDR R0, =data0x55555555
-            LDR R0, [R0]
-            MOV R8, R0
-            CMP R0, R8
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R0, #0x08
-            MOV R8, R0
-
-            BAL _test_cpu_continue
-
-_test_cpu_reg0_reg13_fail
-            ; test fail, R0 will hold value 1
-            MOVS R0, #0x1                        ; STL_ERR
-            B _test_exit
-
-_test_cpu_continue
-            ; Register R9
-            LDR R0, =data0xAAAAAAAA
-            LDR R0, [R0]
-            MOV R9, R0
-            CMP R0, R9
-            BNE _test_cpu_reg0_reg13_fail
-            LDR R0, =data0x55555555
-            LDR R0, [R0]
-            MOV R9, R0
-            CMP R0, R9
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R0, #0x09
-            MOV R9, R0
-
-            ; Register R10
-            LDR R0, =data0xAAAAAAAA
-            LDR R0, [R0]
-            MOV R10, R0
-            CMP R0, R10
-            BNE _test_cpu_reg0_reg13_fail
-            LDR R0, =data0x55555555
-            LDR R0, [R0]
-            MOV R10, R0
-            CMP R0, R10
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R0, #0x0A
-            MOV R10, R0
-
-            ; Register R11
-            LDR R0, =data0xAAAAAAAA
-            LDR R0, [R0]
-            MOV R11, R0
-            CMP R0, R11
-            BNE _test_cpu_reg0_reg13_fail
-            LDR R0, =data0x55555555
-            LDR R0, [R0]
-            MOV R11, R0
-            CMP R0, R11
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R0, #0x0B
-            MOV R11, R0
-
-            ; Register R12
-            LDR R0, =data0xAAAAAAAA
-            LDR R0, [R0]
-            MOV R12, R0
-            CMP R0, R12
-            BNE _test_cpu_reg0_reg13_fail
-            LDR R0, =data0x55555555
-            LDR R0, [R0]
-            MOV R12, R0
-            CMP R0, R12
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R0, #0x0C
-            MOV R12, R0
-            LDR R0, =_test_cpu_continue
-
-            ; pattern verification (R0 is not tested)
-            CMP R1, #0x01
-            BNE _test_cpu_reg0_reg13_fail
-            CMP R2, #0x02
-            BNE _test_cpu_reg0_reg13_fail
-            CMP R3, #0x03
-            BNE _test_cpu_reg0_reg13_fail
-            CMP R4, #0x04
-            BNE _test_cpu_reg0_reg13_fail
-            CMP R5, #0x05
-            BNE _test_cpu_reg0_reg13_fail
-            CMP R6, #0x06
-            BNE _test_cpu_reg0_reg13_fail
-            CMP R7, #0x07
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R0, #0x08
-            CMP R0, R8
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R0, #0x09
-            CMP R0, R9
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R0, #0x0A
-            CMP R0, R10
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R0, #0x0B
-            CMP R0, R11
-            BNE _test_cpu_reg0_reg13_fail
-            MOVS R0, #0x0C
-            CMP R0, R12
-            BNE _test_cpu_reg0_reg13_fail
-
-            ; Process Stack pointer (banked Register R13)
-            MRS R0, PSP                          ; Save process stack value
-            LDR R1, =data0xAAAAAAA8              ; Test is different (PSP is word aligned, 2 LSB cleared)
-            LDR R1, [R1]
-            MSR PSP, R1                          ; load process stack value
-            MRS R2, PSP                          ; Get back process stack value
-            CMP R2, R1                           ; Verify value
-            BNE _test_cpu_reg0_reg13_fail
-            LDR R1, =data0x55555554              ; Test is different (PSP is word aligned, 2 LSB cleared)
-            LDR R1, [R1]
-            MSR PSP, R1                          ; load process stack value
-            MRS R2, PSP                          ; Get back process stack value
-            CMP R2, R1                           ; Verify value
-            BNE _test_cpu_reg0_reg13_fail
-            MSR PSP, R0                          ; Restore process stack value
-
-            ; Stack pointer (Register R13)
-            MRS R0, MSP                          ; Save stack pointer value
-            LDR R1, =data0xAAAAAAA8              ; Test is different (SP is word aligned, 2 LSB cleared)
-            LDR R1, [R1]
-            MSR MSP, R1                          ; load SP value
-            MRS R2, MSP                          ; Get back SP value
-            CMP R2, R1                           ; Verify value
-            BNE _test_cpu_reg0_reg13_fail
-            LDR R1, =data0x55555554
-            LDR R1, [R1]                         ; load SP value
-            MSR MSP, R1                          ; Get back SP value
-            MRS R2, MSP                          ; Verify value
-            CMP R2, R1
-            BNE _test_cpu_reg0_reg13_fail
-            MSR MSP, R0                          ; Restore stack pointer value
-
-_test_cpu_r14_sfr
-            ; Link register R14
-            MOV R1, LR
-            LDR R0, =data0x55555555
-            LDR R0, [R0]
-            MOV R14, R0
-            CMP R0, R14
-            BNE _test_cpu_r14_sfr_fail
-
-            LDR R0, =data0xAAAAAAAA
-            LDR R0, [R0]
-            MOV R14, R0
-            CMP R0, R14
-            BNE _test_cpu_r14_sfr_fail
-
-            LDR R0, =data0x55555555
-            LDR R0, [R0]
-            MOV R14, R0
-            CMP R0, R14
-            BNE _test_cpu_r14_sfr_fail
-
-            LDR R0, =data0xAAAAAAAA
-            LDR R0, [R0]
-            MOV R14, R0
-            CMP R0, R14
-            BNE _test_cpu_r14_sfr_fail
-            MOV LR, R1
-
-            ; APSR
-            MRS R0, APSR
-            LDR R1, =data0x50000000
-            LDR R1,[R1]
-            MSR APSR,R1
-            MRS R2, APSR
-            CMP R1, R2
-            BNE _test_cpu_r14_sfr_fail
-
-            LDR R1, =data0xA8000000
-            LDR R1,[R1]
-            MSR APSR,R1
-            MRS R2, APSR
-            CMP R1, R2
-            BNE _test_cpu_r14_sfr_fail
-            MSR APSR,R0
-
-            ; PRIMASK register
-            MRS R0, PRIMASK
-            LDR R1, =data0x00000000
-            LDR R1, [R1]
-            MSR PRIMASK, R1
-            MRS R2, PRIMASK
-            CMP R1, R2
-            BNE _test_cpu_r14_sfr_fail
-
-            LDR R1, =data0x00000001
-            LDR R1, [R1]
-            MSR PRIMASK, R1
-            MRS R2, PRIMASK
-            CMP R1, R2
-            BNE _test_cpu_r14_sfr_fail
-            MSR PRIMASK, R0
-
-            ; FAULTMASK register
-            MRS R0, FAULTMASK
-            LDR R1, =data0x00000000
-            LDR R1, [R1]
-            MSR FAULTMASK, R1
-            MRS R2, FAULTMASK
-            CMP R1, R2
-            BNE _test_cpu_r14_sfr_fail
-
-            LDR R1, =data0x00000001
-            LDR R1, [R1]
-            MSR FAULTMASK, R1
-            MRS R2, FAULTMASK
-            CMP R1, R2
-            BNE _test_cpu_r14_sfr_fail
-            MSR FAULTMASK, R0
-
-            ; BASEPRI register
-            MRS R0, BASEPRI
-            LDR R1, =data0x000000A0
-            LDR R1, [R1]
-            MSR BASEPRI, R1
-            MRS R2, BASEPRI
-            CMP R1, R2
-            BNE _test_cpu_r14_sfr_fail
-
-            LDR R1, =data0x00000050
-            LDR R1, [R1]
-            MSR BASEPRI, R1
-            MRS R2, BASEPRI
-            CMP R1, R2
-            BNE _test_cpu_r14_sfr_fail
-            MSR BASEPRI, R0
-            B _test_cpu_pass
-
-_test_cpu_r14_sfr_fail
-            ; test fail, R0 will hold value 1
-            MOVS R0, #0x1                        ; STL_ERR
-            B _test_exit
-
-_test_cpu_pass
-            ; test pass, R0 will hold value 0
-            MOVS R0, #0x0                        ; STL_OK
-            B _test_exit
-
-_test_exit
-            POP {R4-R7}                          ; Restore registers
-            BX LR
-
-            END